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arch: riscv: custom: add OpenHW Group CVA6 CSR support

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CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h',
allowing other SoCs using the CVA6 core to reuse the same CSR definitions.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng
2025-07-24 14:39:44 +08:00
committed by Chris Friedt
parent 8b27ffbecc
commit a6a11cc57d
3 changed files with 17 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/riscv/custom/openhwgroup/cva6/CMakeLists.txt Normal file
View File

@@ -0,0 +1,3 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)

18
soc/openhwgroup/cva6/cva6.h → arch/riscv/custom/openhwgroup/cva6/cva6_csr.h
View File

@@ -8,8 +8,8 @@
* OpenHwGroup CVA6 declarations
*/
#ifndef ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H
#define ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H
#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_
#define ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_
#ifdef __cplusplus
extern "C" {
@@ -24,17 +24,17 @@ extern "C" {
*
*/
#define SOC_CVA6_CUSTOM_CSR_DCACHE 0x7C1
#define SOC_CVA6_CUSTOM_CSR_ICACHE 0x7C0
#define CVA6_DCACHE 0x7C1
#define CVA6_ICACHE 0x7C0
#define SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE 0x1
#define SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE 0x0
#define CVA6_DCACHE_ENABLE 0x1
#define CVA6_DCACHE_DISABLE 0x0
#define SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE 0x1
#define SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE 0x0
#define CVA6_ICACHE_ENABLE 0x1
#define CVA6_ICACHE_DISABLE 0x0
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H */
#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_ */

10
soc/openhwgroup/cva6/soc_cache_management.c
View File

@@ -9,16 +9,16 @@
#include <zephyr/arch/riscv/csr.h>
#include <zephyr/kernel.h>
#include "cva6.h"
#include <cva6_csr.h>
void __weak arch_dcache_enable(void)
{
csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE);
csr_write(CVA6_DCACHE, CVA6_DCACHE_ENABLE);
}
void __weak arch_dcache_disable(void)
{
csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE);
csr_write(CVA6_DCACHE, CVA6_DCACHE_DISABLE);
}
int __weak arch_dcache_flush_all(void)
@@ -66,12 +66,12 @@ int __weak arch_dcache_flush_and_invd_range(void *addr, size_t size)
void __weak arch_icache_enable(void)
{
csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE);
csr_write(CVA6_ICACHE, CVA6_ICACHE_ENABLE);
}
void __weak arch_icache_disable(void)
{
csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE);
csr_write(CVA6_ICACHE, CVA6_ICACHE_DISABLE);
}
int __weak arch_icache_flush_all(void)