Added a condition to check trigger type as high-level detection is not
supported by Renesas RZ external interrupt.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Disable all interrupts when the VIM interrupt controller is initialized so
that it doesn't encounter any stray interrupts that were not enabled on
Zephyr.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Supporting irqsteer using NXP HAL becomes increasingly harder with new
SoCs.
For example now there are two incompatible HAL drivers for IRQ steer
(mcux-sdk-ng/drivers/irqsteer and mcux-sdk-ng/drivers/irqsteer_1).
In order to avoid overcomplicating code and better scaling code for
newer SoCs just drop using the NXP HAL and implement an IRQ Steer native
Zephyr driver
Use irqsteer node of imx943 as example.
New features:
- Support multiple irqsteer instances.
- Indroduce new properties(nxp,irq-offset, nxp,num-irqs).
Signed-off-by: Biwen Li <biwen.li@nxp.com>
PINT connects GPIO pin to seperate IRQ slot. This info is
hidden in PINT driver, there is no way to know which IRQ
actually the GPIO pin is connected to.
Add new API to get which IRQ slot is connected to, based on
pin index.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit introduces a new comparison for the ARM (AArch32) architecture
in the GICv3 interrupt controller.
It specifically compares the lower 24 bits of the affinity values,
because there is no aff3 in AArch32 or Arm-v7.
Signed-off-by: Guowei Li <15035660024@163.com>
Similarly to what was present on L0, GPIO port indexes are not continuous
in EXTI configuration register and a dedicated treatment is required.
Deal with it case by case.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
VIM is a vector interrupt manager that TI devices have and is used a
interrupt controller. the driver's Kconfig selection is created as "VIM"
and is resulting in the confusion with a Text Editor name.
Make the VIM Kconfig option to indicate the vendor TI name in it.
Signed-off-by: Mihira Madhava Bollapragada <madhava@ti.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.
Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
- adapt for mcxe31x series
- due to some bit defined in header files
add some conditional macro to separate
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The RP2350 uses the Xh3irq interrupt controller, which supports nested
and prioritised interrupts. This adds initial support, configuring the
controller in 'direct' (non-vectored) mode.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Switch to using the new NXP_ENABLE_WAKEUP_SIGNAL and
NXP_DISABLE_WAKEUP_SIGNAL macros to avoid adding
platform specific calls in the Zephyr drivers.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The SIUL2 external interrupt driver is a native implementation usable
across all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow
clean reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Now use the 5-parameter function "PINT_PinInterruptConfig"
deprecated in MCUX SDK, need to add compile definition
'PINT_USE_LEGACY_CALBACK' to make intc_nxp_pint compatible
with updated 'fsl_pint' driver.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Update the initializers to support platforms with multiple instances
of the DesignWare interrupt aggregator. Also ensure that the initialize
function calls irq_enable(). The calculation of the _sw_isr_table entry
also now takes CONFIG_GEN_IRQ_START_VECTOR into account.
Signed-off-by: Aaron Fong <afong@tenstorrent.com>
Espressif's interrupt controller drive should not build for
ESP32C6 LP Core since it's behavior is different.
Add proper condition for that.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Create Kconfig variable NXP_INPUTMUX, which selects the fsl_inputmux
driver. Imply the MCUX component symbol from it. Imply that variable
from the NXP PINT, SmartDMA and LPC DMA drivers and from the mimxrt685s
SoC.
This needed to be done for the mimxrt700_evk/mimxrt798s/hifi4 domain, as
the INPUTMUX peripheral handles IRQ assginments and its driver
(fsl_inputmux) is used directly by the domain's soc.c. Instantiating the
currently dependent drivers (for PINT and SmartDMA) isn's possible nor
reasonable on the said target.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
GIC v3 ITS is initialized in pre-kernel stage in which sleep function
can't work yet, so use busy delay in pre-kernel stage and use sleep
delay in post-kernel stage.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
For RDbase used by its command, When GITS_TYPER.PTA = 1, physicall address
is used, the RDbase field consist of bits[51:16] of the address, so need
to left shift the address by 16 bits. But when GITS_TYPER.PTA = 0, PE
number is used, no need to shit anymore.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
GIC redistributor on Some platform are connected to a non-coherent
downstream interconnect, it need to use Non-cahable and Non-shareable
access atttributes to access external memory. And also flush the
data cache after CPU update related memory.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
rename intc_exti_stm32.c to intc_gpio_stm32.c
rename EXTI_STM32 to GPIO_INTC_STM32 in Kconfig.stm32
update CMakeLists.txt
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
Fix the non-IRAM interrupt disable routine to use non_iram_int_mask[cpu]
directly instead of its bitwise inverse. The previous implementation used
the wrong mask and could affect unrelated interrupts. This change ensures
that only intended non-IRAM interrupts are disabled and restored.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fix bitwise operation when freeing an interrupt to correctly clear the
VECDESC_FL_NONSHARED, VECDESC_FL_RESERVED, and VECDESC_FL_SHARED flags.
Also reset the interrupt source to ETS_INTERNAL_UNUSED_INTR_SOURCE to
ensure proper cleanup and prevent issues with future allocations.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Replace global lock variable with function-local storage for irq_lock()
state. This fixes a race condition when multiple access enter or exit
the critical section at the same time. Now each lock/unlock pair uses
its own key, making interrupt safe.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The WCH External Trigger and Interrupt controller (EXTI) supports
between 8 and 22 lines where each line can trigger an interrupt on
rising edge, falling edge, or both edges. Lines are assigned to a
group, and each group has a separate interrupt. On the CH32V003/6,
there is one group of 8 lines, while on the CH32V208 there are
multiple groups with between one and six lines per group.
In the same way as the STM32 and GD32, define an EXTI driver that
configures the peripheral and an internal interface that can configure
individual lines.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Prevent out-of-bounds access in nxp_pint_pin_enable by fixing the
comparison to use >= instead of >.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add the mp2 exti2 dts to the dtsi file.
Add mp2 exti hal and ll function calls with EXTI2 instance. We use the
EXTI2 instance because it contains the GPIO interrupts in the non-secure
context. (We are trying to build the blinky sample as a first milestone)
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Replace the use of `DT_NODELABEL(exti)` which depends on the node label
with the defined EXTI_NODE macro using the instance with the
`st_stm32_exti` compatible.
Since both macros point to the same node, this change doesn't affect
the code logic, but makes it independent of the node label, in
preparation for the addition of the STM32MP2 exti nodes.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
The IRER registers are write-only and clear the enable bit for the
provided interrupt. Use a direct write instead of a read/modify/write
sequence to avoid generating a bogus read access and improve performance
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.
This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.
Signed-off-by: Keith Packard <keithp@keithp.com>
Disable IRQ before connecting new handler when interrupt is not
shared. This aligns intc behavior to version before PR #87369.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Update hal_wch.
As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add drivers/interrupt_controller/intc_nxp_pint/power.h abstracting
EnableDeepSleepIRQ and DisableDeepSleepIRQ invocations from
intc_nxp_pint.c. Modify intc_nxp_pint.c to use that file.
fsl_power.c and fsl_power.h can't be built on the
mimxrt685_evk/mimxrt685s/hifi4 target, so it's excluded from it in hal_nxp.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
