Bluetooth: Controller: Fix connection update interval_us variables

Fix connection update microsecond interval variable data
type, to use 32-bit so that a value upto 2000 seconds, i.e.
4 seconds interval and 499 peripheral latency can be stored.

Regression in commit abfe5f17a9 ("Bluetooth: Controller:
1 ms connection").

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
(cherry picked from commit 0a4480ce61)

.github/workflows/assigner.yml

@@ -22,6 +22,11 @@ jobs:
     runs-on: ubuntu-22.04
 
     steps:
+    - name: Set up Python
+      uses: actions/setup-python@v5
+      with:
+        python-version: 3.12
+
     - name: Install Python dependencies
       run: |
         sudo pip3 install -U setuptools wheel pip

.github/workflows/doc-build.yml

@@ -70,6 +70,11 @@ jobs:
       cancel-in-progress: true
 
     steps:
+    - name: Set up Python
+      uses: actions/setup-python@v5
+      with:
+        python-version: 3.12
+
     - name: install-pkgs
       run: |
         sudo apt-get update
@@ -202,6 +207,11 @@ jobs:
     - name: checkout
       uses: actions/checkout@v4
 
+    - name: Set up Python
+      uses: actions/setup-python@v5
+      with:
+        python-version: 3.12
+
     - name: install-pkgs
       run: |
         apt-get update

arch/posix/core/thread.c

@@ -96,6 +96,25 @@ void posix_arch_thread_entry(void *pa_thread_status)
 	z_thread_entry(ptr->entry_point, ptr->arg1, ptr->arg2, ptr->arg3);
 }
 
+#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
+int arch_float_disable(struct k_thread *thread)
+{
+	ARG_UNUSED(thread);
+
+	/* Posix always has FPU enabled so cannot be disabled */
+	return -ENOTSUP;
+}
+
+int arch_float_enable(struct k_thread *thread, unsigned int options)
+{
+	ARG_UNUSED(thread);
+	ARG_UNUSED(options);
+
+	/* Posix always has FPU enabled so nothing to do here */
+	return 0;
+}
+#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
+
 #if defined(CONFIG_ARCH_HAS_THREAD_ABORT)
 void z_impl_k_thread_abort(k_tid_t thread)
 {

boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi

@@ -2,7 +2,7 @@
  * Copyright (c) 2017 Piotr Mienkowski
  * Copyright (c) 2017 Justin Watson
  * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
- * Copyright (c) 2019-2022 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,7 @@
 		led0 = &yellow_led1;
 		pwm-led0 = &pwm_led0;
 		pwm-0 = &pwm0;
+		rtc = &rtc;
 		sw0 = &sw0_user_button;
 		sw1 = &sw1_user_button;
 		watchdog0 = &wdt;
@@ -336,6 +337,10 @@ zephyr_udc0: &usbhs {
 	};
 };
 
+&rtc {
+	status = "okay";
+};
+
 ext1_spi: &spi0 {
 };
 

boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml

@@ -22,6 +22,7 @@ supported:
   - i2s
   - pwm
   - netif:eth
+  - rtc
   - spi
   - usb_device
   - watchdog

boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml

@@ -22,6 +22,7 @@ supported:
   - i2s
   - pwm
   - netif:eth
+  - rtc
   - spi
   - usb_device
   - watchdog

boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml

@@ -1,3 +1,6 @@
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
 identifier: samd20_xpro
 name: SAM D20 Xplained Pro
 type: mcu
@@ -9,7 +12,6 @@ toolchain:
 flash: 256
 ram: 32
 supported:
-  - adc
   - flash
   - gpio
   - i2c

boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml

@@ -1,6 +1,7 @@
 # Copyright (c) 2018 Bryan O'Donoghue
 # Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
+
 identifier: samd21_xpro
 name: SAM D21 Xplained Pro
 type: mcu
@@ -12,7 +13,6 @@ toolchain:
 flash: 256
 ram: 32
 supported:
-  - adc
   - counter
   - dma
   - gpio

boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi

@@ -1,11 +1,17 @@
 /*
- * Copyright (c) 2022, Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2022-2024, Gerson Fernando Budke <nandojve@gmail.com>
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <dt-bindings/pinctrl/samr21g-pinctrl.h>
 
 &pinctrl {
+	adc_default: adc_default {
+		group1 {
+			pinmux = <PA6B_ADC_AIN6>;
+		};
+	};
+
 	pwm_default: pwm_default {
 		group1 {
 			pinmux = <PA19F_TCC0_WO3>;

boards/atmel/sam0/samr21_xpro/samr21_xpro.dts

@@ -106,6 +106,12 @@
 	clock-frequency = <48000000>;
 };
 
+&adc {
+	status = "okay";
+	pinctrl-0 = <&adc_default>;
+	pinctrl-names = "default";
+};
+
 &tcc0 {
 	status = "okay";
 	compatible = "atmel,sam0-tcc-pwm";

boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml

@@ -1,6 +1,7 @@
 # Copyright (c) 2019 Benjamin Valentin
-# Copyright (c) 2019-2024 Gerson Fernando Budke
+# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
+
 identifier: samr21_xpro
 name: SAM R21 Xplained Pro
 type: mcu

boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig

@@ -17,6 +17,9 @@ CONFIG_UART_CONSOLE=y
 # Enable UART driver
 CONFIG_SERIAL=y
 
+# Enable GPIO driver
+CONFIG_GPIO=y
+
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
 

boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig

@@ -18,6 +18,9 @@ CONFIG_UART_CONSOLE=y
 # Enable UART driver
 CONFIG_SERIAL=y
 
+# Enable GPIO
+CONFIG_GPIO=y
+
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
 

boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig

@@ -18,6 +18,9 @@ CONFIG_UART_CONSOLE=y
 # Enable UART driver
 CONFIG_SERIAL=y
 
+# Enable GPIO driver
+CONFIG_GPIO=y
+
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
 

boards/nxp/frdm_mcxn947/board.c

@@ -190,10 +190,6 @@ static int frdm_mcxn947_init(void)
 	CLOCK_EnableClock(kCLOCK_Gpio4);
 #endif
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio5))
-	CLOCK_EnableClock(kCLOCK_Gpio5);
-#endif
-
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0))
 	SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0);
 	CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1u);

boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay

@@ -39,7 +39,7 @@
 		ahb-write-wait-unit = <2>;
 		ahb-write-wait-interval = <20>;
 		status = "okay";
-		erase-block-size = <4096>;
+		erase-block-size = <DT_SIZE_K(256)>;
 		write-block-size = <16>;
 
 		partitions {
@@ -48,22 +48,22 @@
 			#size-cells = <1>;
 			boot_partition: partition@0 {
 				label = "mcuboot";
-				reg = <0x00000000 DT_SIZE_K(128)>;
+				reg = <0x00000000 DT_SIZE_K(256)>;
 			};
-			/* The MCUBoot swap-move algorithm uses the last 11 sectors
+			/* The MCUBoot swap-move algorithm uses the last 2 sectors
 			 * of the primary slot0 for swap status and move.
 			 */
-			slot0_partition: partition@20000 {
+			slot0_partition: partition@40000 {
 				label = "image-0";
-				reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(44))>;
+				reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>;
 			};
-			slot1_partition: partition@32B000 {
+			slot1_partition: partition@3C0000 {
 				label = "image-1";
-				reg = <0x0032B000 DT_SIZE_M(3)>;
+				reg = <0x003C0000 DT_SIZE_M(3)>;
 			};
-			storage_partition: partition@62B000 {
+			storage_partition: partition@6C0000 {
 				label = "storage";
-				reg = <0x0062B000 (DT_SIZE_M(58) - DT_SIZE_K(172))>;
+				reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>;
 			};
 		};
 	};

boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay

@@ -37,7 +37,7 @@
 		ahb-write-wait-unit = <2>;
 		ahb-write-wait-interval = <20>;
 		status = "okay";
-		erase-block-size = <4096>;
+		erase-block-size = <DT_SIZE_K(256)>;
 		write-block-size = <16>;
 
 		partitions {
@@ -46,22 +46,22 @@
 			#size-cells = <1>;
 			boot_partition: partition@0 {
 				label = "mcuboot";
-				reg = <0x00000000 DT_SIZE_K(128)>;
+				reg = <0x00000000 DT_SIZE_K(256)>;
 			};
-			/* The MCUBoot swap-move algorithm uses the last 11 sectors
+			/* The MCUBoot swap-move algorithm uses the last 2 sectors
 			 * of the primary slot0 for swap status and move.
 			 */
-			slot0_partition: partition@20000 {
+			slot0_partition: partition@40000 {
 				label = "image-0";
-				reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(44))>;
+				reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>;
 			};
-			slot1_partition: partition@32B000 {
+			slot1_partition: partition@3C0000 {
 				label = "image-1";
-				reg = <0x0032B000 DT_SIZE_M(3)>;
+				reg = <0x003C0000 DT_SIZE_M(3)>;
 			};
-			storage_partition: partition@62B000 {
+			storage_partition: partition@6C0000 {
 				label = "storage";
-				reg = <0x0062B000 (DT_SIZE_M(58) - DT_SIZE_K(172))>;
+				reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>;
 			};
 		};
 	};

boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts

@@ -200,7 +200,7 @@
 		ahb-write-wait-unit = <2>;
 		ahb-write-wait-interval = <20>;
 		status = "okay";
-		erase-block-size = <4096>;
+		erase-block-size = <DT_SIZE_K(256)>;
 		write-block-size = <16>;
 
 		partitions {
@@ -209,22 +209,22 @@
 			#size-cells = <1>;
 			boot_partition: partition@0 {
 				label = "mcuboot";
-				reg = <0x00000000 DT_SIZE_K(128)>;
+				reg = <0x00000000 DT_SIZE_K(256)>;
 			};
-			/* The MCUBoot swap-move algorithm uses the last 11 sectors
+			/* The MCUBoot swap-move algorithm uses the last 2 sectors
 			 * of the primary slot0 for swap status and move.
 			 */
-			slot0_partition: partition@20000 {
+			slot0_partition: partition@40000 {
 				label = "image-0";
-				reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(44))>;
+				reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>;
 			};
-			slot1_partition: partition@32B000 {
+			slot1_partition: partition@3C0000 {
 				label = "image-1";
-				reg = <0x0032B000 DT_SIZE_M(3)>;
+				reg = <0x003C0000 DT_SIZE_M(3)>;
 			};
-			storage_partition: partition@62B000 {
+			storage_partition: partition@6C0000 {
 				label = "storage";
-				reg = <0x0062B000 (DT_SIZE_M(58) - DT_SIZE_K(172))>;
+				reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>;
 			};
 		};
 	};

boards/st/disco_l475_iot1/arduino_r3_connector.dtsi

@@ -35,6 +35,6 @@
 	};
 };
 
-arduino_i2c: &i2c3 {};
+arduino_i2c: &i2c1 {};
 arduino_spi: &spi1 {};
 arduino_serial: &uart4 {};

cmake/modules/extensions.cmake

@@ -3251,8 +3251,9 @@ function(zephyr_get variable)
       set(sysbuild_global_${var})
     endif()
 
-    if(TARGET snippets_scope)
-      get_property(snippets_${var} TARGET snippets_scope PROPERTY ${var})
+    zephyr_scope_exists(scope_defined snippets)
+    if(scope_defined)
+      zephyr_get_scoped(snippets_${var} snippets ${var})
     endif()
   endforeach()
 
@@ -3317,11 +3318,54 @@ endfunction(zephyr_get variable)
 # <scope>: Name of new scope.
 #
 function(zephyr_create_scope scope)
-  if(TARGET ${scope}_scope)
+  zephyr_scope_exists(scope_defined ${scope})
+  if(scope_defined)
     message(FATAL_ERROR "zephyr_create_scope(${scope}) already exists.")
   endif()
 
-  add_custom_target(${scope}_scope)
+  set_property(GLOBAL PROPERTY scope:${scope} TRUE)
+endfunction()
+
+# Usage:
+#   zephyr_scope_exists(<result> <scope>)
+#
+# Check if <scope> exists.
+#
+# <result>: Variable to set with result.
+#           TRUE if scope exists, FALSE otherwise.
+# <scope> : Name of scope.
+#
+function(zephyr_scope_exists result scope)
+  get_property(scope_defined GLOBAL PROPERTY scope:${scope})
+  if(scope_defined)
+    set(${result} TRUE PARENT_SCOPE)
+  else()
+    set(${result} FALSE PARENT_SCOPE)
+  endif()
+endfunction()
+
+# Usage:
+#   zephyr_get_scoped(<output> <scope> <var>)
+#
+# Get the current value of <var> in a specific <scope>, as defined by a
+# previous zephyr_set() call. The value will be stored in the <output> var.
+#
+# <output> : Variable to store the value in
+# <scope>  : Scope for the variable look up
+# <var>    : Name to look up in the specific scope
+#
+function(zephyr_get_scoped output scope var)
+  zephyr_scope_exists(scope_defined ${scope})
+  if(NOT scope_defined)
+    message(FATAL_ERROR "zephyr_get_scoped(): scope ${scope} doesn't exists.")
+  endif()
+
+  get_property(value GLOBAL PROPERTY ${scope}_scope:${var})
+  if(DEFINED value)
+    set(${output} "${value}" PARENT_SCOPE)
+  else()
+    unset(${output} PARENT_SCOPE)
+  endif()
 endfunction()
 
 # Usage:
@@ -3342,7 +3386,8 @@ function(zephyr_set variable)
 
   zephyr_check_arguments_required_all(zephyr_set SET_VAR SCOPE)
 
-  if(NOT TARGET ${SET_VAR_SCOPE}_scope)
+  zephyr_scope_exists(scope_defined ${SET_VAR_SCOPE})
+  if(NOT scope_defined)
     message(FATAL_ERROR "zephyr_set(... SCOPE ${SET_VAR_SCOPE}) doesn't exists.")
   endif()
 
@@ -3350,8 +3395,8 @@ function(zephyr_set variable)
     set(property_args APPEND)
   endif()
 
-  set_property(TARGET ${SET_VAR_SCOPE}_scope ${property_args}
-               PROPERTY ${variable} ${SET_VAR_UNPARSED_ARGUMENTS}
+  set_property(GLOBAL ${property_args} PROPERTY
+               ${SET_VAR_SCOPE}_scope:${variable} ${SET_VAR_UNPARSED_ARGUMENTS}
   )
 endfunction()
 
@@ -5871,16 +5916,11 @@ if(CMAKE_SCRIPT_MODE_FILE)
     # This silence the error: 'set_target_properties command is not scriptable'
   endfunction()
 
-  function(zephyr_set variable)
-    # This silence the error: zephyr_set(...  SCOPE <scope>) doesn't exists.
-  endfunction()
-
   # Build info creates a custom target for handling of build info.
   # build_info is not needed in script mode but still called by Zephyr CMake
   # modules. Therefore disable build_info(...) in when including
   # extensions.cmake in script mode.
   function(build_info)
-    # This silence the error: 'YAML context 'build_info' does not exist.'
-    #                         'Remember to create a YAML context'
+    # This silence the error: 'Unknown CMake command "yaml_context"'
   endfunction()
 endif()

cmake/modules/yaml.cmake

@@ -93,7 +93,8 @@ function(yaml_context)
     )
   endif()
 
-  if(TARGET ${ARG_YAML_NAME}_scope)
+  zephyr_scope_exists(scope_defined ${ARG_YAML_NAME})
+  if(scope_defined)
     list(POP_FRONT ARG_YAML_UNPARSED_ARGUMENTS out-var)
     set(${out-var} TRUE PARENT_SCOPE)
   else()
@@ -183,7 +184,7 @@ function(yaml_get out_var)
   zephyr_check_arguments_required_all(${CMAKE_CURRENT_FUNCTION} ARG_YAML NAME KEY)
   internal_yaml_context_required(NAME ${ARG_YAML_NAME})
 
-  get_property(json_content TARGET ${ARG_YAML_NAME}_scope PROPERTY JSON)
+  zephyr_get_scoped(json_content ${ARG_YAML_NAME} JSON)
 
   # We specify error variable to avoid a fatal error.
   # If key is not found, then type becomes '-NOTFOUND' and value handling is done below.
@@ -224,7 +225,7 @@ function(yaml_length out_var)
   zephyr_check_arguments_required_all(${CMAKE_CURRENT_FUNCTION} ARG_YAML NAME KEY)
   internal_yaml_context_required(NAME ${ARG_YAML_NAME})
 
-  get_property(json_content TARGET ${ARG_YAML_NAME}_scope PROPERTY JSON)
+  zephyr_get_scoped(json_content ${ARG_YAML_NAME} JSON)
 
   string(JSON type ERROR_VARIABLE error TYPE "${json_content}" ${ARG_YAML_KEY})
   if(type STREQUAL ARRAY)
@@ -262,7 +263,7 @@ function(yaml_set)
   zephyr_check_arguments_exclusive(${CMAKE_CURRENT_FUNCTION} ARG_YAML VALUE LIST)
   internal_yaml_context_required(NAME ${ARG_YAML_NAME})
 
-  get_property(json_content TARGET ${ARG_YAML_NAME}_scope PROPERTY JSON)
+  zephyr_get_scoped(json_content ${ARG_YAML_NAME} JSON)
 
   set(yaml_key_undefined ${ARG_YAML_KEY})
   foreach(k ${yaml_key_undefined})
@@ -335,7 +336,7 @@ function(yaml_remove)
   zephyr_check_arguments_required_all(${CMAKE_CURRENT_FUNCTION} ARG_YAML NAME KEY)
   internal_yaml_context_required(NAME ${ARG_YAML_NAME})
 
-  get_property(json_content TARGET ${ARG_YAML_NAME}_scope PROPERTY JSON)
+  zephyr_get_scoped(json_content ${ARG_YAML_NAME} JSON)
   string(JSON json_content REMOVE "${json_content}" ${ARG_YAML_KEY})
 
   zephyr_set(JSON "${json_content}" SCOPE ${ARG_YAML_NAME})
@@ -359,18 +360,18 @@ function(yaml_save)
   zephyr_check_arguments_required(${CMAKE_CURRENT_FUNCTION} ARG_YAML NAME)
   internal_yaml_context_required(NAME ${ARG_YAML_NAME})
 
-  get_target_property(yaml_file ${ARG_YAML_NAME}_scope FILE)
+  zephyr_get_scoped(yaml_file ${ARG_YAML_NAME} FILE)
   if(NOT yaml_file)
     zephyr_check_arguments_required(${CMAKE_CURRENT_FUNCTION} ARG_YAML FILE)
   endif()
 
-  get_property(json_content TARGET ${ARG_YAML_NAME}_scope PROPERTY JSON)
+  zephyr_get_scoped(json_content ${ARG_YAML_NAME} JSON)
   to_yaml("${json_content}" 0 yaml_out)
 
   if(DEFINED ARG_YAML_FILE)
     set(yaml_file ${ARG_YAML_FILE})
   else()
-    get_property(yaml_file TARGET ${ARG_YAML_NAME}_scope PROPERTY FILE)
+    zephyr_get_scoped(yaml_file ${ARG_YAML_NAME} FILE)
   endif()
   if(EXISTS ${yaml_file})
     FILE(RENAME ${yaml_file} ${yaml_file}.bak)

doc/_static/css/custom.css

@@ -921,6 +921,10 @@ dark-mode-toggle::part(toggleLabel){
   font-size: unset;
 }
 
+div.graphviz > object {
+    filter: var(--graphviz-filter);
+}
+
 /* Home page grid display */
 .grid {
     list-style-type: none !important;

doc/_static/css/dark.css

@@ -93,4 +93,6 @@
     --btn-neutral-background-color: #404040;
     --btn-neutral-hover-background-color: #505050;
     --footer-color: #aaa;
+
+    --graphviz-filter: invert(0.9) brightness(1.2);
 }

doc/_static/css/light.css

@@ -91,4 +91,6 @@
     --btn-neutral-background-color: #f3f6f6;
     --btn-neutral-hover-background-color: #e5ebeb;
     --footer-color: #808080;
+
+    --graphviz-filter: none;
 }

doc/_templates/zversions.html

@@ -2,7 +2,7 @@
   <div class="rst-versions" data-toggle="rst-versions" role="note" aria-label="versions">
     <span class="rst-current-version" data-toggle="rst-current-version">
       <span class="fa fa-book"> Zephyr Project</span>
-      v: latest
+      v: {{ current_version if is_release else "latest" }}
       <span class="fa fa-caret-down"></span>
     </span>
     <div class="rst-other-versions">

doc/conf.py

@@ -325,6 +325,9 @@ graphviz_dot_args = [
     "-Ncolor=gray60",
     "-Nfontcolor=gray25",
     "-Ecolor=gray60",
+    "-Gfontname=system-ui,-apple-system,Segoe UI,Roboto,Helvetica Neue,Arial,Noto Sans,sans-serif",
+    "-Nfontname=system-ui,-apple-system,Segoe UI,Roboto,Helvetica Neue,Arial,Noto Sans,sans-serif",
+    "-Efontname=SFMono-Regular,Menlo,Monaco,Consolas,Liberation Mono,Courier New,Courier,monospace",
 ]
 
 # -- Options for sphinx_copybutton ----------------------------------------

doc/releases/release-notes-4.0.rst

@@ -2,6 +2,48 @@
 
 .. _zephyr_4.0:
 
+.. _zephyr_4.0.1:
+
+Zephyr 4.0.1
+############
+
+This is an LTS maintenance release with fixes.
+
+Security Vulnerability Related
+******************************
+
+The following CVEs are addressed by this release:
+
+* :cve:`2025-27809` `TLS clients may unwittingly skip server authentication
+  <https://mbed-tls.readthedocs.io/en/latest/security-advisories/mbedtls-security-advisory-2025-03-1/>`_
+* :cve:`2025-27810` `Potential authentication bypass in TLS handshake
+  <https://mbed-tls.readthedocs.io/en/latest/security-advisories/mbedtls-security-advisory-2025-03-2/>`_
+
+More detailed information can be found in:
+https://docs.zephyrproject.org/latest/security/vulnerabilities.html
+
+Issues fixed
+************
+
+These GitHub issues were addressed since the previous 4.0.0 tagged release:
+
+Mbed TLS
+********
+
+Mbed TLS was updated to version 3.6.3 (from 3.6.2). The release notes can be found at:
+https://github.com/Mbed-TLS/mbedtls/releases/tag/mbedtls-3.6.3
+
+Mbed TLS 3.6 is an LTS release that will be supported
+with security and bug fixes until at least March 2027.
+
+Trusted Firmware-M (TF-M)
+*************************
+
+TF-M was updated to version 2.1.2 (from 2.1.1). The release notes can be found at:
+https://trustedfirmware-m.readthedocs.io/en/tf-mv2.1.2/releases/2.1.2.html
+
+.. _zephyr_4.0.0:
+
 Zephyr 4.0.0
 ############
 

doc/zephyr.doxyfile.in

@@ -279,7 +279,7 @@ TAB_SIZE               = 8
 # with the commands \{ and \} for these it is advised to use the version @{ and
 # @} or use a double escape (\\{ and \\})
 
-ALIASES                = "kconfig{1}=\verbatim \1 \endverbatim" \
+ALIASES                = "kconfig{1}=\c \1" \
                          "req{1}=\ref ZEPH_\1 \"ZEPH-\1\"" \
                          "satisfy{1}=\xrefitem satisfy \"Satisfies requirement\" \"Requirement Implementation\" \1" \
                          "verify{1}=\xrefitem verify \"Verifies requirement\" \"Requirement Verification\" \1" \

drivers/auxdisplay/auxdisplay_jhd1313.c

@@ -205,7 +205,7 @@ static int auxdisplay_jhd1313_backlight_set(const struct device *dev, uint8_t co
 	const struct auxdisplay_jhd1313_config *config = dev->config;
 	struct auxdisplay_jhd1313_data *data = dev->data;
 
-	if (colour > ARRAY_SIZE(colour_define)) {
+	if (colour >= ARRAY_SIZE(colour_define)) {
 		LOG_WRN("Selected colour is too high a value");
 		return -EINVAL;
 	}

drivers/can/can_tcan4x5x.c

@@ -508,8 +508,10 @@ static int tcan4x5x_wake(const struct device *dev)
 
 static int tcan4x5x_reset(const struct device *dev)
 {
+#if TCAN4X5X_RST_GPIO_SUPPORT
 	const struct can_mcan_config *mcan_config = dev->config;
 	const struct tcan4x5x_config *tcan_config = mcan_config->custom;
+#endif /* TCAN4X5X_RST_GPIO_SUPPORT */
 	int err;
 
 	err = tcan4x5x_wake(dev);

drivers/entropy/fake_entropy_native_posix.c

@@ -42,7 +42,10 @@ static int entropy_native_posix_get_entropy(const struct device *dev,
 		 */
 		long value = nsi_host_random();
 
-		size_t to_copy = MIN(length, sizeof(long int));
+		/* The host random() provides a number between 0 and 2**31-1. Bit 32 is always 0.
+		 * So let's just use the lower 3 bytes discarding the upper 7 bits
+		 */
+		size_t to_copy = MIN(length, 3);
 
 		memcpy(buffer, &value, to_copy);
 		buffer += to_copy;

drivers/ethernet/eth_stm32_hal.c

@@ -56,7 +56,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 
 #define PHY_ADDR	CONFIG_ETH_STM32_HAL_PHY_ADDRESS
 
-#if defined(CONFIG_MDIO)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_mdio)
 
 #define DEVICE_PHY_BY_NAME(n) \
 	    DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(n, mdio), _CONCAT(ethernet_phy_, PHY_ADDR)))
@@ -239,7 +239,7 @@ static HAL_StatusTypeDef read_eth_phy_register(ETH_HandleTypeDef *heth,
 						uint32_t PHYReg,
 						uint32_t *RegVal)
 {
-#if defined(CONFIG_MDIO)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_mdio)
 	return phy_read(eth_stm32_phy_dev, PHYReg, RegVal);
 #elif defined(CONFIG_ETH_STM32_HAL_API_V2)
 	return HAL_ETH_ReadPHYRegister(heth, PHYAddr, PHYReg, RegVal);

drivers/flash/flash_handlers.c

@@ -31,7 +31,7 @@ static inline int z_vrfy_flash_write(const struct device *dev, off_t offset,
 static inline int z_vrfy_flash_erase(const struct device *dev, off_t offset,
 				     size_t size)
 {
-	K_OOPS(K_SYSCALL_DRIVER_FLASH(dev, erase));
+	K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_FLASH));
 	return z_impl_flash_erase((const struct device *)dev, offset, size);
 }
 #include <zephyr/syscalls/flash_erase_mrsh.c>

drivers/flash/flash_mcux_flexspi_nor.c

@@ -944,8 +944,10 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 	}
 
 	/* Switch on manufacturer and vendor ID */
-	switch (vendor_id & 0xFFFF) {
-	case 0x609d: /* IS25LP flash, needs P[4:3] cleared with same method as IS25WP */
+	switch (vendor_id & 0xFFFFFF) {
+	case 0x16609d: /* IS25LP032 flash, needs P[4:3] cleared with same method as IS25WP */
+	case 0x17609d: /* IS25LP064 */
+	case 0x18609d: /* IS25LP128 */
 		read_params = 0xE0U;
 		ret = flash_flexspi_nor_is25_clear_read_param(data, flexspi_lut, &read_params);
 		if (ret < 0) {
@@ -959,7 +961,9 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 		}
 		/* Still return an error- we want the JEDEC configuration to run */
 		return -ENOTSUP;
-	case 0x709d:
+	case 0x16709d: /* IS25WP032 */
+	case 0x17709d: /* IS25WP064 */
+	case 0x18709d: /* IS25WP128 */
 		/*
 		 * IS25WP flash. We can support this flash with the JEDEC probe,
 		 * but we need to insure P[6:3] are at the default value
@@ -977,15 +981,8 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 		}
 		/* Still return an error- we want the JEDEC configuration to run */
 		return -ENOTSUP;
-	case 0x40ef:
-		if ((vendor_id & 0xFFFFFF) != 0x2040ef) {
-			/*
-			 * This is not the correct flash chip, and will not
-			 * support the LUT table. Return here
-			 */
-			return -ENOTSUP;
-		}
-		/* W25Q512JV flash, use 4 byte read/write */
+	case 0x2040ef:
+		/* W25Q512JV-IQ/IN flash, use 4 byte read/write */
 		flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
 				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
 				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
@@ -1015,14 +1012,7 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 		/* Device uses bit 1 of status reg 2 for QE */
 		return flash_flexspi_nor_quad_enable(data, flexspi_lut,
 						     JESD216_DW15_QER_VAL_S2B1v5);
-	case 0x60ef:
-		if ((vendor_id & 0xFFFFFF) != 0x2060ef) {
-			/*
-			 * This is not the correct flash chip, and will not
-			 * support the LUT table. Return here
-			 */
-			return -ENOTSUP;
-		}
+	case 0x2060ef:
 		/* W25Q512NW-IQ/IN flash, use 4 byte read/write */
 		flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
 				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
@@ -1053,8 +1043,8 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 		/* Device uses bit 1 of status reg 2 for QE */
 		return flash_flexspi_nor_quad_enable(data, flexspi_lut,
 						     JESD216_DW15_QER_VAL_S2B1v5);
-	case 0x25C2:
-		/* MX25 flash, use 4 byte read/write */
+	case 0x3A25C2:
+		/* MX25U51245G flash, use 4 byte read/write */
 		flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
 				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
 				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);

drivers/flash/soc_flash_mcux.c

@@ -93,7 +93,7 @@ static uint32_t get_cmd_status(uint32_t cmd, uint32_t addr, size_t len)
 }
 
 /* This function prevents erroneous reading. Some ECC enabled devices will
- * crash when reading an erased or wrongly programmed area.
+ * crash when reading an erased area.
  */
 static status_t is_area_readable(uint32_t addr, size_t len)
 {
@@ -102,21 +102,13 @@ static status_t is_area_readable(uint32_t addr, size_t len)
 
 	key = irq_lock();
 
-	/* Check if the are is correctly programmed and can be read. */
-	status = get_cmd_status(FMC_CMD_MARGIN_CHECK, addr, len);
-	if (status & FMC_STATUS_FAILURES) {
-		/* If the area was erased, ECC errors are triggered on read. */
-		status = get_cmd_status(FMC_CMD_BLANK_CHECK, addr, len);
-		if (!(status & FMC_STATUS_FAIL)) {
-			LOG_DBG("read request on erased addr:0x%08x size:%d",
-				addr, len);
-			irq_unlock(key);
-			return -ENODATA;
-		}
-		LOG_DBG("read request error for addr:0x%08x size:%d",
+	/* If the area was erased, ECC errors are triggered on read. */
+	status = get_cmd_status(FMC_CMD_BLANK_CHECK, addr, len);
+	if (!(status & FMC_STATUS_FAIL)) {
+		LOG_DBG("read request on erased addr:0x%08x size:%d",
 			addr, len);
 		irq_unlock(key);
-		return -EIO;
+		return -ENODATA;
 	}
 
 	irq_unlock(key);

drivers/gpio/gpio_adp5585.c

@@ -143,14 +143,14 @@ static int gpio_adp5585_config(const struct device *dev, gpio_pin_t pin, gpio_fl
 			data->output |= BIT(pin);
 		}
 		if (bank == 0) {
-			/* reg_value for ADP5585_GPO_OUT_MODE */
+			/* reg_value for ADP5585_GPO_DATA_OUT */
 			reg_value = (uint8_t)data->output;
 		} else {
-			/* reg_value for ADP5585_GPO_OUT_MODE */
+			/* reg_value for ADP5585_GPO_DATA_OUT */
 			reg_value = (uint8_t)(data->output >> 8);
 		}
 		ret = i2c_reg_write_byte_dt(&parent_cfg->i2c_bus,
-					ADP5585_GPO_OUT_MODE_A + bank,
+					ADP5585_GPO_DATA_OUT_A + bank,
 					reg_value);
 		if (ret != 0) {
 			goto out;

drivers/i2c/target/eeprom_target.c

@@ -179,9 +179,19 @@ static void eeprom_target_buf_write_received(struct i2c_target_config *config,
 	struct i2c_eeprom_target_data *data = CONTAINER_OF(config,
 						struct i2c_eeprom_target_data,
 						config);
-	/* The first byte is offset */
-	data->buffer_idx = *ptr;
-	memcpy(&data->buffer[data->buffer_idx], ptr + 1, len - 1);
+	/* The first byte(s) is offset */
+	uint32_t idx_write_cnt = 0;
+
+	data->buffer_idx = 0;
+	while (idx_write_cnt < (data->address_width >> 3)) {
+		data->buffer_idx = (data->buffer_idx << 8) | *ptr++;
+		len--;
+		idx_write_cnt++;
+	}
+
+	if (len > 0) {
+		memcpy(&data->buffer[data->buffer_idx], ptr, len);
+	}
 }
 
 static int eeprom_target_buf_read_requested(struct i2c_target_config *config,

drivers/led/lp50xx.c

@@ -153,7 +153,8 @@ static int lp50xx_set_color(const struct device *dev, uint32_t led,
 {
 	const struct lp50xx_config *config = dev->config;
 	const struct led_info *led_info = lp50xx_led_to_info(config, led);
-	uint8_t buf[4];
+	uint8_t buf[LP50XX_COLORS_PER_LED + 1];
+	uint8_t i;
 
 	if (!led_info) {
 		return -ENODEV;
@@ -170,11 +171,11 @@ static int lp50xx_set_color(const struct device *dev, uint32_t led,
 	buf[0] = LP50XX_OUT0_COLOR(config->num_modules);
 	buf[0] += LP50XX_COLORS_PER_LED * led_info->index;
 
-	buf[1] = color[0];
-	buf[2] = color[1];
-	buf[3] = color[2];
+	for (i = 0; i < led_info->num_colors; i++) {
+		buf[1 + i] = color[i];
+	}
 
-	return i2c_write_dt(&config->bus, buf, sizeof(buf));
+	return i2c_write_dt(&config->bus, buf, led_info->num_colors + 1);
 }
 
 static int lp50xx_write_channels(const struct device *dev,
@@ -266,6 +267,7 @@ static int lp50xx_enable(const struct device *dev, bool enable)
 static int lp50xx_init(const struct device *dev)
 {
 	const struct lp50xx_config *config = dev->config;
+	uint8_t led;
 	int err;
 
 	if (!i2c_is_ready_dt(&config->bus)) {
@@ -273,6 +275,7 @@ static int lp50xx_init(const struct device *dev)
 		return -ENODEV;
 	}
 
+	/* Check LED configuration found in DT */
 	if (config->num_leds > config->max_leds) {
 		LOG_ERR("%s: invalid number of LEDs %d (max %d)",
 			dev->name,
@@ -280,6 +283,16 @@ static int lp50xx_init(const struct device *dev)
 			config->max_leds);
 		return -EINVAL;
 	}
+	for (led = 0; led < config->num_leds; led++) {
+		const struct led_info *led_info =
+			lp50xx_led_to_info(config, led);
+
+		if (led_info->num_colors > LP50XX_COLORS_PER_LED) {
+			LOG_ERR("%s: LED %d: invalid number of colors (max %d)",
+				dev->name, led, LP50XX_COLORS_PER_LED);
+			return -EINVAL;
+		}
+	}
 
 	/* Configure GPIO if present */
 	if (config->gpio_enable.port != NULL) {

drivers/retained_mem/retained_mem_nrf_ram_ctrl.c

@@ -11,7 +11,7 @@
 
 #define _BUILD_MEM_REGION(node_id)		    \
 	{.dt_addr = DT_REG_ADDR(DT_PARENT(node_id)),\
-	 .dt_size = DT_REG_SIZE(DT_PARENT(node_id))}
+	 .dt_size = DT_REG_SIZE(DT_PARENT(node_id))},
 
 struct ret_mem_region {
 	uintptr_t dt_addr;

drivers/sensor/adi/adxl345/Kconfig

@@ -37,7 +37,6 @@ endchoice
 config ADXL345_STREAM
 	bool "Use FIFO to stream data"
 	select ADXL345_TRIGGER
-	default y
 	depends on SPI_RTIO
 	depends on SENSOR_ASYNC_API
 	help

drivers/sensor/adi/adxl345/adxl345.c

@@ -229,7 +229,7 @@ static int adxl345_attr_set_odr(const struct device *dev,
 				const struct sensor_value *val)
 {
 	enum adxl345_odr odr;
-	struct adxl345_dev_config *cfg = (struct adxl345_dev_config *)dev->config;
+	struct adxl345_dev_data *data = dev->data;
 
 	switch (val->val1) {
 	case 12:
@@ -257,7 +257,7 @@ static int adxl345_attr_set_odr(const struct device *dev,
 	int ret = adxl345_set_odr(dev, odr);
 
 	if (ret == 0) {
-		cfg->odr = odr;
+		data->odr = odr;
 	}
 
 	return ret;
@@ -281,6 +281,7 @@ int adxl345_read_sample(const struct device *dev,
 {
 	int16_t raw_x, raw_y, raw_z;
 	uint8_t axis_data[6], status1;
+	struct adxl345_dev_data *data = dev->data;
 
 	if (!IS_ENABLED(CONFIG_ADXL345_TRIGGER)) {
 		do {
@@ -303,6 +304,9 @@ int adxl345_read_sample(const struct device *dev,
 	sample->y = raw_y;
 	sample->z = raw_z;
 
+	sample->selected_range = data->selected_range;
+	sample->is_full_res = data->is_full_res;
+
 	return 0;
 }
 
@@ -453,11 +457,13 @@ static int adxl345_init(const struct device *dev)
 		return -ENODEV;
 	}
 
+#if CONFIG_ADXL345_STREAM
 	rc = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, ADXL345_FIFO_STREAM_MODE);
 	if (rc < 0) {
 		LOG_ERR("FIFO enable failed\n");
 		return -EIO;
 	}
+#endif
 
 	rc = adxl345_reg_write_byte(dev, ADXL345_DATA_FORMAT_REG, ADXL345_RANGE_8G);
 	if (rc < 0) {

drivers/sensor/adi/adxl345/adxl345.h

@@ -153,6 +153,7 @@ struct adxl345_dev_data {
 	struct adxl345_fifo_config fifo_config;
 	uint8_t is_full_res;
 	uint8_t selected_range;
+	enum adxl345_odr odr;
 #ifdef CONFIG_ADXL345_TRIGGER
 	struct gpio_callback gpio_cb;
 
@@ -201,6 +202,7 @@ struct adxl345_sample {
 	uint8_t res: 7;
 #endif /* CONFIG_ADXL345_STREAM */
 	uint8_t selected_range;
+	bool is_full_res;
 	int16_t x;
 	int16_t y;
 	int16_t z;

drivers/sensor/adi/adxl345/adxl345_decoder.c

@@ -6,17 +6,42 @@
 
 #include "adxl345.h"
 
-#ifdef CONFIG_ADXL345_STREAM
+/** The q-scale factor will always be the same, as the nominal LSB/g
+ * changes at the same rate the selected shift parameter per range:
+ *
+ * - At 2G: 256 LSB/g, 10-bits resolution.
+ * - At 4g: 128 LSB/g, 10-bits resolution.
+ * - At 8g: 64 LSB/g, 10-bits resolution.
+ * - At 16g 32 LSB/g, 10-bits resolution.
+ */
+static const uint32_t qscale_factor_no_full_res[] = {
+	/* (1.0 / Resolution-LSB-per-g * (2^31 / 2^5) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_2G] = UINT32_C(2570754),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^6) * SENSOR_G / 1000000  */
+	[ADXL345_RANGE_4G] = UINT32_C(2570754),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^7) ) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_8G] = UINT32_C(2570754),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^8) ) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_16G] = UINT32_C(2570754),
+};
 
-#define SENSOR_SCALING_FACTOR (SENSOR_G / (16 * 1000 / 100))
 
-static const uint32_t accel_period_ns[] = {
-	[ADXL345_ODR_12HZ] = UINT32_C(1000000000) / 12,
-	[ADXL345_ODR_25HZ] = UINT32_C(1000000000) / 25,
-	[ADXL345_ODR_50HZ] = UINT32_C(1000000000) / 50,
-	[ADXL345_ODR_100HZ] = UINT32_C(1000000000) / 100,
-	[ADXL345_ODR_200HZ] = UINT32_C(1000000000) / 200,
-	[ADXL345_ODR_400HZ] = UINT32_C(1000000000) / 400,
+/** Sensitivities based on Range:
+ *
+ * - At 2G: 256 LSB/g, 10-bits resolution.
+ * - At 4g: 256 LSB/g, 11-bits resolution.
+ * - At 8g: 256 LSB/g, 12-bits resolution.
+ * - At 16g 256 LSB/g, 13-bits resolution.
+ */
+static const uint32_t qscale_factor_full_res[] = {
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^5) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_2G] = UINT32_C(2570754),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^6) * SENSOR_G / 1000000  */
+	[ADXL345_RANGE_4G] = UINT32_C(1285377),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^7) ) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_8G] = UINT32_C(642688),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^8) ) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_16G] = UINT32_C(321344),
 };
 
 static const uint32_t range_to_shift[] = {
@@ -26,30 +51,6 @@ static const uint32_t range_to_shift[] = {
 	[ADXL345_RANGE_16G] = 8,
 };
 
-/* (1 / sensitivity) * (pow(2,31) / pow(2,shift)) * (unit_scaler) */
-static const uint32_t qscale_factor_no_full_res[] = {
-	/* (1.0 / ADXL362_ACCEL_2G_LSB_PER_G) * (2^31 / 2^5) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_2G] = UINT32_C(2569011),
-	/* (1.0 / ADXL362_ACCEL_4G_LSB_PER_G) * (2^31 / 2^6) * SENSOR_G / 1000000  */
-	[ADXL345_RANGE_4G] = UINT32_C(642253),
-	/* (1.0 / ADXL362_ACCEL_8G_LSB_PER_G) * (2^31 / 2^7) ) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_8G] = UINT32_C(160563),
-	/* (1.0 / ADXL362_ACCEL_8G_LSB_PER_G) * (2^31 / 2^8) ) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_16G] = UINT32_C(40141),
-};
-
-/* (1 / sensitivity) * (pow(2,31) / pow(2,shift)) * (unit_scaler) */
-static const uint32_t qscale_factor_full_res[] = {
-	/* (1.0 / ADXL362_ACCEL_2G_LSB_PER_G) * (2^31 / 2^5) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_2G] = UINT32_C(2569011),
-	/* (1.0 / ADXL362_ACCEL_4G_LSB_PER_G) * (2^31 / 2^6) * SENSOR_G / 1000000  */
-	[ADXL345_RANGE_4G] = UINT32_C(1284506),
-	/* (1.0 / ADXL362_ACCEL_8G_LSB_PER_G) * (2^31 / 2^7) ) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_8G] = UINT32_C(642253),
-	/* (1.0 / ADXL362_ACCEL_8G_LSB_PER_G) * (2^31 / 2^8) ) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_16G] = UINT32_C(321126),
-};
-
 static inline void adxl345_accel_convert_q31(q31_t *out, int16_t sample, int32_t range,
 					uint8_t is_full_res)
 {
@@ -76,15 +77,28 @@ static inline void adxl345_accel_convert_q31(q31_t *out, int16_t sample, int32_t
 			}
 			break;
 		}
+		*out = sample * qscale_factor_full_res[range];
 	} else {
 		if (sample & BIT(9)) {
 			sample |= ADXL345_COMPLEMENT;
 		}
+		*out = sample * qscale_factor_no_full_res[range];
 	}
-
-	*out = sample * qscale_factor_no_full_res[range];
 }
 
+#ifdef CONFIG_ADXL345_STREAM
+
+#define SENSOR_SCALING_FACTOR (SENSOR_G / (16 * 1000 / 100))
+
+static const uint32_t accel_period_ns[] = {
+	[ADXL345_ODR_12HZ] = UINT32_C(1000000000) / 12,
+	[ADXL345_ODR_25HZ] = UINT32_C(1000000000) / 25,
+	[ADXL345_ODR_50HZ] = UINT32_C(1000000000) / 50,
+	[ADXL345_ODR_100HZ] = UINT32_C(1000000000) / 100,
+	[ADXL345_ODR_200HZ] = UINT32_C(1000000000) / 200,
+	[ADXL345_ODR_400HZ] = UINT32_C(1000000000) / 400,
+};
+
 static int adxl345_decode_stream(const uint8_t *buffer, struct sensor_chan_spec chan_spec,
 				 uint32_t *fit, uint16_t max_count, void *data_out)
 {
@@ -208,7 +222,12 @@ static int adxl345_decode_sample(const struct adxl345_sample *data,
 				 struct sensor_chan_spec chan_spec, uint32_t *fit,
 				 uint16_t max_count, void *data_out)
 {
-	struct sensor_value *out = (struct sensor_value *)data_out;
+	struct sensor_three_axis_data *out = (struct sensor_three_axis_data *)data_out;
+
+	memset(out, 0, sizeof(struct sensor_three_axis_data));
+	out->header.base_timestamp_ns = k_ticks_to_ns_floor64(k_uptime_ticks());
+	out->header.reading_count = 1;
+	out->shift = range_to_shift[data->selected_range];
 
 	if (*fit > 0) {
 		return -ENOTSUP;
@@ -216,9 +235,12 @@ static int adxl345_decode_sample(const struct adxl345_sample *data,
 
 	switch (chan_spec.chan_type) {
 	case SENSOR_CHAN_ACCEL_XYZ:
-		adxl345_accel_convert(out++, data->x);
-		adxl345_accel_convert(out++, data->y);
-		adxl345_accel_convert(out, data->z);
+		adxl345_accel_convert_q31(&out->readings->x, data->x, data->selected_range,
+					  data->is_full_res);
+		adxl345_accel_convert_q31(&out->readings->y, data->y, data->selected_range,
+					  data->is_full_res);
+		adxl345_accel_convert_q31(&out->readings->z, data->z, data->selected_range,
+					  data->is_full_res);
 		break;
 	default:
 		return -ENOTSUP;
@@ -226,7 +248,7 @@ static int adxl345_decode_sample(const struct adxl345_sample *data,
 
 	*fit = 1;
 
-	return 0;
+	return 1;
 }
 
 static int adxl345_decoder_decode(const uint8_t *buffer, struct sensor_chan_spec chan_spec,
@@ -259,10 +281,33 @@ static bool adxl345_decoder_has_trigger(const uint8_t *buffer, enum sensor_trigg
 	}
 }
 
+static int adxl345_get_size_info(struct sensor_chan_spec channel, size_t *base_size,
+				 size_t *frame_size)
+{
+	__ASSERT_NO_MSG(base_size != NULL);
+	__ASSERT_NO_MSG(frame_size != NULL);
+
+	if (channel.chan_type >= SENSOR_CHAN_ALL) {
+		return -ENOTSUP;
+	}
+
+	switch (channel.chan_type) {
+	case SENSOR_CHAN_ACCEL_XYZ:
+		*base_size = sizeof(struct sensor_three_axis_data);
+		*frame_size = sizeof(struct sensor_three_axis_sample_data);
+		return 0;
+	default:
+		break;
+	}
+
+	return -ENOTSUP;
+}
+
 SENSOR_DECODER_API_DT_DEFINE() = {
 	.get_frame_count = adxl345_decoder_get_frame_count,
 	.decode = adxl345_decoder_decode,
 	.has_trigger = adxl345_decoder_has_trigger,
+	.get_size_info = adxl345_get_size_info,
 };
 
 int adxl345_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder)

drivers/sensor/adi/adxl345/adxl345_stream.c

@@ -159,7 +159,7 @@ static void adxl345_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq
 	hdr->int_status = data->status1;
 	hdr->is_full_res = data->is_full_res;
 	hdr->selected_range = data->selected_range;
-	hdr->accel_odr = cfg->odr;
+	hdr->accel_odr = data->odr;
 	hdr->sample_set_size = sample_set_size;
 
 	uint32_t buf_avail = buf_len;

drivers/sensor/adi/adxl372/adxl372.c

@@ -550,7 +550,7 @@ static int adxl372_attr_set_odr(const struct device *dev,
 				const struct sensor_value *val)
 {
 	enum adxl372_odr odr;
-	struct adxl372_dev_config *cfg = (struct adxl372_dev_config *)dev->config;
+	struct adxl372_data *data = dev->data;
 
 	switch (val->val1) {
 	case 400:
@@ -575,7 +575,7 @@ static int adxl372_attr_set_odr(const struct device *dev,
 	int ret = adxl372_set_odr(dev, odr);
 
 	if (ret == 0) {
-		cfg->odr = odr;
+		data->odr = odr;
 	}
 
 	return ret;

drivers/sensor/adi/adxl372/adxl372.h

@@ -312,6 +312,7 @@ struct adxl372_data {
 	const struct adxl372_transfer_function *hw_tf;
 	struct adxl372_fifo_config fifo_config;
 	enum adxl372_act_proc_mode act_proc_mode;
+	enum adxl372_odr odr;
 #ifdef CONFIG_ADXL372_TRIGGER
 	struct gpio_callback gpio_cb;
 

drivers/sensor/adi/adxl372/adxl372_stream.c

@@ -213,7 +213,7 @@ static void adxl372_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq
 	hdr->is_fifo = 1;
 	hdr->timestamp = data->timestamp;
 	hdr->int_status = data->status1;
-	hdr->accel_odr = cfg->odr;
+	hdr->accel_odr = data->odr;
 	hdr->sample_set_size = sample_set_size;
 
 	if ((cfg->fifo_config.fifo_format == ADXL372_X_FIFO) ||

drivers/sensor/default_rtio_sensor.c

@@ -318,25 +318,44 @@ static int get_frame_count(const uint8_t *buffer, struct sensor_chan_spec channe
 
 	switch (channel.chan_type) {
 	case SENSOR_CHAN_ACCEL_XYZ:
-		channel.chan_type = SENSOR_CHAN_ACCEL_X;
-		break;
 	case SENSOR_CHAN_GYRO_XYZ:
-		channel.chan_type = SENSOR_CHAN_GYRO_X;
-		break;
 	case SENSOR_CHAN_MAGN_XYZ:
-		channel.chan_type = SENSOR_CHAN_MAGN_X;
-		break;
 	case SENSOR_CHAN_POS_DXYZ:
-		channel.chan_type = SENSOR_CHAN_POS_DX;
+		for (size_t i = 0 ; i < header->num_channels; ++i) {
+			/* For 3-axis channels, we need to verify we have each individual axis */
+			struct sensor_chan_spec channel_x = {
+				.chan_type = channel.chan_type - 3,
+				.chan_idx = channel.chan_idx,
+			};
+			struct sensor_chan_spec channel_y = {
+				.chan_type = channel.chan_type - 2,
+				.chan_idx = channel.chan_idx,
+			};
+			struct sensor_chan_spec channel_z = {
+				.chan_type = channel.chan_type - 1,
+				.chan_idx = channel.chan_idx,
+			};
+
+			/** The three axes don't need to be at the beginning of the header, but
+			 * they should be consecutive.
+			 */
+			if (((header->num_channels - i) >= 3) &&
+			    sensor_chan_spec_eq(header->channels[i], channel_x) &&
+			    sensor_chan_spec_eq(header->channels[i + 1], channel_y) &&
+			    sensor_chan_spec_eq(header->channels[i + 2], channel_z)) {
+				*frame_count = 1;
+				return 0;
+			}
+		}
 		break;
 	default:
-		break;
-	}
-	for (size_t i = 0; i < header->num_channels; ++i) {
-		if (sensor_chan_spec_eq(header->channels[i], channel)) {
-			*frame_count = 1;
-			return 0;
+		for (size_t i = 0; i < header->num_channels; ++i) {
+			if (sensor_chan_spec_eq(header->channels[i], channel)) {
+				*frame_count = 1;
+				return 0;
+			}
 		}
+		break;
 	}
 
 	return -ENOTSUP;
@@ -353,21 +372,9 @@ int sensor_natively_supported_channel_size_info(struct sensor_chan_spec channel,
 	}
 
 	switch (channel.chan_type) {
-	case SENSOR_CHAN_ACCEL_X:
-	case SENSOR_CHAN_ACCEL_Y:
-	case SENSOR_CHAN_ACCEL_Z:
 	case SENSOR_CHAN_ACCEL_XYZ:
-	case SENSOR_CHAN_GYRO_X:
-	case SENSOR_CHAN_GYRO_Y:
-	case SENSOR_CHAN_GYRO_Z:
 	case SENSOR_CHAN_GYRO_XYZ:
-	case SENSOR_CHAN_MAGN_X:
-	case SENSOR_CHAN_MAGN_Y:
-	case SENSOR_CHAN_MAGN_Z:
 	case SENSOR_CHAN_MAGN_XYZ:
-	case SENSOR_CHAN_POS_DX:
-	case SENSOR_CHAN_POS_DY:
-	case SENSOR_CHAN_POS_DZ:
 	case SENSOR_CHAN_POS_DXYZ:
 		*base_size = sizeof(struct sensor_three_axis_data);
 		*frame_size = sizeof(struct sensor_three_axis_sample_data);
@@ -480,33 +487,21 @@ static int decode(const uint8_t *buffer, struct sensor_chan_spec chan_spec,
 
 	/* Check for 3d channel mappings */
 	switch (chan_spec.chan_type) {
-	case SENSOR_CHAN_ACCEL_X:
-	case SENSOR_CHAN_ACCEL_Y:
-	case SENSOR_CHAN_ACCEL_Z:
 	case SENSOR_CHAN_ACCEL_XYZ:
 		count = decode_three_axis(header, q, data_out, SENSOR_CHAN_ACCEL_X,
 					  SENSOR_CHAN_ACCEL_Y, SENSOR_CHAN_ACCEL_Z,
 					  chan_spec.chan_idx);
 		break;
-	case SENSOR_CHAN_GYRO_X:
-	case SENSOR_CHAN_GYRO_Y:
-	case SENSOR_CHAN_GYRO_Z:
 	case SENSOR_CHAN_GYRO_XYZ:
 		count = decode_three_axis(header, q, data_out, SENSOR_CHAN_GYRO_X,
 					  SENSOR_CHAN_GYRO_Y, SENSOR_CHAN_GYRO_Z,
 					  chan_spec.chan_idx);
 		break;
-	case SENSOR_CHAN_MAGN_X:
-	case SENSOR_CHAN_MAGN_Y:
-	case SENSOR_CHAN_MAGN_Z:
 	case SENSOR_CHAN_MAGN_XYZ:
 		count = decode_three_axis(header, q, data_out, SENSOR_CHAN_MAGN_X,
 					  SENSOR_CHAN_MAGN_Y, SENSOR_CHAN_MAGN_Z,
 					  chan_spec.chan_idx);
 		break;
-	case SENSOR_CHAN_POS_DX:
-	case SENSOR_CHAN_POS_DY:
-	case SENSOR_CHAN_POS_DZ:
 	case SENSOR_CHAN_POS_DXYZ:
 		count = decode_three_axis(header, q, data_out, SENSOR_CHAN_POS_DX,
 					  SENSOR_CHAN_POS_DY, SENSOR_CHAN_POS_DZ,

drivers/sensor/sensor_shell.c

@@ -354,23 +354,6 @@ void sensor_shell_processing_callback(int result, uint8_t *buf, uint32_t buf_len
 		size_t frame_size;
 		uint16_t frame_count;
 
-		/* Channels with multi-axis equivalents are skipped */
-		switch (ch.chan_type) {
-		case SENSOR_CHAN_ACCEL_X:
-		case SENSOR_CHAN_ACCEL_Y:
-		case SENSOR_CHAN_ACCEL_Z:
-		case SENSOR_CHAN_GYRO_X:
-		case SENSOR_CHAN_GYRO_Y:
-		case SENSOR_CHAN_GYRO_Z:
-		case SENSOR_CHAN_MAGN_X:
-		case SENSOR_CHAN_MAGN_Y:
-		case SENSOR_CHAN_MAGN_Z:
-		case SENSOR_CHAN_POS_DX:
-		case SENSOR_CHAN_POS_DY:
-		case SENSOR_CHAN_POS_DZ:
-			continue;
-		}
-
 		rc = decoder->get_size_info(ch, &base_size, &frame_size);
 		if (rc != 0) {
 			LOG_DBG("skipping unsupported channel %s:%d",

drivers/sensor/st/lis2de12/lis2de12.c

@@ -435,7 +435,7 @@ static int lis2de12_init(const struct device *dev)
 
 #define LIS2DE12_CONFIG_SPI(inst)						\
 	{									\
-		STMEMSC_CTX_SPI(&lis2de12_config_##inst.stmemsc_cfg),		\
+		STMEMSC_CTX_SPI_INCR(&lis2de12_config_##inst.stmemsc_cfg),		\
 		.stmemsc_cfg = {						\
 			.spi = SPI_DT_SPEC_INST_GET(inst, LIS2DE12_SPI_OP, 0),	\
 		},								\

drivers/sensor/st/stmemsc/stmemsc_spi.c

@@ -63,13 +63,19 @@ int stmemsc_spi_write(const struct spi_dt_spec *stmemsc,
 int stmemsc_spi_read_incr(const struct spi_dt_spec *stmemsc,
 			  uint8_t reg_addr, uint8_t *value, uint8_t len)
 {
-	reg_addr |= STMEMSC_SPI_ADDR_AUTO_INCR;
+	if (len > 1) {
+		reg_addr |= STMEMSC_SPI_ADDR_AUTO_INCR;
+	}
+
 	return stmemsc_spi_read(stmemsc, reg_addr, value, len);
 }
 
 int stmemsc_spi_write_incr(const struct spi_dt_spec *stmemsc,
 			   uint8_t reg_addr, uint8_t *value, uint8_t len)
 {
-	reg_addr |= STMEMSC_SPI_ADDR_AUTO_INCR;
+	if (len > 1) {
+		reg_addr |= STMEMSC_SPI_ADDR_AUTO_INCR;
+	}
+
 	return stmemsc_spi_write(stmemsc, reg_addr, value, len);
 }

drivers/serial/uart_esp32.c

@@ -276,6 +276,7 @@ static int uart_esp32_configure(const struct device *dev, const struct uart_conf
 	uart_hal_set_rxfifo_full_thr(&data->hal, UART_RX_FIFO_THRESH);
 	uart_hal_set_txfifo_empty_thr(&data->hal, UART_TX_FIFO_THRESH);
 	uart_hal_rxfifo_rst(&data->hal);
+	uart_hal_txfifo_rst(&data->hal);
 
 	switch (cfg->parity) {
 	case UART_CFG_PARITY_NONE:

drivers/serial/uart_nrfx_uarte.c

@@ -2339,6 +2339,18 @@ static int uarte_instance_init(const struct device *dev,
 			     : UART_CFG_FLOW_CTRL_NONE,			       \
 	}
 
+/* Macro determines if PM actions are interrupt safe. They are in case of
+ * asynchronous API (except for instance in fast power domain) and non-asynchronous
+ * API if RX is disabled. Macro must resolve to a literal 1 or 0.
+ */
+#define UARTE_PM_ISR_SAFE(idx)						       \
+	COND_CODE_1(INSTANCE_IS_FAST_PD(_, /*empty*/, idx, _),		       \
+		    (0),						       \
+		    (COND_CODE_1(CONFIG_UART_##idx##_ASYNC,		       \
+				 (PM_DEVICE_ISR_SAFE),			       \
+				 (COND_CODE_1(UARTE_PROP(idx, disable_rx),     \
+					      (PM_DEVICE_ISR_SAFE), (0))))))   \
+
 #define UART_NRF_UARTE_DEVICE(idx)					       \
 	NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(UARTE(idx));		       \
 	UARTE_INT_DRIVEN(idx);						       \
@@ -2405,7 +2417,7 @@ static int uarte_instance_init(const struct device *dev,
 	}								       \
 									       \
 	PM_DEVICE_DT_DEFINE(UARTE(idx), uarte_nrfx_pm_action,		       \
-			    PM_DEVICE_ISR_SAFE);			       \
+			    UARTE_PM_ISR_SAFE(idx));			       \
 									       \
 	DEVICE_DT_DEFINE(UARTE(idx),					       \
 		      uarte_##idx##_init,				       \

drivers/spi/Kconfig

@@ -37,6 +37,24 @@ config SPI_RTIO
 	  This option enables the RTIO API calls. RTIO support is
 	  experimental as the API itself is unstable.
 
+if SPI_RTIO
+
+config SPI_RTIO_FALLBACK_MSGS
+	int "Number of available spi_buf structs for the default handler to use"
+	default 4
+	help
+		When RTIO is used with a driver that does not yet implement the submit API
+		natively the submissions are converted back to struct spi_buf values that
+		are given to spi_transfer. This requires some number of msgs be available to convert
+		the submissions into on the stack. MISRA rules dictate we must know this in
+		advance.
+
+		In all likelihood 4 is going to work for everyone, but in case you do end up with
+		an issue where you are using RTIO, your driver does not implement submit natively,
+		and get an error relating to not enough spi msgs this is the Kconfig to manipulate.
+
+endif # SPI_RTIO
+
 config SPI_SLAVE
 	bool "Slave support [EXPERIMENTAL]"
 	select EXPERIMENTAL

drivers/spi/spi_mcux_ecspi.c

@@ -93,7 +93,8 @@ static void spi_mcux_transfer_next_packet(const struct device *dev)
 		transfer.txData = NULL;
 	}
 
-	transfer.dataSize = data->dfs;
+	/* Burst length is set in the configure step */
+	transfer.dataSize = 1;
 
 	status = ECSPI_MasterTransferNonBlocking(base, &data->handle, &transfer);
 	if (status != kStatus_Success) {
@@ -163,7 +164,7 @@ static int spi_mcux_configure(const struct device *dev,
 		return -ENOTSUP;
 	}
 
-	if (spi_cfg->slave > kECSPI_Channel3) {
+	if (!spi_cs_is_gpio(spi_cfg) && spi_cfg->slave > kECSPI_Channel3) {
 		LOG_ERR("Slave %d is greater than %d", spi_cfg->slave, kECSPI_Channel3);
 		return -EINVAL;
 	}
@@ -181,7 +182,8 @@ static int spi_mcux_configure(const struct device *dev,
 
 	ECSPI_MasterGetDefaultConfig(&master_config);
 
-	master_config.channel = (ecspi_channel_source_t)spi_cfg->slave;
+	master_config.channel =
+		spi_cs_is_gpio(spi_cfg) ? kECSPI_Channel0 : (ecspi_channel_source_t)spi_cfg->slave;
 	master_config.channelConfig.polarity =
 		(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
 		? kECSPI_PolarityActiveLow

drivers/spi/spi_rtio.c

@@ -22,6 +22,7 @@ static void spi_rtio_iodev_default_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 {
 	struct spi_dt_spec *dt_spec = iodev_sqe->sqe.iodev->data;
 	const struct device *dev = dt_spec->bus;
+	uint8_t num_msgs = 0;
 	int err = 0;
 
 	LOG_DBG("Sync RTIO work item for: %p", (void *)dev);
@@ -33,67 +34,103 @@ static void spi_rtio_iodev_default_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 	struct rtio_iodev_sqe *txn_head = iodev_sqe;
 	struct rtio_iodev_sqe *txn_curr = iodev_sqe;
 
+	/* We allocate the spi_buf's on the stack, to do so
+	 * the count of messages needs to be determined to
+	 * ensure we don't go over the statically sized array.
+	 */
 	do {
+		switch (txn_curr->sqe.op) {
+		case RTIO_OP_RX:
+		case RTIO_OP_TX:
+		case RTIO_OP_TINY_TX:
+		case RTIO_OP_TXRX:
+			num_msgs++;
+			break;
+		default:
+			LOG_ERR("Invalid op code %d for submission %p", txn_curr->sqe.op,
+				(void *)&txn_curr->sqe);
+			err = -EIO;
+			break;
+		}
+		txn_curr = rtio_txn_next(txn_curr);
+	} while (err == 0 && txn_curr != NULL);
+
+	if (err != 0) {
+		rtio_iodev_sqe_err(txn_head, err);
+		return;
+	}
+
+	/* Allocate msgs on the stack, MISRA doesn't like VLAs so we need a statically
+	 * sized array here. It's pretty unlikely we have more than 4 spi messages
+	 * in a transaction as we typically would only have 2, one to write a
+	 * register address, and another to read/write the register into an array
+	 */
+	if (num_msgs > CONFIG_SPI_RTIO_FALLBACK_MSGS) {
+		LOG_ERR("At most CONFIG_SPI_RTIO_FALLBACK_MSGS"
+			" submissions in a transaction are"
+			" allowed in the default handler");
+		rtio_iodev_sqe_err(txn_head, -ENOMEM);
+		return;
+	}
+
+	struct spi_buf tx_bufs[CONFIG_SPI_RTIO_FALLBACK_MSGS];
+	struct spi_buf rx_bufs[CONFIG_SPI_RTIO_FALLBACK_MSGS];
+	struct spi_buf_set tx_buf_set = {
+		.buffers = tx_bufs,
+		.count = num_msgs,
+	};
+	struct spi_buf_set rx_buf_set = {
+		.buffers = rx_bufs,
+		.count = num_msgs,
+	};
+
+	txn_curr = txn_head;
+
+	for (size_t i = 0 ; i < num_msgs ; i++) {
 		struct rtio_sqe *sqe = &txn_curr->sqe;
-		struct spi_buf tx_buf = {0};
-		struct spi_buf_set tx_buf_set = {
-			.buffers = &tx_buf,
-		};
-
-		struct spi_buf rx_buf = {0};
-		struct spi_buf_set rx_buf_set = {
-			.buffers = &rx_buf,
-		};
-
-		LOG_DBG("Preparing transfer: %p", txn_curr);
 
 		switch (sqe->op) {
 		case RTIO_OP_RX:
-			rx_buf.buf = sqe->rx.buf;
-			rx_buf.len = sqe->rx.buf_len;
-			rx_buf_set.count = 1;
+			rx_bufs[i].buf = sqe->rx.buf;
+			rx_bufs[i].len = sqe->rx.buf_len;
+			tx_bufs[i].buf = NULL;
+			tx_bufs[i].len = sqe->rx.buf_len;
 			break;
 		case RTIO_OP_TX:
-			tx_buf.buf = (uint8_t *)sqe->tx.buf;
-			tx_buf.len = sqe->tx.buf_len;
-			tx_buf_set.count = 1;
+			rx_bufs[i].buf = NULL;
+			rx_bufs[i].len = sqe->tx.buf_len;
+			tx_bufs[i].buf = (uint8_t *)sqe->tx.buf;
+			tx_bufs[i].len = sqe->tx.buf_len;
 			break;
 		case RTIO_OP_TINY_TX:
-			tx_buf.buf = (uint8_t *)sqe->tiny_tx.buf;
-			tx_buf.len = sqe->tiny_tx.buf_len;
-			tx_buf_set.count = 1;
+			rx_bufs[i].buf = NULL;
+			rx_bufs[i].len = sqe->tiny_tx.buf_len;
+			tx_bufs[i].buf = (uint8_t *)sqe->tiny_tx.buf;
+			tx_bufs[i].len = sqe->tiny_tx.buf_len;
 			break;
 		case RTIO_OP_TXRX:
-			rx_buf.buf = sqe->txrx.rx_buf;
-			rx_buf.len = sqe->txrx.buf_len;
-			tx_buf.buf = (uint8_t *)sqe->txrx.tx_buf;
-			tx_buf.len = sqe->txrx.buf_len;
-			rx_buf_set.count = 1;
-			tx_buf_set.count = 1;
+			rx_bufs[i].buf = sqe->txrx.rx_buf;
+			rx_bufs[i].len = sqe->txrx.buf_len;
+			tx_bufs[i].buf = (uint8_t *)sqe->txrx.tx_buf;
+			tx_bufs[i].len = sqe->txrx.buf_len;
 			break;
 		default:
-			LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
 			err = -EIO;
 			break;
 		}
 
-		if (!err) {
-			struct spi_buf_set *tx_buf_ptr = tx_buf_set.count > 0 ? &tx_buf_set : NULL;
-			struct spi_buf_set *rx_buf_ptr = rx_buf_set.count > 0 ? &rx_buf_set : NULL;
+		txn_curr = rtio_txn_next(txn_curr);
+	}
 
-			err = spi_transceive_dt(dt_spec, tx_buf_ptr, rx_buf_ptr);
+	if (err == 0) {
+		__ASSERT_NO_MSG(num_msgs > 0);
+		err = spi_transceive_dt(dt_spec, &tx_buf_set, &rx_buf_set);
+	}
 
-			/* NULL if this submission is not a transaction */
-			txn_curr = rtio_txn_next(txn_curr);
-		}
-	} while (err >= 0 && txn_curr != NULL);
-
-	if (err < 0) {
-		LOG_ERR("Transfer failed: %d", err);
+	if (err != 0) {
 		rtio_iodev_sqe_err(txn_head, err);
 	} else {
-		LOG_DBG("Transfer OK: %d", err);
-		rtio_iodev_sqe_ok(txn_head, err);
+		rtio_iodev_sqe_ok(txn_head, 0);
 	}
 }
 

drivers/wifi/nrfwifi/CMakeLists.txt

@@ -305,13 +305,20 @@ zephyr_compile_definitions_ifdef(CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS
   -DWIFI_MGMT_RAW_SCAN_RESULTS=${CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS}
 )
 
+zephyr_compile_definitions_ifdef(CONFIG_NRF70_OFFLOADED_RAW_TX
+  -DNRF_NRF70_OFFLOADED_RAW_TX
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_NRF70_PASSIVE_SCAN_ONLY
+  -DNRF70_PASSIVE_SCAN_ONLY
+)
+
 zephyr_compile_definitions(
   -DNRF70_RX_NUM_BUFS=${CONFIG_NRF70_RX_NUM_BUFS}
   -DNRF70_MAX_TX_TOKENS=${CONFIG_NRF70_MAX_TX_TOKENS}
   -DNRF70_RX_MAX_DATA_SIZE=${CONFIG_NRF70_RX_MAX_DATA_SIZE}
   -DNRF70_MAX_TX_PENDING_QLEN=${CONFIG_NRF70_MAX_TX_PENDING_QLEN}
   -DNRF70_RPU_PS_IDLE_TIMEOUT_MS=${CONFIG_NRF70_RPU_PS_IDLE_TIMEOUT_MS}
-  -DNRF70_REG_DOMAIN=${CONFIG_NRF70_REG_DOMAIN}
   -DNRF70_BAND_2G_LOWER_EDGE_BACKOFF_DSSS=${CONFIG_NRF70_BAND_2G_LOWER_EDGE_BACKOFF_DSSS}
   -DNRF70_BAND_2G_LOWER_EDGE_BACKOFF_HT=${CONFIG_NRF70_BAND_2G_LOWER_EDGE_BACKOFF_HT}
   -DNRF70_BAND_2G_LOWER_EDGE_BACKOFF_HE=${CONFIG_NRF70_BAND_2G_LOWER_EDGE_BACKOFF_HE}

dts/arm/atmel/sam4s.dtsi

@@ -55,7 +55,7 @@
 			status = "okay";
 		};
 
-		sram0: memory@20100000 {
+		sram0: memory@20000000 {
 			compatible = "mmio-sram";
 		};
 

dts/arm/atmel/sam4s16b.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(128)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(128)>;
 		};
 	};
 };

dts/arm/atmel/sam4s16c.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(128)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(128)>;
 		};
 	};
 };

dts/arm/atmel/sam4s2a.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };

dts/arm/atmel/sam4s2b.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };

dts/arm/atmel/sam4s2c.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };

dts/arm/atmel/sam4s4a.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };

dts/arm/atmel/sam4s4b.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };

dts/arm/atmel/sam4s4c.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };

dts/arm/atmel/sam4s8b.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(128)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(128)>;
 		};
 	};
 };

dts/arm/atmel/sam4s8c.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(128)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(128)>;
 		};
 	};
 };

dts/arm/atmel/sam4sa16c.dtsi

@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(160)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(160)>;
 		};
 	};
 };

dts/arm/atmel/samc21.dtsi

@@ -8,6 +8,8 @@
 
 / {
 	aliases {
+		adc-1 = &adc1;
+
 		sercom-4 = &sercom4;
 		sercom-5 = &sercom5;
 	};
@@ -15,15 +17,17 @@
 	soc {
 		adc1: adc@42004800 {
 			compatible = "atmel,sam0-adc";
-			status = "disabled";
 			reg = <0x42004800 0x30>;
 			interrupts = <26 0>;
 			interrupt-names = "resrdy";
 			clocks = <&gclk 34>, <&mclk 0x1c 18>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
+			#io-channel-cells = <1>;
+
 			gclk = <0>;
 			prescaler = <4>;
-			#io-channel-cells = <1>;
 		};
 
 		sercom4: sercom@42001400 {
@@ -51,9 +55,10 @@
 			interrupt-names = "int0";
 			clocks = <&gclk 26>, <&mclk 0x10 8>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
 			divider = <12>;
-			status = "disabled";
 		};
 
 		can1: can@42002000 {
@@ -63,9 +68,10 @@
 			interrupt-names = "int0";
 			clocks = <&gclk 27>, <&mclk 0x10 9>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
 			divider = <12>;
-			status = "disabled";
 		};
 	};
 };

dts/arm/atmel/samc2x.dtsi

@@ -13,6 +13,21 @@
 
 / {
 	aliases {
+		adc-0 = &adc0;
+
+		port-a = &porta;
+		port-b = &portb;
+		port-c = &portc;
+
+		sercom-0 = &sercom0;
+		sercom-1 = &sercom1;
+		sercom-2 = &sercom2;
+		sercom-3 = &sercom3;
+
+		tcc-0 = &tcc0;
+		tcc-1 = &tcc1;
+		tcc-2 = &tcc2;
+
 		watchdog0 = &wdog;
 	};
 
@@ -25,9 +40,10 @@
 		#size-cells = <0>;
 
 		cpu0: cpu@0 {
-			device_type = "cpu";
 			compatible = "arm,cortex-m0+";
 			reg = <0>;
+
+			device_type = "cpu";
 		};
 	};
 
@@ -43,33 +59,20 @@
 			<0x0080A048 0x4>;
 	};
 
-	aliases {
-		port-a = &porta;
-		port-b = &portb;
-		port-c = &portc;
-
-		sercom-0 = &sercom0;
-		sercom-1 = &sercom1;
-		sercom-2 = &sercom2;
-		sercom-3 = &sercom3;
-
-		tcc-0 = &tcc0;
-		tcc-1 = &tcc1;
-		tcc-2 = &tcc2;
-	};
-
 	soc {
 		nvmctrl: nvmctrl@41004000  {
 			compatible = "atmel,sam0-nvmctrl";
 			reg = <0x41004000 0x22>;
 			interrupts = <6 0>;
-			lock-regions = <16>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			lock-regions = <16>;
+
 			flash0: flash@0 {
 				compatible = "soc-nv-flash";
+
 				write-block-size = <4>;
 			};
 		};
@@ -77,12 +80,14 @@
 		mclk: mclk@40000800 {
 			compatible = "atmel,samc2x-mclk";
 			reg = <0x40000800 0x400>;
+
 			#clock-cells = <2>;
 		};
 
 		gclk: gclk@40001c00 {
 			compatible = "atmel,samc2x-gclk";
 			reg = <0x40001c00 0x400>;
+
 			#clock-cells = <1>;
 		};
 
@@ -107,20 +112,24 @@
 			compatible = "atmel,sam0-dmac";
 			reg = <0x41006000 0x50>;
 			interrupts = <7 0>;
+			status = "disabled";
+
 			#dma-cells = <2>;
 		};
 
 		adc0: adc@42004400 {
 			compatible = "atmel,sam0-adc";
-			status = "disabled";
 			reg = <0x42004400 0x30>;
 			interrupts = <25 0>;
 			interrupt-names = "resrdy";
 			clocks = <&gclk 33>, <&mclk 0x1c 17>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
+			#io-channel-cells = <1>;
+
 			gclk = <0>;
 			prescaler = <4>;
-			#io-channel-cells = <1>;
 		};
 
 		sercom0: sercom@42000400 {
@@ -165,6 +174,7 @@
 			interrupts = <17 0>;
 			clocks = <&gclk 28>, <&mclk 0x1c 9>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 
 			channels = <4>;
 			counter-size = <24>;
@@ -176,6 +186,7 @@
 			interrupts = <18 0>;
 			clocks = <&gclk 28>, <&mclk 0x1c 10>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 
 			channels = <4>;
 			counter-size = <24>;
@@ -187,6 +198,7 @@
 			interrupts = <19 0>;
 			clocks = <&gclk 29>, <&mclk 0x1c 11>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 
 			channels = <2>;
 			counter-size = <16>;
@@ -194,32 +206,39 @@
 
 		pinctrl: pinctrl@41000000 {
 			compatible = "atmel,sam0-pinctrl";
+			ranges = <0x41000000 0x41000000 0x180>;
+
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x41000000 0x41000000 0x180>;
 
 			porta: gpio@41000000 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41000000 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 
 			portb: gpio@41000080 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41000080 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 
 			portc: gpio@41000100 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41000100 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 		};
 
@@ -227,8 +246,9 @@
 			compatible = "atmel,sam0-rtc";
 			reg = <0x40002400 0x1C>;
 			interrupts = <3 0>;
-			clock-generator = <0>;
 			status = "disabled";
+
+			clock-generator = <0>;
 		};
 	};
 };

dts/arm/atmel/samd20.dtsi

@@ -20,6 +20,7 @@
 			interrupts = <13 0>;
 			clocks = <&gclk 0x13>, <&pm 0x20 8>;
 			clock-names = "GCLK", "PM";
+			status = "disabled";
 		};
 
 		tc2: tc@42002800 {
@@ -28,6 +29,7 @@
 			interrupts = <15 0>;
 			clocks = <&gclk 0x14>, <&pm 0x20 10>;
 			clock-names = "GCLK", "PM";
+			status = "disabled";
 		};
 
 		tc6: tc@42003800 {
@@ -36,6 +38,7 @@
 			interrupts = <19 0>;
 			clocks = <&gclk 0x16>, <&pm 0x20 14>;
 			clock-names = "GCLK", "PM";
+			status = "disabled";
 		};
 	};
 };

dts/arm/atmel/samd21.dtsi

@@ -9,14 +9,19 @@
 / {
 	aliases {
 		tc-6 = &tc6;
+
+		tcc-0 = &tcc0;
+		tcc-1 = &tcc1;
+		tcc-2 = &tcc2;
 	};
 
 	soc {
 		usb0: usb@41005000 {
 			compatible = "atmel,sam0-usb";
-			status = "disabled";
 			reg = <0x41005000 0x1000>;
 			interrupts = <7 0>;
+			status = "disabled";
+
 			num-bidir-endpoints = <8>;
 		};
 
@@ -24,6 +29,8 @@
 			compatible = "atmel,sam0-dmac";
 			reg = <0x41004800 0x50>;
 			interrupts = <6 0>;
+			status = "disabled";
+
 			#dma-cells = <2>;
 		};
 
@@ -33,6 +40,7 @@
 			interrupts = <21 0>;
 			clocks = <&gclk 0x1d>, <&pm 0x20 14>;
 			clock-names = "GCLK", "PM";
+			status = "disabled";
 		};
 
 		tcc0: tcc@42002000 {
@@ -41,6 +49,7 @@
 			interrupts = <15 0>;
 			clocks = <&gclk 26>, <&pm 0x20 8>;
 			clock-names = "GCLK", "PM";
+			status = "disabled";
 
 			channels = <4>;
 			counter-size = <24>;
@@ -52,6 +61,7 @@
 			interrupts = <16 0>;
 			clocks = <&gclk 26>, <&pm 0x20 9>;
 			clock-names = "GCLK", "PM";
+			status = "disabled";
 
 			channels = <2>;
 			counter-size = <24>;
@@ -63,6 +73,7 @@
 			interrupts = <17 0>;
 			clocks = <&gclk 27>, <&pm 0x20 10>;
 			clock-names = "GCLK", "PM";
+			status = "disabled";
 
 			channels = <2>;
 			counter-size = <16>;

dts/arm/atmel/samd2x.dtsi

@@ -13,6 +13,20 @@
 
 / {
 	aliases {
+		adc-0 = &adc;
+
+		port-a = &porta;
+		port-b = &portb;
+
+		sercom-0 = &sercom0;
+		sercom-1 = &sercom1;
+		sercom-2 = &sercom2;
+		sercom-3 = &sercom3;
+		sercom-4 = &sercom4;
+		sercom-5 = &sercom5;
+
+		tc-4 = &tc4;
+
 		watchdog0 = &wdog;
 	};
 
@@ -25,9 +39,10 @@
 		#size-cells = <0>;
 
 		cpu0: cpu@0 {
-			device_type = "cpu";
 			compatible = "arm,cortex-m0+";
 			reg = <0>;
+
+			device_type = "cpu";
 		};
 	};
 
@@ -43,33 +58,20 @@
 			<0x0080A048 0x4>;
 	};
 
-	aliases {
-		port-a = &porta;
-		port-b = &portb;
-		adc-0 = &adc;
-
-		sercom-0 = &sercom0;
-		sercom-1 = &sercom1;
-		sercom-2 = &sercom2;
-		sercom-3 = &sercom3;
-		sercom-4 = &sercom4;
-		sercom-5 = &sercom5;
-
-		tc-4 = &tc4;
-	};
-
 	soc {
 		nvmctrl: nvmctrl@41004000  {
 			compatible = "atmel,sam0-nvmctrl";
 			reg = <0x41004000 0x22>;
 			interrupts = <5 0>;
-			lock-regions = <16>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			lock-regions = <16>;
+
 			flash0: flash@0 {
 				compatible = "soc-nv-flash";
+
 				write-block-size = <4>;
 			};
 		};
@@ -78,12 +80,14 @@
 			compatible = "atmel,samd2x-pm";
 			reg = <0x40000400 0x400>;
 			interrupts = <0 0>;
+
 			#clock-cells = <2>;
 		};
 
 		gclk: gclk@40000c00 {
 			compatible = "atmel,samd2x-gclk";
 			reg = <0x40000c00 0x400>;
+
 			#clock-cells = <1>;
 		};
 
@@ -148,29 +152,34 @@
 		tc4: tc@42003000 {
 			compatible = "atmel,sam0-tc32";
 			reg = <0x42003000 0x20>;
+			status = "disabled";
 		};
 
 		pinctrl: pinctrl@41004400 {
 			compatible = "atmel,sam0-pinctrl";
+			ranges = <0x41004400 0x41004400 0x100>;
+
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x41004400 0x41004400 0x100>;
 
 			porta: gpio@41004400 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41004400 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				#atmel,pin-cells = <2>;
 
+				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 
 			portb: gpio@41004480 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41004480 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 		};
 
@@ -178,13 +187,17 @@
 			compatible = "atmel,sam0-rtc";
 			reg = <0x40001400 0x1C>;
 			interrupts = <3 0>;
-			clock-generator = <0>;
 			status = "disabled";
+
+			clock-generator = <0>;
 		};
 
 		adc: adc@42004000 {
 			compatible = "atmel,sam0-adc";
 			reg = <0x42004000 0x2B>;
+			status = "disabled";
+
+			#io-channel-cells = <1>;
 
 			/*
 			 * 2.1 MHz max, so clock it with the
@@ -192,13 +205,13 @@
 			 */
 			gclk = <3>;
 			prescaler = <4>;
-			#io-channel-cells = <1>;
 		};
 
 		dac0: dac@42004800 {
 			compatible = "atmel,sam0-dac";
-			status = "disabled";
 			reg = <0x42004800 0x10>;
+			status = "disabled";
+
 			#io-channel-cells = <0>;
 		};
 	};

dts/arm/atmel/samd5x.dtsi

@@ -11,28 +11,6 @@
 #include <zephyr/dt-bindings/pwm/pwm.h>
 
 / {
-	chosen {
-		zephyr,flash-controller = &nvmctrl;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-m4f";
-			reg = <0>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			mpu: mpu@e000ed90 {
-				compatible = "arm,armv7m-mpu";
-				reg = <0xe000ed90 0x40>;
-			};
-		};
-	};
-
 	aliases {
 		adc-0 = &adc0;
 		adc-1 = &adc1;
@@ -67,6 +45,27 @@
 
 	chosen {
 		zephyr,entropy = &trng;
+		zephyr,flash-controller = &nvmctrl;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			device_type = "cpu";
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
 	};
 
 	soc {
@@ -91,12 +90,14 @@
 		mclk: mclk@40000800 {
 			compatible = "atmel,samd5x-mclk";
 			reg = <0x40000800 0x400>;
+
 			#clock-cells = <2>;
 		};
 
 		gclk: gclk@40001c00 {
 			compatible = "atmel,samd5x-gclk";
 			reg = <0x40001c00 0x400>;
+
 			#clock-cells = <1>;
 		};
 
@@ -104,13 +105,15 @@
 			compatible = "atmel,sam0-nvmctrl";
 			reg = <0x41004000 0x22>;
 			interrupts = <29 0>, <30 0>;
-			lock-regions = <32>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			lock-regions = <32>;
+
 			flash0: flash@0 {
 				compatible = "soc-nv-flash";
+
 				write-block-size = <8>;
 			};
 		};
@@ -119,6 +122,8 @@
 			compatible = "atmel,sam0-dmac";
 			reg = <0x4100A000 0x50>;
 			interrupts = <31 0>, <32 0>, <33 0>, <34 0>, <35 0>;
+			status = "disabled";
+
 			#dma-cells = <2>;
 		};
 
@@ -161,118 +166,128 @@
 			compatible = "atmel,sam0-sercom";
 			reg = <0x40003000 0x40>;
 			interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
-			status = "disabled";
 			clocks = <&gclk 7>, <&mclk 0x14 12>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		sercom1: sercom@40003400 {
 			compatible = "atmel,sam0-sercom";
 			reg = <0x40003400 0x40>;
 			interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
-			status = "disabled";
 			clocks = <&gclk 8>, <&mclk 0x14 13>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		sercom2: sercom@41012000 {
 			compatible = "atmel,sam0-sercom";
 			reg = <0x41012000 0x40>;
 			interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
-			status = "disabled";
 			clocks = <&gclk 23>, <&mclk 0x18 9>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		sercom3: sercom@41014000 {
 			compatible = "atmel,sam0-sercom";
 			reg = <0x41014000 0x40>;
 			interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
-			status = "disabled";
 			clocks = <&gclk 24>, <&mclk 0x18 10>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		sercom4: sercom@43000000 {
 			compatible = "atmel,sam0-sercom";
 			reg = <0x43000000 0x40>;
 			interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
-			status = "disabled";
 			clocks = <&gclk 34>, <&mclk 0x20 0>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		sercom5: sercom@43000400 {
 			compatible = "atmel,sam0-sercom";
 			reg = <0x43000400 0x40>;
 			interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
-			status = "disabled";
 			clocks = <&gclk 35>, <&mclk 0x20 1>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		sercom6: sercom@43000800 {
 			compatible = "atmel,sam0-sercom";
 			reg = <0x43000800 0x40>;
 			interrupts = <70 0>, <71 0>, <72 0>, <73 0>;
-			status = "disabled";
 			clocks = <&gclk 36>, <&mclk 0x20 2>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		sercom7: sercom@43000c00 {
 			compatible = "atmel,sam0-sercom";
 			reg = <0x43000C00 0x40>;
 			interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
-			status = "disabled";
 			clocks = <&gclk 37>, <&mclk 0x20 3>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		pinctrl: pinctrl@41008000 {
 			compatible = "atmel,sam0-pinctrl";
+			ranges = <0x41008000 0x41008000 0x200>;
+
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x41008000 0x41008000 0x200>;
 
 			porta: gpio@41008000 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41008000 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 
 			portb: gpio@41008080 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41008080 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 
 			portc: gpio@41008100 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41008100 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 
 			portd: gpio@41008180 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41008180 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 		};
 
 		usb0: usb@41000000 {
 			compatible = "atmel,sam0-usb";
-			status = "disabled";
 			reg = <0x41000000 0x1000>;
 			interrupts = <80 0>, <81 0>, <82 0>, <83 0>;
+			status = "disabled";
+
 			num-bidir-endpoints = <8>;
 		};
 
@@ -286,8 +301,9 @@
 			compatible = "atmel,sam0-rtc";
 			reg = <0x40002400 0x1C>;
 			interrupts = <11 0>;
-			clock-generator = <0>;
 			status = "disabled";
+
+			clock-generator = <0>;
 		};
 
 		adc0: adc@43001c00 {
@@ -295,6 +311,11 @@
 			reg = <0x43001C00 0x4A>;
 			interrupts = <118 0>, <119 0>;
 			interrupt-names = "overrun", "resrdy";
+			clocks = <&gclk 40>, <&mclk 0x20 7>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
+			#io-channel-cells = <1>;
 
 			/*
 			 * 16 MHz max, source clock must not exceed 100 MHz.
@@ -304,9 +325,6 @@
 			 */
 			gclk = <2>;
 			prescaler = <4>;
-			#io-channel-cells = <1>;
-			clocks = <&gclk 40>, <&mclk 0x20 7>;
-			clock-names = "GCLK", "MCLK";
 			calib-offset = <0>;
 		};
 
@@ -315,6 +333,11 @@
 			reg = <0x43002000 0x4A>;
 			interrupts = <120 0>, <121 0>;
 			interrupt-names = "overrun", "resrdy";
+			clocks = <&gclk 41>, <&mclk 0x20 8>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
+			#io-channel-cells = <1>;
 
 			/*
 			 * 16 MHz max, source clock must not exceed 100 MHz.
@@ -324,9 +347,6 @@
 			 */
 			gclk = <2>;
 			prescaler = <4>;
-			#io-channel-cells = <1>;
-			clocks = <&gclk 41>, <&mclk 0x20 8>;
-			clock-names = "GCLK", "MCLK";
 			calib-offset = <14>;
 		};
 
@@ -336,6 +356,7 @@
 			interrupts = <107 0>;
 			clocks = <&gclk 9>, <&mclk 0x14 14>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		tc2: tc@4101a000 {
@@ -344,6 +365,7 @@
 			interrupts = <109 0>;
 			clocks = <&gclk 26>, <&mclk 0x18 13>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		tc4: tc@42001400 {
@@ -352,6 +374,7 @@
 			interrupts = <111 0>;
 			clocks = <&gclk 30>, <&mclk 0x1c 5>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		tc6: tc@43001400 {
@@ -360,6 +383,7 @@
 			interrupts = <113 0>;
 			clocks = <&gclk 39>, <&mclk 0x20 5>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 		};
 
 		tcc0: tcc@41016000 {
@@ -369,6 +393,8 @@
 				     <90 0>, <91 0>;
 			clocks = <&gclk 25>, <&mclk 0x18 11>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			channels = <6>;
 			counter-size = <24>;
 		};
@@ -379,6 +405,8 @@
 			interrupts = <92 0>, <93 0>, <94 0>, <95 0>, <96 0>;
 			clocks = <&gclk 25>, <&mclk 0x18 12>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			channels = <4>;
 			counter-size = <24>;
 		};
@@ -389,6 +417,8 @@
 			interrupts = <97 0>, <98 0>, <99 0>, <100 0>;
 			clocks = <&gclk 29>, <&mclk 0x1c 3>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			channels = <3>;
 			counter-size = <16>;
 		};
@@ -399,6 +429,8 @@
 			interrupts = <101 0>, <102 0>, <103 0>;
 			clocks = <&gclk 29>, <&mclk 0x1c 4>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			channels = <2>;
 			counter-size = <16>;
 		};
@@ -409,6 +441,8 @@
 			interrupts = <104 0>, <105 0>, <106 0>;
 			clocks = <&gclk 38>, <&mclk 0x20 4>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			channels = <2>;
 			counter-size = <16>;
 		};

dts/arm/atmel/same5x.dtsi

@@ -14,15 +14,17 @@
 			reg = <0x42000800 0x400>;
 			interrupts = <84 0>;
 			interrupt-names = "gmac";
+			status = "disabled";
+
 			num-queues = <1>;
 			local-mac-address = [00 00 00 00 00 00];
-			status = "disabled";
 		};
 
 		mdio: mdio@42000800 {
 			compatible = "atmel,sam-mdio";
 			reg = <0x42000800 0x400>;
 			status = "disabled";
+
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -34,9 +36,10 @@
 			interrupt-names = "int0", "int1";
 			clocks = <&gclk 27>, <&mclk 0x10 17>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 			divider = <12>;
-			status = "disabled";
 		};
 
 		can1: can@42000400 {
@@ -46,9 +49,10 @@
 			interrupt-names = "int0", "int1";
 			clocks = <&gclk 28>, <&mclk 0x10 18>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+
 			bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 			divider = <12>;
-			status = "disabled";
 		};
 	};
 };

dts/arm/atmel/saml21.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021 Argentum Systems Ltd.
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,28 +8,20 @@
 #include <atmel/saml2x.dtsi>
 
 / {
+	aliases {
+		tcc-0 = &tcc0;
+		tcc-1 = &tcc1;
+		tcc-2 = &tcc2;
+	};
+
 	soc {
-		usb0: usb@41000000 {
-			compatible = "atmel,sam0-usb";
-			status = "disabled";
-			reg = <0x41000000 0x1000>;
-			interrupts = <6 0>;
-			num-bidir-endpoints = <8>;
-		};
-
-		dmac: dmac@44000400 {
-			compatible = "atmel,sam0-dmac";
-			reg = <0x44000400 0x50>;
-			interrupts = <5 0>;
-			#dma-cells = <2>;
-		};
-
 		tcc0: tcc@42001400 {
 			compatible = "atmel,sam0-tcc";
 			reg = <0x42001400 0x80>;
 			interrupts = <14 0>;
 			clocks = <&gclk 25>, <&mclk 0x1c 5>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 
 			channels = <4>;
 			counter-size = <24>;
@@ -40,6 +33,7 @@
 			interrupts = <15 0>;
 			clocks = <&gclk 25>, <&mclk 0x1c 6>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 
 			channels = <4>;
 			counter-size = <24>;
@@ -51,6 +45,7 @@
 			interrupts = <16 0>;
 			clocks = <&gclk 26>, <&mclk 0x1c 7>;
 			clock-names = "GCLK", "MCLK";
+			status = "disabled";
 
 			channels = <2>;
 			counter-size = <16>;

dts/arm/atmel/saml2x.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021 Argentum Systems Ltd.
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +14,20 @@
 
 / {
 	aliases {
+		adc-0 = &adc;
+
+		port-a = &porta;
+		port-b = &portb;
+
+		sercom-0 = &sercom0;
+		sercom-1 = &sercom1;
+		sercom-2 = &sercom2;
+		sercom-3 = &sercom3;
+		sercom-4 = &sercom4;
+		sercom-5 = &sercom5;
+
+		tc-4 = &tc4;
+
 		watchdog0 = &wdog;
 	};
 
@@ -26,9 +41,10 @@
 		#size-cells = <0>;
 
 		cpu0: cpu@0 {
-			device_type = "cpu";
 			compatible = "arm,cortex-m0+";
 			reg = <0>;
+
+			device_type = "cpu";
 		};
 	};
 
@@ -50,14 +66,16 @@
 			compatible = "atmel,sam0-nvmctrl";
 			reg = <0x41004000 0x22>;
 			interrupts = <4 0>;
-			lock-regions = <16>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			lock-regions = <16>;
+
 			flash0: flash@0 {
 				compatible = "soc-nv-flash";
 				reg = <0 0x40000>;
+
 				write-block-size = <4>;
 			};
 		};
@@ -66,18 +84,21 @@
 			compatible = "atmel,saml2x-pm";
 			reg = <0x40000400 0x400>;
 			interrupts = <0 0>;
+
 			#clock-cells = <2>;
 		};
 
 		mclk: mclk@40000400 {
 			compatible = "atmel,saml2x-mclk";
 			reg = <0x40000400 0x400>;
+
 			#clock-cells = <2>;
 		};
 
 		gclk: gclk@40001800 {
 			compatible = "atmel,saml2x-gclk";
 			reg = <0x40001800 0x400>;
+
 			#clock-cells = <1>;
 		};
 
@@ -85,6 +106,8 @@
 			compatible = "atmel,sam0-dmac";
 			reg = <0x44000400 0x400>;
 			interrupts = <5 0>;
+			status = "disabled";
+
 			#dma-cells = <2>;
 		};
 
@@ -139,29 +162,34 @@
 		tc4: tc@43000800 {
 			compatible = "atmel,sam0-tc32";
 			reg = <0x43000800 0x34>;
+			status = "disabled";
 		};
 
 		pinctrl: pinctrl@40002800 {
 			compatible = "atmel,sam0-pinctrl";
+			ranges = <0x40002800 0x40002800 0x100>;
+
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x40002800 0x40002800 0x100>;
 
 			porta: gpio@40002800 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x40002800 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				#atmel,pin-cells = <2>;
 
+				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 
 			portb: gpio@40002880 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x40002880 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 		};
 
@@ -169,13 +197,17 @@
 			compatible = "atmel,sam0-rtc";
 			reg = <0x40002000 0x1c>;
 			interrupts = <2 0>;
-			clock-generator = <0>;
 			status = "disabled";
+
+			clock-generator = <0>;
 		};
 
 		adc: adc@43000c00 {
 			compatible = "atmel,sam0-adc";
 			reg = <0x43000c00 0x30>;
+			status = "disabled";
+
+			#io-channel-cells = <1>;
 
 			/*
 			 * 16 MHz max, so clock it with the
@@ -183,13 +215,13 @@
 			 */
 			gclk = <3>;
 			prescaler = <2>;
-			#io-channel-cells = <1>;
 		};
 
 		dac: dac@42003000 {
 			compatible = "atmel,sam0-dac";
-			status = "disabled";
 			reg = <0x42003000 0x1a>;
+			status = "disabled";
+
 			#io-channel-cells = <0>;
 		};
 
@@ -198,6 +230,15 @@
 			reg = <0x42003800 0x24>;
 			interrupts = <27 0>;
 		};
+
+		usb0: usb@41000000 {
+			compatible = "atmel,sam0-usb";
+			reg = <0x41000000 0x1000>;
+			interrupts = <6 0>;
+			status = "disabled";
+
+			num-bidir-endpoints = <8>;
+		};
 	};
 };
 

dts/arm/atmel/samr21.dtsi

@@ -1,10 +1,11 @@
 /*
  * Copyright (c) 2019 Benjamin Valentin
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <atmel/samd2x.dtsi>
+#include <atmel/samd21.dtsi>
 
 / {
 	aliases {
@@ -12,30 +13,17 @@
 	};
 
 	soc {
-		usb0: usb@41005000 {
-			compatible = "atmel,sam0-usb";
-			status = "disabled";
-			reg = <0x41005000 0x1000>;
-			interrupts = <7 0>;
-			num-bidir-endpoints = <8>;
-		};
-
-		dmac: dmac@41004800 {
-			compatible = "atmel,sam0-dmac";
-			reg = <0x41004800 0x50>;
-			interrupts = <6 0>;
-			#dma-cells = <2>;
-		};
-
 		pinctrl: pinctrl@41004400 {
 			ranges = <0x41004400 0x41004400 0x180>;
 
 			portc: gpio@41004500 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x41004500 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+
+				gpio-controller;
 			};
 		};
 
@@ -43,87 +31,5 @@
 			compatible = "atmel,sam0-pinmux";
 			reg = <0x41004500 0x80>;
 		};
-
-		tcc0: tcc@42002000 {
-			compatible = "atmel,sam0-tcc";
-			reg = <0x42002000 0x80>;
-			interrupts = <15 0>;
-			clocks = <&gclk 26>, <&pm 0x20 8>;
-			clock-names = "GCLK", "PM";
-
-			channels = <4>;
-			counter-size = <24>;
-		};
-
-		tcc1: tcc@42002400 {
-			compatible = "atmel,sam0-tcc";
-			reg = <0x42002400 0x80>;
-			interrupts = <16 0>;
-			clocks = <&gclk 26>, <&pm 0x20 9>;
-			clock-names = "GCLK", "PM";
-
-			channels = <2>;
-			counter-size = <24>;
-		};
-
-		tcc2: tcc@42002800 {
-			compatible = "atmel,sam0-tcc";
-			reg = <0x42002800 0x80>;
-			interrupts = <17 0>;
-			clocks = <&gclk 27>, <&pm 0x20 10>;
-			clock-names = "GCLK", "PM";
-
-			channels = <2>;
-			counter-size = <16>;
-		};
 	};
 };
-
-&sercom0 {
-	interrupts = <9 0>;
-	clocks = <&gclk 0x14>, <&pm 0x20 2>;
-	clock-names = "GCLK", "PM";
-};
-
-&sercom1 {
-	interrupts = <10 0>;
-	clocks = <&gclk 0x15>, <&pm 0x20 3>;
-	clock-names = "GCLK", "PM";
-};
-
-&sercom2 {
-	interrupts = <11 0>;
-	clocks = <&gclk 0x16>, <&pm 0x20 4>;
-	clock-names = "GCLK", "PM";
-};
-
-&sercom3 {
-	interrupts = <12 0>;
-	clocks = <&gclk 0x17>, <&pm 0x20 5>;
-	clock-names = "GCLK", "PM";
-};
-
-&sercom4 {
-	interrupts = <13 0>;
-	clocks = <&gclk 0x18>, <&pm 0x20 6>;
-	clock-names = "GCLK", "PM";
-};
-
-&sercom5 {
-	interrupts = <14 0>;
-	clocks = <&gclk 0x19>, <&pm 0x20 7>;
-	clock-names = "GCLK", "PM";
-};
-
-&tc4 {
-	interrupts = <19 0>;
-	clocks = <&gclk 0x1c>, <&pm 0x20 12>;
-	clock-names = "GCLK", "PM";
-};
-
-&adc {
-	clocks = <&gclk 0x1e>, <&pm 0x20 16>;
-	clock-names = "GCLK", "PM";
-	interrupts = <23 0>;
-	interrupt-names = "resrdy";
-};

dts/arm/atmel/samr34.dtsi

@@ -13,6 +13,8 @@
 
 / {
 	aliases {
+		port-c = &portc;
+
 		lora0 = &lora;
 	};
 
@@ -23,9 +25,10 @@
 			portc: gpio@40002900 {
 				compatible = "atmel,sam0-gpio";
 				reg = <0x40002900 0x80>;
-				gpio-controller;
-				#gpio-cells = <2>;
+
 				#atmel,pin-cells = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
 			};
 		};
 	};
@@ -37,19 +40,22 @@
 	/* SERCOM4 is used to interface with the internal LoRa radio */
 	compatible = "atmel,sam0-spi";
 	status = "disabled";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
 	dipo = <0>;
 	dopo = <1>;
 	cs-gpios = <&portb 31 GPIO_ACTIVE_LOW>;
-	#address-cells = <1>;
-	#size-cells = <0>;
 
 	pinctrl-0 = <&sercom4_default>;
 	pinctrl-names = "default";
 
 	lora: sx1276@0 {
 		compatible = "semtech,sx1276";
-		status = "disabled";
 		reg = <0>;
+		status = "disabled";
+
 		reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>;               /* nRST */
 		dio-gpios =
 			<&portb 16 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 */

dts/arm/st/f1/stm32f105.dtsi

@@ -49,7 +49,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
 			status = "disabled";
 		};
 

dts/arm/st/f4/stm32f405.dtsi

@@ -220,7 +220,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};

dts/arm/st/f4/stm32f412.dtsi

@@ -230,7 +230,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};

dts/arm/st/f4/stm32f446.dtsi

@@ -73,7 +73,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};

dts/arm/st/h7/stm32h723.dtsi

@@ -88,7 +88,7 @@
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
 			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
-			resets = <&rctl STM32_RESET(APB3, 4U)>;
+			resets = <&rctl STM32_RESET(APB3, 3U)>;
 			status = "disabled";
 		};
 

dts/arm/st/h7/stm32h743.dtsi

@@ -49,7 +49,7 @@
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
 			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
-			resets = <&rctl STM32_RESET(APB3, 4U)>;
+			resets = <&rctl STM32_RESET(APB3, 3U)>;
 			status = "disabled";
 		};
 

dts/arm/st/h7/stm32h745.dtsi

@@ -42,7 +42,7 @@
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
 			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
-			resets = <&rctl STM32_RESET(APB3, 4U)>;
+			resets = <&rctl STM32_RESET(APB3, 3U)>;
 			status = "disabled";
 		};
 

dts/arm/st/h7/stm32h7a3.dtsi

@@ -52,7 +52,7 @@
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
 			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
-			resets = <&rctl STM32_RESET(APB3, 4U)>;
+			resets = <&rctl STM32_RESET(APB3, 3U)>;
 			status = "disabled";
 		};
 

dts/arm/st/u5/stm32u5.dtsi

@@ -304,7 +304,7 @@
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x40036400 DT_SIZE_K(2)>;
 			/* BKPSRAMEN and RAMCFGEN clock enable */
-			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 ((1 << 28) | (1 << 17))>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};

dts/arm/st/u5/stm32u595.dtsi

@@ -106,7 +106,8 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <4096>;
 			maximum-speed = "high-speed";
-			clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
+			/* Enable OTG_HS PHY and peripheral clocks (OTGHSPHYEN | OTGEN) */
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 ((1 << 15) | (1 << 14))>,
 				 <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
 			phys = <&otghs_phy>;
 			status = "disabled";

dts/common/espressif/partitions_0x0_amp_16M.dtsi

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /* 16MB flash partition table */
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 DT_SIZE_K(6080)>;
+		};
+
+		slot0_appcpu_partition: partition@610000 {
+			label = "image-0-appcpu";
+			reg = <0x610000 DT_SIZE_K(1920)>;
+		};
+
+		slot1_partition: partition@7F0000 {
+			label = "image-1";
+			reg = <0x7F0000 DT_SIZE_K(6080)>;
+		};
+
+		slot1_appcpu_partition: partition@DE0000 {
+			label = "image-1-appcpu";
+			reg = <0xDE0000 DT_SIZE_K(1920)>;
+		};
+
+		storage_partition: partition@FC0000 {
+			label = "storage";
+			reg = <0xFC0000 DT_SIZE_K(128)>;
+		};
+
+		scratch_partition: partition@FE0000 {
+			   label = "image-scratch";
+			   reg = <0xFE0000 DT_SIZE_K(64)>;
+		};
+
+		coredump_partition: partition@FF0000 {
+			label = "coredump-partition";
+			reg = <0xFF0000 DT_SIZE_K(4)>;
+		};
+	};
+};

dts/common/espressif/partitions_0x0_amp_32M.dtsi

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /* 32MB flash partition table */
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 DT_SIZE_K(12352)>;
+		};
+
+		slot0_appcpu_partition: partition@C30000 {
+			label = "image-0-appcpu";
+			reg = <0xC30000 DT_SIZE_K(3840)>;
+		};
+
+		slot1_partition: partition@FF0000 {
+			label = "image-1";
+			reg = <0xFF0000 DT_SIZE_K(12352)>;
+		};
+
+		slot1_appcpu_partition: partition@1C00000 {
+			label = "image-1-appcpu";
+			reg = <0x1C00000 DT_SIZE_K(3840)>;
+		};
+
+		storage_partition: partition@1FC0000 {
+			label = "storage";
+			reg = <0x1FC0000 DT_SIZE_K(128)>;
+		};
+
+		scratch_partition: partition@1FE0000 {
+			   label = "image-scratch";
+			   reg = <0x1FE0000 DT_SIZE_K(64)>;
+		};
+
+		coredump_partition: partition@1FF0000 {
+			label = "coredump-partition";
+			reg = <0x1FF0000 DT_SIZE_K(4)>;
+		};
+	};
+};

dts/common/espressif/partitions_0x0_default_16M.dtsi

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /* 16MB flash partition table */
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 DT_SIZE_K(8000)>;
+		};
+
+		slot1_partition: partition@7F0000 {
+			label = "image-1";
+			reg = <0x7F0000 DT_SIZE_K(8000)>;
+		};
+
+		storage_partition: partition@FC0000 {
+			label = "storage";
+			reg = <0xFC0000 DT_SIZE_K(128)>;
+		};
+
+		scratch_partition: partition@FE0000 {
+			   label = "image-scratch";
+			   reg = <0xFE0000 DT_SIZE_K(64)>;
+		};
+
+		coredump_partition: partition@FF0000 {
+			label = "coredump-partition";
+			reg = <0xFF0000 DT_SIZE_K(4)>;
+		};
+	};
+};

dts/common/espressif/partitions_0x0_default_32M.dtsi

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /* 32MB flash partition table */
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 DT_SIZE_K(16192)>;
+		};
+
+		slot1_partition: partition@FF0000 {
+			label = "image-1";
+			reg = <0xFF0000 DT_SIZE_K(16192)>;
+		};
+
+		storage_partition: partition@1FC0000 {
+			label = "storage";
+			reg = <0x1FC0000 DT_SIZE_K(128)>;
+		};
+
+		scratch_partition: partition@1FE0000 {
+			   label = "image-scratch";
+			   reg = <0x1FE0000 DT_SIZE_K(64)>;
+		};
+
+		coredump_partition: partition@1FF0000 {
+			label = "coredump-partition";
+			reg = <0x1FF0000 DT_SIZE_K(4)>;
+		};
+	};
+};

dts/common/espressif/partitions_0x1000_amp_16M.dtsi

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /* 16MB flash partition table */
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@1000 {
+			label = "mcuboot";
+			reg = <0x1000 DT_SIZE_K(60)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 DT_SIZE_K(6080)>;
+		};
+
+		slot0_appcpu_partition: partition@610000 {
+			label = "image-0-appcpu";
+			reg = <0x610000 DT_SIZE_K(1920)>;
+		};
+
+		slot1_partition: partition@7F0000 {
+			label = "image-1";
+			reg = <0x7F0000 DT_SIZE_K(6080)>;
+		};
+
+		slot1_appcpu_partition: partition@DE0000 {
+			label = "image-1-appcpu";
+			reg = <0xDE0000 DT_SIZE_K(1920)>;
+		};
+
+		storage_partition: partition@FC0000 {
+			label = "storage";
+			reg = <0xFC0000 DT_SIZE_K(128)>;
+		};
+
+		scratch_partition: partition@FE0000 {
+			   label = "image-scratch";
+			   reg = <0xFE0000 DT_SIZE_K(64)>;
+		};
+
+		coredump_partition: partition@FF0000 {
+			label = "coredump-partition";
+			reg = <0xFF0000 DT_SIZE_K(4)>;
+		};
+	};
+};

dts/common/espressif/partitions_0x1000_amp_32M.dtsi

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /* 32MB flash partition table */
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@1000 {
+			label = "mcuboot";
+			reg = <0x1000 DT_SIZE_K(60)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 DT_SIZE_K(12352)>;
+		};
+
+		slot0_appcpu_partition: partition@C30000 {
+			label = "image-0-appcpu";
+			reg = <0xC24000 DT_SIZE_K(3840)>;
+		};
+
+		slot1_partition: partition@FF0000 {
+			label = "image-1";
+			reg = <0xFF0000 DT_SIZE_K(12352)>;
+		};
+
+		slot1_appcpu_partition: partition@1C00000 {
+			label = "image-1-appcpu";
+			reg = <0x1C00000 DT_SIZE_K(3840)>;
+		};
+
+		storage_partition: partition@1FC0000 {
+			label = "storage";
+			reg = <0x1FC0000 DT_SIZE_K(128)>;
+		};
+
+		scratch_partition: partition@1FE0000 {
+			   label = "image-scratch";
+			   reg = <0x1FE0000 DT_SIZE_K(64)>;
+		};
+
+		coredump_partition: partition@1FF0000 {
+			label = "coredump-partition";
+			reg = <0x1FF0000 DT_SIZE_K(4)>;
+		};
+	};
+};

dts/common/espressif/partitions_0x1000_default_16M.dtsi

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /* 16MB flash partition table */
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@1000 {
+			label = "mcuboot";
+			reg = <0x1000 DT_SIZE_K(60)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 DT_SIZE_K(8000)>;
+		};
+
+		slot1_partition: partition@7F0000 {
+			label = "image-1";
+			reg = <0x7F0000 DT_SIZE_K(8000)>;
+		};
+
+		storage_partition: partition@FC0000 {
+			label = "storage";
+			reg = <0xFC0000 DT_SIZE_K(128)>;
+		};
+
+		scratch_partition: partition@FE0000 {
+			   label = "image-scratch";
+			   reg = <0xFE0000 DT_SIZE_K(64)>;
+		};
+
+		coredump_partition: partition@FF0000 {
+			label = "coredump-partition";
+			reg = <0xFF0000 DT_SIZE_K(4)>;
+		};
+	};
+};

dts/common/espressif/partitions_0x1000_default_32M.dtsi

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /* 32MB flash partition table */
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@1000 {
+			label = "mcuboot";
+			reg = <0x1000 DT_SIZE_K(60)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x20000 DT_SIZE_K(16192)>;
+		};
+
+		slot1_partition: partition@FF0000 {
+			label = "image-1";
+			reg = <0xFF0000 DT_SIZE_K(16192)>;
+		};
+
+		storage_partition: partition@1FC0000 {
+			label = "storage";
+			reg = <0x1FC0000 DT_SIZE_K(128)>;
+		};
+
+		scratch_partition: partition@1FE0000 {
+			   label = "image-scratch";
+			   reg = <0x1FE0000 DT_SIZE_K(64)>;
+		};
+
+		coredump_partition: partition@1FF0000 {
+			label = "coredump-partition";
+			reg = <0x1FF0000 DT_SIZE_K(4)>;
+		};
+	};
+};

include/zephyr/arch/riscv/reg.h

@@ -7,6 +7,8 @@
 #ifndef ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_
 #define ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_
 
+#include <zephyr/sys/util.h>
+
 #define reg_read(reg)                                                                              \
 	({                                                                                         \
 		register unsigned long __rv;                                                       \

include/zephyr/bluetooth/services/cts.h

@@ -16,7 +16,6 @@
  */
 
 #include <stdint.h>
-#include <zephyr/posix/time.h>
 
 #ifdef __cplusplus
 extern "C" {