posix: c_lib_ext: fnmatch: fix llvm warning

The tolower() function takes an int parameter. LLVM compilers generate a
warning if a char is passed instead.

Signed-off-by: Keith Short <keithshort@google.com>

.github/SECURITY.md

@@ -8,11 +8,11 @@ updates:
   - The most recent release, and the release prior to that.
   - Active LTS releases.
 
-At this time, with the latest release of v4.3, the supported
+At this time, with the latest release of v4.2, the supported
 versions are:
 
-  - v4.3: Current release
-  - v4.2: Prior release
+  - v4.2: Current release
+  - v4.1: Prior release
   - v3.7: Current LTS
 
 ## Reporting process

.github/workflows/assigner.yml

@@ -34,17 +34,16 @@ jobs:
         persist-credentials: false
 
     - name: Set up Python
-      uses: zephyrproject-rtos/action-python-env@32e53bef090c33d53aa94f1d9a9d29c93cfdc5f7 # main
+      uses: zephyrproject-rtos/action-python-env@ace91a63fd503cd618ff1eb83fbcf302dabd7d44 # main
       with:
         python-version: 3.12
 
-    - name: Fetch west.yml/Maintainer.yml from pull request
+    - name: Fetch west.yml from pull request
       if: >
-        github.event_name == 'pull_request_target' && github.base_ref == 'main'
+        github.event_name == 'pull_request_target'
       run: |
         git fetch origin pull/${{ github.event.pull_request.number }}/merge
         git show FETCH_HEAD:west.yml > pr_west.yml
-        git show FETCH_HEAD:MAINTAINERS.yml > pr_MAINTAINERS.yml
 
     - name: west setup
       if: >
@@ -63,11 +62,7 @@ jobs:
         FLAGS+=" -r ${{ github.event.repository.name }}"
         FLAGS+=" -M MAINTAINERS.yml"
         if [ "${{ github.event_name }}" = "pull_request_target" ]; then
-          if [ "${{ github.base_ref }}" != "main" ]; then
-            FLAGS+=" -P ${{ github.event.pull_request.number }} --updated-manifest pr_west.yml --updated-maintainer-file pr_MAINTAINERS.yml"
-          else
-            FLAGS+=" -P ${{ github.event.pull_request.number }}"
-          fi
+          FLAGS+=" -P ${{ github.event.pull_request.number }} --updated-manifest pr_west.yml"
         elif [ "${{ github.event_name }}" = "issues" ]; then
           FLAGS+=" -I ${{ github.event.issue.number }}"
         elif [ "${{ github.event_name }}" = "schedule" ]; then
@@ -76,13 +71,4 @@ jobs:
           echo "Unknown event: ${{ github.event_name }}"
           exit 1
         fi
-        python3 scripts/ci/set_assignees.py $FLAGS
-
-    - name: Check maintainer file changes
-      if: >
-        github.event_name == 'pull_request_target' && github.base_ref == 'main'
-      env:
-        GITHUB_TOKEN: ${{ secrets.ZB_PR_ASSIGNER_GITHUB_TOKEN }}
-      run: |
-        python  ./scripts/ci/check_maintainer_changes.py  \
-          --repo zephyrproject-rtos/zephyr MAINTAINERS.yml pr_MAINTAINERS.yml
+        python3 scripts/set_assignees.py $FLAGS

.github/workflows/bsim-tests-publish.yaml

@@ -24,7 +24,7 @@ jobs:
           run_id: ${{ github.event.workflow_run.id }}
 
       - name: Publish BabbleSim Test Results
-        uses: EnricoMi/publish-unit-test-result-action@34d7c956a59aed1bfebf31df77b8de55db9bbaaf # v2.21.0
+        uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0
         with:
           check_name: BabbleSim Test Results
           comment_mode: off

.github/workflows/bsim-tests.yaml

@@ -42,7 +42,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.7.20251127
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.6.20251003
       options: '--entrypoint /bin/bash'
     env:
       ZEPHYR_TOOLCHAIN_VARIANT: zephyr
@@ -189,7 +189,7 @@ jobs:
 
       - name: Upload Unit Test Results in HTML
         if: always()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: HTML Unit Test Results
           if-no-files-found: ignore
@@ -197,7 +197,7 @@ jobs:
             junit.html
 
       - name: Publish Unit Test Results
-        uses: EnricoMi/publish-unit-test-result-action@34d7c956a59aed1bfebf31df77b8de55db9bbaaf # v2.21.0
+        uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0
         with:
           check_name: Bsim Test Results
           files: "junit.xml"
@@ -205,7 +205,7 @@ jobs:
 
       - name: Upload Event Details
         if: always()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: event
           path: |

.github/workflows/bug_snapshot.yaml

@@ -51,7 +51,7 @@ jobs:
         echo "BUGS_PICKLE_PATH=${BUGS_PICKLE_PATH}" >> ${GITHUB_ENV}
 
     - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0
+      uses: aws-actions/configure-aws-credentials@a03048d87541d1d9fcf2ecf528a4a65ba9bd7838 # v5.0.0
       with:
         aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_SECRET_ACCESS_KEY }}

.github/workflows/clang.yaml

@@ -18,7 +18,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.7.20251127
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.6.20251003
       options: '--entrypoint /bin/bash'
     strategy:
       fail-fast: false
@@ -123,7 +123,7 @@ jobs:
 
       - name: Upload Unit Test Results
         if: always()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Unit Test Results (Subset ${{ matrix.subset }})
           path: |
@@ -146,7 +146,7 @@ jobs:
           persist-credentials: false
 
       - name: Download Artifacts
-        uses: actions/download-artifact@018cc2cf5baa6db3ef3c5f8a56943fffe632ef53 # v6.0.0
+        uses: actions/download-artifact@634f93cb2916e3fdff6788551b99b062d0335ce0 # v5.0.0
         with:
           path: artifacts
 
@@ -168,7 +168,7 @@ jobs:
 
       - name: Upload Unit Test Results in HTML
         if: always()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: HTML Unit Test Results
           if-no-files-found: ignore
@@ -176,7 +176,7 @@ jobs:
             junit-clang.html
 
       - name: Publish Unit Test Results
-        uses: EnricoMi/publish-unit-test-result-action@34d7c956a59aed1bfebf31df77b8de55db9bbaaf # v2.21.0
+        uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0
         if: always()
         with:
           check_name: Unit Test Results

.github/workflows/codecov.yaml

@@ -20,7 +20,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.7.20251127
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.6.20251003
       options: '--entrypoint /bin/bash'
     strategy:
       fail-fast: false
@@ -126,7 +126,7 @@ jobs:
 
       - name: Upload Doxygen Coverage Results
         if: matrix.platform == 'unit_testing'
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: doxygen-coverage-results
           path: |
@@ -145,7 +145,7 @@ jobs:
 
       - name: Upload Coverage Results
         if: always()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Coverage Data (Subset ${{ matrix.normalized }})
           path: |
@@ -177,7 +177,7 @@ jobs:
           pip install -r scripts/requirements-actions.txt --require-hashes
 
       - name: Download Artifacts
-        uses: actions/download-artifact@018cc2cf5baa6db3ef3c5f8a56943fffe632ef53 # v6.0.0
+        uses: actions/download-artifact@634f93cb2916e3fdff6788551b99b062d0335ce0 # v5.0.0
         with:
           path: coverage/reports
 
@@ -242,7 +242,7 @@ jobs:
 
       - name: Upload Merged Coverage Results and Report
         if: always()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Coverage Data and report
           path: |

.github/workflows/codeql.yml

@@ -39,7 +39,7 @@ jobs:
         uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0
 
       - name: Initialize CodeQL
-        uses: github/codeql-action/init@0499de31b99561a6d14a36a5f662c2a54f91beee # v4.31.2
+        uses: github/codeql-action/init@64d10c13136e1c5bce3e5fbde8d4906eeaafc885 # v3.30.6
         with:
           languages: ${{ matrix.language }}
           build-mode: ${{ matrix.build-mode }}
@@ -53,6 +53,6 @@ jobs:
           exit 0
 
       - name: Perform CodeQL Analysis
-        uses: github/codeql-action/analyze@0499de31b99561a6d14a36a5f662c2a54f91beee # v4.31.2
+        uses: github/codeql-action/analyze@64d10c13136e1c5bce3e5fbde8d4906eeaafc885 # v3.30.6
         with:
           category: "/language:${{matrix.language}}"

.github/workflows/compliance.yml

@@ -91,14 +91,14 @@ jobs:
         ./scripts/ci/check_compliance.py --annotate $excludes -c origin/${BASE_REF}..
 
     - name: upload-results
-      uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       continue-on-error: true
       with:
         name: compliance.xml
         path: compliance.xml
 
     - name: Upload dts linter patch
-      uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       continue-on-error: true
       if: hashFiles('dts_linter.patch') != ''
       with:

.github/workflows/daily_test_version.yml

@@ -20,7 +20,7 @@ jobs:
 
     steps:
     - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0
+      uses: aws-actions/configure-aws-credentials@a03048d87541d1d9fcf2ecf528a4a65ba9bd7838 # v5.0.0
       with:
         aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }}

.github/workflows/doc-build.yml

@@ -15,8 +15,8 @@ permissions:
   contents: read
 
 env:
-  DOXYGEN_VERSION: 1.15.0
-  DOXYGEN_SHA256SUM: 0ec2e5b2c3cd82b7106d19cb42d8466450730b8cb7a9e85af712be38bf4523a1
+  DOXYGEN_VERSION: 1.14.0
+  DOXYGEN_MD5SUM: e761a5097ae20ecccfd02041925f102a
   JOB_COUNT: 8
 
 jobs:
@@ -59,7 +59,7 @@ jobs:
     runs-on:
       group: zephyr-runner-v2-linux-x64-4xlarge
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.7.20251127
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.6.20251003
       options: '--entrypoint /bin/bash'
     timeout-minutes: 60
     concurrency:
@@ -156,13 +156,13 @@ jobs:
         tar --use-compress-program="xz -T0" -cf api-coverage.tar.xz coverage-report
 
     - name: Upload HTML output
-      uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       with:
         name: html-output
         path: html-output.tar.xz
 
     - name: Upload Doxygen coverage artifacts
-      uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       with:
         name: api-coverage
         path: api-coverage.tar.xz
@@ -183,7 +183,7 @@ jobs:
         echo "API Coverage Report will be available shortly at: ${API_COVERAGE_URL}" >> $GITHUB_STEP_SUMMARY
 
     - name: Upload PR number
-      uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       if: github.event_name == 'pull_request'
       with:
         name: pr_num
@@ -221,7 +221,7 @@ jobs:
           texlive-fonts-recommended texlive-fonts-extra texlive-xetex \
           imagemagick fonts-noto xindy
         wget --no-verbose "https://github.com/doxygen/doxygen/releases/download/Release_${DOXYGEN_VERSION//./_}/doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz"
-        echo "${DOXYGEN_SHA256SUM}  doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" | sha256sum -c
+        echo "${DOXYGEN_MD5SUM}  doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" | md5sum -c
         if [ $? -ne 0 ]; then
           echo "Failed to verify doxygen tarball"
           exit 1
@@ -259,7 +259,7 @@ jobs:
 
     - name: upload-build
       if: always()
-      uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       with:
         name: pdf-output
         if-no-files-found: ignore

.github/workflows/doc-publish-pr.yml

@@ -66,7 +66,7 @@ jobs:
 
     - name: Configure AWS Credentials
       if: steps.download-artifacts.outputs.found_artifact == 'true'
-      uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0
+      uses: aws-actions/configure-aws-credentials@a03048d87541d1d9fcf2ecf528a4a65ba9bd7838 # v5.0.0
       with:
         aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_PR_SECRET_ACCESS_KEY }}

.github/workflows/doc-publish.yml

@@ -40,7 +40,7 @@ jobs:
         fi
 
     - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0
+      uses: aws-actions/configure-aws-credentials@a03048d87541d1d9fcf2ecf528a4a65ba9bd7838 # v5.0.0
       with:
         aws-access-key-id: ${{ vars.AWS_DOCS_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_DOCS_SECRET_ACCESS_KEY }}

.github/workflows/footprint-tracking.yml

@@ -28,7 +28,7 @@ jobs:
       group: zephyr-runner-v2-linux-x64-4xlarge
     if: github.repository_owner == 'zephyrproject-rtos'
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.7.20251127
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.6.20251003
       options: '--entrypoint /bin/bash'
     defaults:
       run:
@@ -89,7 +89,7 @@ jobs:
           west update 2>&1 1> west.update.log || west update 2>&1 1> west.update2.log
 
       - name: Configure AWS Credentials
-        uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0
+        uses: aws-actions/configure-aws-credentials@a03048d87541d1d9fcf2ecf528a4a65ba9bd7838 # v5.0.0
         with:
           aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }}
           aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }}

.github/workflows/hello_world_multiplatform.yaml

@@ -80,7 +80,7 @@ jobs:
 
       - name: Upload artifacts
         if: failure()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           if-no-files-found: ignore
           path:

.github/workflows/issue_count.yml

@@ -38,14 +38,14 @@ jobs:
         token: ${{ secrets.GITHUB_TOKEN }}
 
     - name: upload-stats
-      uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       continue-on-error: true
       with:
         name: ${{ env.OUTPUT_FILE_NAME }}
         path: ${{ env.OUTPUT_FILE_NAME }}
 
     - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@00943011d9042930efac3dcd3a170e4273319bc8 # v5.1.0
+      uses: aws-actions/configure-aws-credentials@a03048d87541d1d9fcf2ecf528a4a65ba9bd7838 # v5.0.0
       with:
         aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }}

.github/workflows/license_check.yml

@@ -20,7 +20,7 @@ jobs:
       with:
         directory-to-scan: 'scan/'
     - name: Artifact Upload
-      uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       with:
         name: scancode
         path: ./artifacts

.github/workflows/maintainer_check.yml

@@ -0,0 +1,43 @@
+name: Maintainer file check
+
+on:
+  pull_request_target:
+    branches:
+      - main
+    paths:
+      - MAINTAINERS.yml
+
+permissions:
+  contents: read
+
+jobs:
+  assignment:
+    name: Check MAINTAINERS.yml changes
+    runs-on: ubuntu-24.04
+
+    steps:
+      - name: Check out source code
+        uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0
+
+      - name: Set up Python
+        uses: actions/setup-python@e797f83bcb11b83ae66e0230d6156d7c80228e7c # v6.0.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+
+      - name: Install Python packages
+        run: |
+          pip install -r scripts/requirements-actions.txt --require-hashes
+
+      - name: Fetch MAINTAINERS.yml from pull request
+        run: |
+          git fetch origin pull/${{ github.event.pull_request.number }}/merge
+          git show FETCH_HEAD:MAINTAINERS.yml > pr_MAINTAINERS.yml
+
+      - name: Check maintainer file changes
+        env:
+          GITHUB_TOKEN: ${{ secrets.ZB_PR_ASSIGNER_GITHUB_TOKEN }}
+        run: |
+          python  ./scripts/ci/check_maintainer_changes.py  \
+            --repo zephyrproject-rtos/zephyr MAINTAINERS.yml pr_MAINTAINERS.yml

.github/workflows/pr_metadata_check.yml

@@ -13,15 +13,10 @@ on:
 permissions:
   contents: read
 
-concurrency:
-  group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
-  cancel-in-progress: true
-
 jobs:
   do-not-merge:
     name: Prevent Merging
     runs-on: ubuntu-24.04
-    timeout-minutes: 30
     steps:
       - name: Checkout
         uses: actions/checkout@08c6903cd8c0fde910a37f88322edcfb5dd907a8 # v5.0.0

.github/workflows/release.yml

@@ -31,7 +31,7 @@ jobs:
           args: spdx -o zephyr-${{ steps.get_version.outputs.VERSION }}.spdx
 
       - name: upload-results
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         continue-on-error: true
         with:
           name: zephyr-${{ steps.get_version.outputs.VERSION }}.spdx

.github/workflows/scorecards.yml

@@ -47,7 +47,7 @@ jobs:
       # uploads of run results in SARIF format to the repository Actions tab.
       # https://docs.github.com/en/actions/advanced-guides/storing-workflow-data-as-artifacts
       - name: "Upload artifact"
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: SARIF file
           path: results.sarif
@@ -56,6 +56,6 @@ jobs:
       # Upload the results to GitHub's code scanning dashboard (optional).
       # Commenting out will disable upload of results to your repo's Code Scanning dashboard
       - name: "Upload to code-scanning"
-        uses: github/codeql-action/upload-sarif@0499de31b99561a6d14a36a5f662c2a54f91beee # v4.31.2
+        uses: github/codeql-action/upload-sarif@64d10c13136e1c5bce3e5fbde8d4906eeaafc885 # v3.30.6
         with:
           sarif_file: results.sarif

.github/workflows/twister.yaml

@@ -127,7 +127,7 @@ jobs:
     needs: twister-build-prep
     if: needs.twister-build-prep.outputs.size != 0
     container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.7.20251127
+      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.28.6.20251003
       options: '--entrypoint /bin/bash'
     strategy:
       fail-fast: false
@@ -192,7 +192,7 @@ jobs:
           echo "$HOME/.cargo/bin" >> $GITHUB_PATH
 
           west init -l . || true
-          west config manifest.group-filter -- +ci,+optional,+testing
+          west config manifest.group-filter -- +ci,+optional
           west config --global update.narrow true
           west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject)
           west forall -c 'git reset --hard HEAD'
@@ -283,7 +283,7 @@ jobs:
 
       - name: Upload Unit Test Results
         if: always()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Unit Test Results (Subset ${{ matrix.subset }})
           if-no-files-found: ignore
@@ -305,7 +305,7 @@ jobs:
 
       - if: matrix.subset == 1 && github.event_name == 'push'
         name: Upload the list of Python packages
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Frozen PIP package set
           path: |
@@ -341,7 +341,7 @@ jobs:
           pip install -r scripts/requirements-actions.txt --require-hashes
 
       - name: Download Artifacts
-        uses: actions/download-artifact@018cc2cf5baa6db3ef3c5f8a56943fffe632ef53 # v6.0.0
+        uses: actions/download-artifact@634f93cb2916e3fdff6788551b99b062d0335ce0 # v5.0.0
         with:
           path: artifacts
 
@@ -352,7 +352,7 @@ jobs:
 
       - name: Upload Unit Test Results
         if: always()
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Unit Test Results
           if-no-files-found: ignore
@@ -367,7 +367,7 @@ jobs:
           token: ${{ secrets.CODECOV_TOKEN }}
 
       - name: Publish Unit Test Results
-        uses: EnricoMi/publish-unit-test-result-action@34d7c956a59aed1bfebf31df77b8de55db9bbaaf # v2.21.0
+        uses: EnricoMi/publish-unit-test-result-action@3a74b2957438d0b6e2e61d67b05318aa25c9e6c6 # v2.20.0
         with:
           check_name: Unit Test Results
           files: "**/twister.xml"
@@ -384,7 +384,7 @@ jobs:
 
       - name: Upload Twister Analysis Results
         if: needs.twister-build.result == 'failure'
-        uses: actions/upload-artifact@330a01c490aca151604b8cf639adc76d48f6c5d4 # v5.0.0
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Twister Analysis Results
           if-no-files-found: ignore

.github/workflows/twister_tests_blackbox.yml

@@ -50,8 +50,6 @@ jobs:
         app-path: zephyr
         toolchains: all
         enable-ccache: false
-        west-group-filter: -tools,-bootloader,-babblesim,-hal
-        west-project-filter: -nrf_hw_models,+cmsis,+hal_xtensa,+cmsis_6
 
     - name: Run Pytest For Twister Black Box Tests
       if: ${{ runner.os == 'Linux' }}
@@ -66,3 +64,125 @@ jobs:
         echo "Run twister tests"
         source zephyr-env.sh
         PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox/
+
+    - name: Build firmware No. 1 - basic
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        ./scripts/twister --runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS
+
+    - name: Build firmware No. 2 - save and load with emulation only
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister --save-tests tests.file $BASIC_FLAGS
+        ./scripts/twister --load-tests tests.file --emulation-only $BASIC_FLAGS
+        rm tests.file
+
+    - name: Build firmware No. 3 - print out test plan
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister --test-tree -T tests/kernel/spinlock $BASIC_FLAGS
+
+    - name: Build firmware No. 4 - integration, exclude tag, filter, shuffle, dry run
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister --dry-run --integration --subset 1/3 --shuffle-tests --shuffle-tests-seed 1 --filter runnable --exclude-tag audio --exclude-tag driver $BASIC_FLAGS
+
+    - name: Build firmware No. 5 - test, arch, vendor, exclude-platform, platform-reports
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister --test kernel.multiprocessing.spinlock --arch x86 --exclude-platform qemu_x86_64 --vendor qemu --platform-reports $BASIC_FLAGS
+
+    - name: Build firmware No. 6 - subtest, platform, rom-ram report, ROM footprint report from buildlog, size report
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --create-rom-ram-report --footprint-report ROM --enable-size-report --footprint-from-buildlog $BASIC_FLAGS --detailed-test-id
+
+    - name: Build firmware No. 7 - list tags
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --list-tags $BASIC_FLAGS --detailed-test-id
+
+    - name: Build firmware No. 8 - list tests
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister -T tests/posix/common --list-tests $BASIC_FLAGS
+
+    - name: Build firmware No. 9 - report flags - dir, name, suffix, summary, all-options, filtered
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --platform qemu_x86 --report-dir . --report-name test_name --report-suffix suffix --report-summary 0 --report-all-options --report-filtered $BASIC_FLAGS --detailed-test-id
+
+    - name: Build firmware No. 10 - force platform and toolchain, log level, timestamps, logfile
+      working-directory: zephyr
+      shell: bash
+      run: |
+        if [ "${{ runner.os }}" = "macOS" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --build-only"
+        elif [ "${{ runner.os }}" = "Windows" ]; then
+          EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O /tmp/twister-out"
+        fi
+        BASIC_FLAGS="--runtime-artifact-cleanup --force-color --inline-logs -v $EXTRA_TWISTER_FLAGS"
+        ./scripts/twister --sub-test kernel.multiprocessing.spinlock.minimallibc.spinlock.spinlock_basic --force-platform --platform qemu_x86 --force-toolchain --log-level WARNING --log-file log.file $BASIC_FLAGS --detailed-test-id
+        rm log.file

.ruff-excludes.toml

@@ -5,6 +5,21 @@
 # remove entries for files that pass CI compliance testing.
 
 [lint.per-file-ignores]
+"./arch/x86/gen_gdt.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./arch/x86/gen_idt.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP030",    # https://docs.astral.sh/ruff/rules/format-literals
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./arch/x86/gen_mmu.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP034",    # https://docs.astral.sh/ruff/rules/extraneous-parentheses
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
 "./arch/x86/zefi/zefi.py" = [
     "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
@@ -119,8 +134,196 @@
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
     "SIM112",   # https://docs.astral.sh/ruff/rules/uncapitalized-environment-variables
 ]
+"./scripts/build/check_init_priorities.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F401",     # https://docs.astral.sh/ruff/rules/unused-import
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
+"./scripts/build/check_init_priorities_test.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+]
+"./scripts/build/elf_parser.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/file2hex.py" = [
+    "B023",     # https://docs.astral.sh/ruff/rules/function-uses-loop-variable
+    "B905",     # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict
+]
 "./scripts/build/gen_app_partitions.py" = [
     "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP030",    # https://docs.astral.sh/ruff/rules/format-literals
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/gen_cfb_font_header.py" = [
+    "E101",     # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/gen_device_deps.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/gen_image_info.py" = [
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+]
+"./scripts/build/gen_isr_tables.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/gen_isr_tables_parser_carrays.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP030",    # https://docs.astral.sh/ruff/rules/format-literals
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/gen_isr_tables_parser_local.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP030",    # https://docs.astral.sh/ruff/rules/format-literals
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/gen_kobject_list.py" = [
+    "E101",     # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "SIM401",   # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+    "W191",     # https://docs.astral.sh/ruff/rules/tab-indentation
+]
+"./scripts/build/gen_kobject_placeholders.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+]
+"./scripts/build/gen_offset_header.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/build/gen_relocate_app.py" = [
+    "E101",     # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs
+]
+"./scripts/build/gen_strerror_table.py" = [
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "SIM105",   # https://docs.astral.sh/ruff/rules/suppressible-exception
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/build/gen_strsignal_table.py" = [
+    "SIM105",   # https://docs.astral.sh/ruff/rules/suppressible-exception
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/build/gen_symtab.py" = [
+    "B007",     # https://docs.astral.sh/ruff/rules/unused-loop-control-variable
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/build/gen_syscalls.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "E713",     # https://docs.astral.sh/ruff/rules/not-in-test
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/llext_inject_slids.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM113",   # https://docs.astral.sh/ruff/rules/enumerate-for-loop
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
+"./scripts/build/llext_prepare_exptab.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM113",   # https://docs.astral.sh/ruff/rules/enumerate-for-loop
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
+"./scripts/build/mergehex.py" = [
+    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/build/parse_syscalls.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/build/process_gperf.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/build/subfolder_list.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/build/uf2conv.py" = [
+    "B011",     # https://docs.astral.sh/ruff/rules/assert-false
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "E711",     # https://docs.astral.sh/ruff/rules/none-comparison
+    "E722",     # https://docs.astral.sh/ruff/rules/bare-except
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "SIM103",   # https://docs.astral.sh/ruff/rules/needless-bool
+    "SIM118",   # https://docs.astral.sh/ruff/rules/in-dict-keys
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/ci/check_compliance.py" = [
+    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "E741",     # https://docs.astral.sh/ruff/rules/ambiguous-variable-name
+    "F401",     # https://docs.astral.sh/ruff/rules/unused-import
+    "SIM112",   # https://docs.astral.sh/ruff/rules/uncapitalized-environment-variables
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/ci/coverage/coverage_analysis.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/ci/errno.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/ci/guideline_check.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/ci/stats/merged_prs.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+]
+"./scripts/ci/test_plan.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
+    "E401",     # https://docs.astral.sh/ruff/rules/multiple-imports-on-one-line
+    "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
 ]
 "./scripts/ci/upload_test_results_es.py" = [
     "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
@@ -128,14 +331,62 @@
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
     "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
 ]
-"./scripts/coredump/coredump_parser/elf_parser.py" = [
+"./scripts/ci/version_mgr.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
     "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/coredump/coredump_gdbserver.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+]
+"./scripts/coredump/coredump_parser/elf_parser.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
 ]
 "./scripts/coredump/coredump_parser/log_parser.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
     "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "UP030",    # https://docs.astral.sh/ruff/rules/format-literals
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
 ]
 "./scripts/coredump/coredump_serial_log_parser.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
     "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/coredump/gdbstubs/arch/arm64.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
+"./scripts/coredump/gdbstubs/arch/arm_cortex_m.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
+"./scripts/coredump/gdbstubs/arch/risc_v.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
+"./scripts/coredump/gdbstubs/arch/x86.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
+"./scripts/coredump/gdbstubs/arch/x86_64.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
+]
+"./scripts/coredump/gdbstubs/arch/xtensa.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM113",   # https://docs.astral.sh/ruff/rules/enumerate-for-loop
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/coredump/gdbstubs/gdbstub.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
 ]
 "./scripts/dts/gen_defines.py" = [
     "B007",     # https://docs.astral.sh/ruff/rules/unused-loop-control-variable
@@ -891,6 +1142,9 @@
 
 [format]
 exclude = [
+    "./arch/x86/gen_gdt.py",
+    "./arch/x86/gen_idt.py",
+    "./arch/x86/gen_mmu.py",
     "./arch/x86/zefi/zefi.py",
     "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py",
     "./doc/_scripts/gen_devicetree_rest.py",
@@ -920,8 +1174,52 @@ exclude = [
     "./samples/subsys/testsuite/pytest/basic/pytest/conftest.py",
     "./samples/subsys/testsuite/pytest/basic/pytest/test_sample.py",
     "./samples/subsys/zbus/remote_mock/remote_mock.py",
+    "./scripts/build/check_init_priorities.py",
+    "./scripts/build/check_init_priorities_test.py",
+    "./scripts/build/elf_parser.py",
+    "./scripts/build/file2hex.py",
+    "./scripts/build/gen_app_partitions.py",
+    "./scripts/build/gen_cfb_font_header.py",
+    "./scripts/build/gen_device_deps.py",
+    "./scripts/build/gen_image_info.py",
+    "./scripts/build/gen_isr_tables.py",
+    "./scripts/build/gen_isr_tables_parser_carrays.py",
+    "./scripts/build/gen_isr_tables_parser_local.py",
+    "./scripts/build/gen_kobject_list.py",
+    "./scripts/build/gen_kobject_placeholders.py",
+    "./scripts/build/gen_offset_header.py",
+    "./scripts/build/gen_strerror_table.py",
+    "./scripts/build/gen_strsignal_table.py",
+    "./scripts/build/gen_symtab.py",
+    "./scripts/build/gen_syscalls.py",
+    "./scripts/build/llext_inject_slids.py",
+    "./scripts/build/llext_prepare_exptab.py",
+    "./scripts/build/mergehex.py",
+    "./scripts/build/parse_syscalls.py",
+    "./scripts/build/process_gperf.py",
+    "./scripts/build/subfolder_list.py",
+    "./scripts/build/uf2conv.py",
     "./scripts/check_maintainers.py",
+    "./scripts/ci/check_compliance.py",
+    "./scripts/ci/coverage/coverage_analysis.py",
+    "./scripts/ci/errno.py",
+    "./scripts/ci/guideline_check.py",
+    "./scripts/ci/stats/merged_prs.py",
+    "./scripts/ci/test_plan.py",
+    "./scripts/ci/twister_report_analyzer.py",
     "./scripts/ci/upload_test_results_es.py",
+    "./scripts/ci/version_mgr.py",
+    "./scripts/coredump/coredump_gdbserver.py",
+    "./scripts/coredump/coredump_parser/elf_parser.py",
+    "./scripts/coredump/coredump_parser/log_parser.py",
+    "./scripts/coredump/coredump_serial_log_parser.py",
+    "./scripts/coredump/gdbstubs/arch/arm64.py",
+    "./scripts/coredump/gdbstubs/arch/arm_cortex_m.py",
+    "./scripts/coredump/gdbstubs/arch/risc_v.py",
+    "./scripts/coredump/gdbstubs/arch/x86.py",
+    "./scripts/coredump/gdbstubs/arch/x86_64.py",
+    "./scripts/coredump/gdbstubs/arch/xtensa.py",
+    "./scripts/coredump/gdbstubs/gdbstub.py",
     "./scripts/dts/gen_defines.py",
     "./scripts/dts/gen_driver_kconfig_dts.py",
     "./scripts/dts/gen_dts_cmake.py",
@@ -952,6 +1250,15 @@ exclude = [
     "./scripts/list_boards.py",
     "./scripts/list_hardware.py",
     "./scripts/list_shields.py",
+    "./scripts/logging/dictionary/database_gen.py",
+    "./scripts/logging/dictionary/dictionary_parser/data_types.py",
+    "./scripts/logging/dictionary/dictionary_parser/log_database.py",
+    "./scripts/logging/dictionary/dictionary_parser/log_parser.py",
+    "./scripts/logging/dictionary/dictionary_parser/log_parser_v1.py",
+    "./scripts/logging/dictionary/dictionary_parser/log_parser_v3.py",
+    "./scripts/logging/dictionary/dictionary_parser/utils.py",
+    "./scripts/logging/dictionary/log_parser.py",
+    "./scripts/logging/dictionary/log_parser_uart.py",
     "./scripts/make_bugs_pickle.py",
     "./scripts/net/enumerate_http_status.py",
     "./scripts/profiling/stackcollapse.py",
@@ -1054,6 +1361,7 @@ exclude = [
     "./scripts/utils/pinctrl_nrf_migrate.py",
     "./scripts/utils/twister_to_list.py",
     "./scripts/west_commands/bindesc.py",
+    "./scripts/west_commands/blobs.py",
     "./scripts/west_commands/boards.py",
     "./scripts/west_commands/build.py",
     "./scripts/west_commands/build_helpers.py",
@@ -1166,5 +1474,6 @@ exclude = [
     "./tests/net/socket/tls_configurations/pytest/test_app_vs_openssl.py",
     "./tests/net/socket/udp/generate-c-string.py",
     "./tests/subsys/debug/gdbstub/pytest/test_gdbstub.py",
+    "./tests/subsys/logging/dictionary/pytest/test_logging_dictionary.py",
     "./tests/ztest/ztest_param/pytest/test_parameters.py",
 ]

CMakeLists.txt

@@ -311,13 +311,8 @@ compiler_simple_options(simple_options)
 toolchain_linker_add_compiler_options(${simple_options})
 
 if(CONFIG_LTO)
-  if(CONFIG_LTO_SINGLE_THREADED)
-    zephyr_compile_options($<TARGET_PROPERTY:compiler,optimization_lto_st>)
-    add_link_options($<TARGET_PROPERTY:linker,lto_arguments_st>)
-  else()
-    zephyr_compile_options($<TARGET_PROPERTY:compiler,optimization_lto>)
-    add_link_options($<TARGET_PROPERTY:linker,lto_arguments>)
-  endif()
+  zephyr_compile_options($<TARGET_PROPERTY:compiler,optimization_lto>)
+  add_link_options($<TARGET_PROPERTY:linker,lto_arguments>)
 endif()
 
 if(CONFIG_STD_C23)

CODE_OF_CONDUCT.md

@@ -1,4 +1,4 @@
-# Zephyr Project Code of Conduct
+# Contributor Covenant Code of Conduct
 
 ## Our Pledge
 

Kconfig.zephyr

@@ -9,10 +9,6 @@ source "Kconfig.constants"
 
 osource "$(APPLICATION_SOURCE_DIR)/VERSION"
 
-# This should be sourced early since the autogen Kconfig.dts options
-# and macros may get used by shields/boards/SoC defconfig or modules.
-source "dts/Kconfig"
-
 # Include Kconfig.defconfig files first so that they can override defaults and
 # other symbol/choice properties by adding extra symbol/choice definitions.
 # After merging all definitions for a symbol/choice, Kconfig picks the first
@@ -37,6 +33,10 @@ osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig.defconfig"
 # This loads the testsuite defconfig
 source "subsys/testsuite/Kconfig.defconfig"
 
+# This should be early since the autogen Kconfig.dts symbols may get
+# used by modules
+source "dts/Kconfig"
+
 menu "Modules"
 
 source "modules/Kconfig"
@@ -357,19 +357,18 @@ menu "Compiler Options"
 
 config REQUIRES_STD_C99
 	bool
-	select DEPRECATED
 	help
 	  Hidden option to select compiler support C99 standard or higher.
 
 config REQUIRES_STD_C11
 	bool
-	select DEPRECATED
 	select REQUIRES_STD_C99
 	help
 	  Hidden option to select compiler support C11 standard or higher.
 
 config REQUIRES_STD_C17
 	bool
+	select REQUIRES_STD_C11
 	help
 	  Hidden option to select compiler support C17 standard or higher.
 
@@ -382,28 +381,27 @@ config REQUIRES_STD_C23
 choice STD_C
 	prompt "C Standard"
 	default STD_C23 if REQUIRES_STD_C23
-	default STD_C17
+	default STD_C17 if REQUIRES_STD_C17
+	default STD_C11 if REQUIRES_STD_C11
+	default STD_C99
 	help
 	  C Standards.
 
 config STD_C90
-	bool "C90 [DEPRECATED]"
-	select DEPRECATED
+	bool "C90"
 	depends on !REQUIRES_STD_C99
 	help
 	  1989 C standard as completed in 1989 and ratified by ISO/IEC
 	  as ISO/IEC 9899:1990. This version is known as "ANSI C".
 
 config STD_C99
-	bool "C99 [DEPRECATED]"
-	select DEPRECATED
+	bool "C99"
 	depends on !REQUIRES_STD_C11
 	help
 	  1999 C standard.
 
 config STD_C11
-	bool "C11 [DEPRECATED]"
-	select DEPRECATED
+	bool "C11"
 	depends on !REQUIRES_STD_C17
 	help
 	  2011 C standard.
@@ -482,9 +480,7 @@ choice COMPILER_OPTIMIZATIONS
 	prompt "Optimization level"
 	default NO_OPTIMIZATIONS    if COVERAGE
 	default DEBUG_OPTIMIZATIONS if DEBUG
-	# gcc 14.3 -Os is broken on riscv. This setting should be in the SDK, it's here for testing
-	default SPEED_OPTIMIZATIONS if "$(TOOLCHAIN_VARIANT_COMPILER)" = "gnu" && RISCV
-	default SIZE_OPTIMIZATIONS_AGGRESSIVE if "$(TOOLCHAIN_VARIANT_COMPILER)" = "llvm"
+	default SIZE_OPTIMIZATIONS_AGGRESSIVE if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "llvm"
 	default SIZE_OPTIMIZATIONS
 	help
 	  Note that these flags shall only control the compiler
@@ -533,14 +529,6 @@ config LTO
 	help
 	  This option enables Link Time Optimization.
 
-config LTO_SINGLE_THREADED
-	bool "Single-threaded LTO"
-	depends on LTO
-	help
-	  This option instructs the linker to use a single thread to process
-	  LTO. See the following issue for more info:
-	  https://github.com/zephyrproject-rtos/sdk-ng/issues/1038
-
 config COMPILER_WARNINGS_AS_ERRORS
 	bool "Treat warnings as errors"
 	help
@@ -1073,6 +1061,8 @@ menu "Boot Options"
 
 config IS_BOOTLOADER
 	bool "Act as a bootloader"
+	depends on XIP
+	depends on ARM
 	help
 	  This option indicates that Zephyr will act as a bootloader to execute
 	  a separate Zephyr image payload.

VERSION

@@ -1,5 +1,5 @@
 VERSION_MAJOR = 4
 VERSION_MINOR = 3
-PATCHLEVEL = 99
+PATCHLEVEL = 0
 VERSION_TWEAK = 0
 EXTRAVERSION =

arch/Kconfig

@@ -137,8 +137,6 @@ config XTENSA
 	select THREAD_STACK_INFO
 	select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE
 	select ARCH_SUPPORTS_COREDUMP_STACK_PTR if !SMP
-	select ARCH_HAS_USERSPACE if XTENSA_MMU || XTENSA_MPU
-	imply ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU
 	help
 	  Xtensa architecture
 
@@ -155,6 +153,12 @@ config ARCH_POSIX
 	select BARRIER_OPERATIONS_BUILTIN
 	# POSIX arch based targets get their memory cleared on entry by the host OS
 	select SKIP_BSS_CLEAR
+	# Override the C standard used for compilation to C 2011
+	# This is due to some tests using _Static_assert which is a 2011 feature, but
+	# otherwise relying on compilers supporting it also when set to C99.
+	# This was in general ok, but with some host compilers and C library versions
+	# it led to problems. So we override it to 2011 for the native targets.
+	select REQUIRES_STD_C11
 	help
 	  POSIX (native) architecture
 
@@ -760,6 +764,13 @@ config ARCH_HAS_EXTRA_EXCEPTION_INFO
 config ARCH_HAS_GDBSTUB
 	bool
 
+config ARCH_HAS_COHERENCE
+	bool
+	help
+	  When selected, the architecture supports the
+	  arch_mem_coherent() API and can link into incoherent/cached
+	  memory using the ".cached" linker section.
+
 config ARCH_HAS_THREAD_LOCAL_STORAGE
 	bool
 
@@ -1078,22 +1089,10 @@ config ICACHE
 	help
 	  This option enables the support for the instruction cache (i-cache).
 
-config CACHE_HAS_MIRRORED_MEMORY_REGIONS
-	bool "Mirrored memory region(s) for both cached and uncached access"
-	depends on CPU_CACHE_INCOHERENT
-	help
-	  Enable this if hardware has mirrored memory regions at different
-	  addressed when accessing one would go through cache, but accessing
-	  the other would go to memory directly. A pointer can be cheaply
-	  converted to cached or uncached access.
-
-	  This applies to intra-CPU multiprocessing incoherence and makes only
-	  sense when MP_MAX_NUM_CPUS > 1.
-
 config CACHE_DOUBLEMAP
 	bool "Cache double-mapping support"
-	select CACHE_HAS_MIRRORED_MEMORY_REGIONS
-	select DEPRECATED
+	depends on CPU_CACHE_INCOHERENT
+	default y
 	help
 	  Double-mapping behavior where a pointer can be cheaply converted to
 	  point to the same cached/uncached memory at different locations.
@@ -1171,14 +1170,6 @@ config ARCH_CACHE
 	help
 	  Integrated on-core cache controller
 
-config SOC_CACHE
-	bool "SoC specific cache controller"
-	depends on SOC_HAS_CACHE_FUNCTIONS
-	help
-	  SoC specific cache controller.
-
-	  This requires soc_cache.h file to exist in search path.
-
 config EXTERNAL_CACHE
 	bool "External cache controller"
 	help
@@ -1186,14 +1177,6 @@ config EXTERNAL_CACHE
 
 endchoice
 
-config CACHE_CAN_SAY_MEM_COHERENCE
-	bool
-	help
-	  sys_cache_is_mem_coherent() is defined when enabled. This function can be
-	  used to determine if a pointer lies inside "coherence regions" and can be
-	  safely used in multiprocessor code without explicit flush or invalidate
-	  operations.
-
 endif # CACHE_MANAGEMENT
 
 endmenu

arch/arm/Kconfig

@@ -190,43 +190,4 @@ config HAS_SWO
 	help
 	  When enabled, indicates that SoC has an SWO output
 
-DT_CHOSEN_Z_DTCM := zephyr,dtcm
-DT_CHOSEN_Z_ITCM := zephyr,itcm
-
-choice
-	prompt "Vector table memory location"
-	depends on SRAM_VECTOR_TABLE
-	default ARM_VECTOR_TABLE_SRAM
-
-config ARM_VECTOR_TABLE_SRAM
-	bool "Place the vector table in DT Chosen SRAM instead of DT Chosen Flash"
-	help
-	  When executing in place (XiP), selecting this option will result in the
-	  interrupt vector table being relocated from DT 'zephyr,flash' chosen
-	  memory to DT 'zephyr,sram' chosen memory.
-
-config ARM_VECTOR_TABLE_DTCM
-	bool "Place the vector table in DT Chosen DTCM instead of DT Chosen Flash"
-	depends on $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
-	help
-	  When executing in place (XiP), selecting this option will result in the
-	  interrupt vector table being relocated from DT 'zephyr,flash' chosen
-	  memory to DT 'zephyr,dtcm' chosen memory. While the vector table is
-	  instruction-fetched during exception entry, a DTCM option is provided
-	  for systems where ITCM is unavailable. DTCM still offers low-latency,
-	  deterministic access compared to normal RAM, but is not the optimal
-	  location for instruction fetch performance.
-
-config ARM_VECTOR_TABLE_ITCM
-	bool "Place the vector table in DT Chosen ITCM instead of DT Chosen Flash"
-	depends on $(dt_chosen_enabled,$(DT_CHOSEN_Z_ITCM))
-	help
-	  When executing in place (XiP), selecting this option will result in the
-	  interrupt vector table being relocated from DT 'zephyr,flash' chosen
-	  memory to DT 'zephyr,itcm' chosen memory. ITCM provides single-cycle,
-	  deterministic instruction fetches via the CPU instruction bus, it offers
-	  the lowest interrupt latency and is the preferred location when available.
-
-endchoice
-
 endmenu

arch/arm/core/cortex_m/CMakeLists.txt

@@ -49,9 +49,9 @@ if(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT)
 endif()
 
 if(CONFIG_CORTEX_M_DWT)
-  if(CONFIG_TIMING_FUNCTIONS)
-    zephyr_library_sources(timing.c)
-  endif()
+	if(CONFIG_TIMING_FUNCTIONS)
+		zephyr_library_sources(timing.c)
+	endif()
 endif()
 
 if(CONFIG_SW_VECTOR_RELAY)

arch/arm/core/cortex_m/Kconfig

@@ -192,7 +192,6 @@ config CPU_CORTEX_M_HAS_CMSE
 
 config ARMV6_M_ARMV8_M_BASELINE
 	bool
-	select ATOMIC_OPERATIONS_BUILTIN if ARMV8_M_BASELINE
 	select ATOMIC_OPERATIONS_C if !ARMV8_M_BASELINE
 	select ISA_THUMB2
 	help

arch/arm/core/cortex_m/ram_vector_table.ld

@@ -28,11 +28,5 @@ SECTION_PROLOGUE(.sram_vt,,)
 	. += _vector_end - _vector_start;
 	MPU_ALIGN(_sram_vector_size);
 	_sram_vector_end = .;
-#if defined(CONFIG_ARM_VECTOR_TABLE_ITCM)
-} GROUP_DATA_LINK_IN(ITCM, ROMABLE_REGION)
-#elif defined(CONFIG_ARM_VECTOR_TABLE_DTCM)
-} GROUP_DATA_LINK_IN(DTCM, ROMABLE_REGION)
-#else
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
-#endif
 _sram_vector_size = _sram_vector_end - _sram_vector_start;

arch/arm/core/vector_table.ld

@@ -1,6 +1,5 @@
 /*
  * Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
- * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -58,8 +57,4 @@ INCLUDE isr_tables_vt.ld
 KEEP(*(.vectors))
 #endif
 
-#ifdef CONFIG_CPU_AARCH32_CORTEX_R
-KEEP(*(._bindesc_entry.*))
-#endif
-
 _vector_end = .;

arch/arm/include/cortex_m/dwt.h

@@ -82,7 +82,7 @@ static inline void dwt_access(bool ena)
 static inline int z_arm_dwt_init(void)
 {
 	/* Enable tracing */
-	DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk;
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
 
 	/* Unlock DWT access if any */
 	dwt_access(true);
@@ -149,7 +149,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void)
 	 * unpredictable if the DebugMonitor exception is triggered. We
 	 * assert that the CPU is in normal mode.
 	 */
-	__ASSERT((DCB->DHCSR & DCB_DHCSR_C_DEBUGEN_Msk) == 0,
+	__ASSERT((CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) == 0,
 		 "Cannot enable DBM when CPU is in Debug mode\n");
 
 #if defined(CONFIG_ARMV8_M_SE) && !defined(CONFIG_ARM_NONSECURE_FIRMWARE)
@@ -160,7 +160,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void)
 	 * when enabling the DebugMonitor exception, assert that
 	 * it is not targeting the Non Secure domain.
 	 */
-	__ASSERT((DCB->DEMCR & DCB_DEMCR_SDME_Msk) != 0, "DebugMonitor targets Non-Secure\n");
+	__ASSERT((CoreDebug->DEMCR & DCB_DEMCR_SDME_Msk) != 0, "DebugMonitor targets Non-Secure\n");
 #endif
 
 	/* The DebugMonitor handler priority is set already
@@ -169,7 +169,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void)
 	 */
 
 	/* Enable debug monitor exception triggered on debug events */
-	DCB->DEMCR |= DCB_DEMCR_MON_EN_Msk;
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_MON_EN_Msk;
 }
 
 #endif /* CONFIG_CORTEX_M_DWT */

arch/arm64/core/Kconfig

@@ -79,26 +79,6 @@ config CPU_CORTEX_A78
 	help
 	  This option signifies the use of a Cortex-A78 CPU
 
-config CPU_CORTEX_A510
-	bool
-	select CPU_CORTEX_A
-	select ARMV9_A
-	help
-	  This option signifies the use of a Cortex-A510 CPU, which is Arm's
-	  efficiency core implementing the ARMv9-A architecture. It provides
-	  power-efficient processing optimized for embedded applications with
-	  ARMv9-A features.
-
-config CPU_CORTEX_A320
-	bool
-	select CPU_CORTEX_A
-	select ARMV9_A
-	help
-	  This option signifies the use of a Cortex-A320 CPU, which implements
-	  the ARMv9.2-A architecture. It provides advanced features including
-	  enhanced SVE2, improved security extensions, and specialized performance
-	  optimizations.
-
 config CPU_CORTEX_R82
 	bool
 	select CPU_AARCH64_CORTEX_R
@@ -121,15 +101,10 @@ config MAIN_STACK_SIZE
 config IDLE_STACK_SIZE
 	default 4096
 
-config PRIVILEGED_STACK_SIZE
-	default 4096 if FPU_SHARING
-	default 2048
-
 config ISR_STACK_SIZE
 	default 4096
 
 config TEST_EXTRA_STACK_SIZE
-	default 4096 if FPU_SHARING
 	default 2048
 
 config SYSTEM_WORKQUEUE_STACK_SIZE
@@ -183,6 +158,14 @@ config ARM64_EXCEPTION_STACK_TRACE
 	help
 	  Internal config to enable runtime stack traces on fatal exceptions.
 
+config ARCH_HAS_STACKWALK
+	bool
+	default y
+	depends on FRAME_POINTER
+	help
+	  Internal config to indicate that the arch_stack_walk() API is implemented
+	  and it can be enabled.
+
 config ARM64_SAFE_EXCEPTION_STACK_SIZE
 	int "The stack size of the safe exception stack"
 	default 4096
@@ -213,14 +196,6 @@ config ARM64_STACK_PROTECTION
 
 if CPU_CORTEX_A
 
-config ARCH_HAS_STACKWALK
-	bool
-	default y
-	depends on FRAME_POINTER
-	help
-	  Internal config to indicate that the arch_stack_walk() API is implemented
-	  and it can be enabled.
-
 config ARMV8_A_NS
 	bool "ARMv8-A Normal World (Non-Secure world of Trustzone)"
 	help
@@ -248,20 +223,6 @@ config ARMV8_A
 	  so that it can support some features included in the AArch64 state.
 	  It supports the T32 and A32 instruction sets.
 
-config ARMV9_A
-	bool
-	select ATOMIC_OPERATIONS_BUILTIN
-	select CPU_HAS_MMU
-	select ARCH_HAS_USERSPACE if ARM_MMU
-	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MMU
-	imply ARM64_SVE if FPU_SHARING
-	help
-	  This option signifies the use of an ARMv9-A processor
-	  implementation.
-	  ARMv9-A builds on ARMv8-A and introduces additional security,
-	  performance, and machine learning capabilities while maintaining
-	  backward compatibility with ARMv8-A software.
-
 rsource "xen/Kconfig"
 
 endif # CPU_CORTEX_A
@@ -387,8 +348,6 @@ config ARM64_PA_BITS
 
 config MAX_XLAT_TABLES
 	int "Maximum numbers of translation tables"
-	default 32 if USERSPACE && TEST && SMP
-	default 24 if USERSPACE && TEST
 	default 20 if USERSPACE && (ARM64_VA_BITS >= 40)
 	default 16 if USERSPACE
 	default 12 if (ARM64_VA_BITS >= 40)
@@ -421,27 +380,4 @@ config ARM64_BOOT_DISABLE_DCACHE
 	  cache and then disable data cache, it will will be re-enabled after
 	  MMU is configured and enabled.
 
-config ARM64_SVE
-	bool "Scalable Vector Extension (SVE) support"
-	depends on ARMV9_A
-	help
-	  Enable support for ARM64 Scalable Vector Extension (SVE).
-	  This allows threads to use SVE/SVE2 instructions and automatically
-	  handles context switching of SVE registers (Z0-Z31, P0-P15, FFR)
-	  if CONFIG_FPU_SHARING is also set. Requires ARMv9-A architecture.
-
-config ARM64_SVE_VL_MAX
-	int "Maximum SVE vector length in bytes"
-	depends on ARM64_SVE
-	default 16
-	range 16 256
-	help
-	  Maximum supported SVE vector length in bytes. This determines
-	  the SVE context size within each thread structure. Valid values
-	  are any power of two from 16 to 256 inclusive (128 to 2048 bits).
-	  This can be smaller than the hardware supported vector length to
-	  save some per-thread memory in which case the hardware will be
-	  limited to the specified length. Having a larger value than what
-	  the hardware supports will only waste memory.
-
 endif # CPU_CORTEX_A || CPU_AARCH64_CORTEX_R

arch/arm64/core/fatal.c

@@ -337,7 +337,7 @@ static bool z_arm64_stack_corruption_check(struct arch_esf *esf, uint64_t esr, u
 			 * a new nested exception triggered by FPU accessing (var_args).
 			 */
 			arch_flush_local_fpu();
-			write_cpacr_el1(read_cpacr_el1() | CPACR_EL1_FPEN);
+			write_cpacr_el1(read_cpacr_el1() | CPACR_EL1_FPEN_NOTRAP);
 #endif
 			arch_curr_cpu()->arch.corrupted_sp = 0UL;
 			EXCEPTION_DUMP("STACK OVERFLOW FROM KERNEL,"

arch/arm64/core/fpu.S

@@ -7,20 +7,12 @@
 
 #include <zephyr/toolchain.h>
 #include <zephyr/linker/sections.h>
-#include <zephyr/offsets.h>
 
 _ASM_FILE_PROLOGUE
 
 GTEXT(z_arm64_fpu_save)
 SECTION_FUNC(TEXT, z_arm64_fpu_save)
 
-	mrs	x1, fpsr
-	mrs	x2, fpcr
-	str	w1, [x0, #__z_arm64_fp_context_fpsr_OFFSET]
-	str	w2, [x0, #__z_arm64_fp_context_fpcr_OFFSET]
-
-	/* Save NEON registers */
-	add	x0, x0, #__z_arm64_fp_context_neon_OFFSET
 	stp	q0,  q1,  [x0, #(16 *  0)]
 	stp	q2,  q3,  [x0, #(16 *  2)]
 	stp	q4,  q5,  [x0, #(16 *  4)]
@@ -38,18 +30,16 @@ SECTION_FUNC(TEXT, z_arm64_fpu_save)
 	stp	q28, q29, [x0, #(16 * 28)]
 	stp	q30, q31, [x0, #(16 * 30)]
 
+	mrs	x1, fpsr
+	mrs	x2, fpcr
+	str	w1, [x0, #(16 * 32 + 0)]
+	str	w2, [x0, #(16 * 32 + 4)]
+
 	ret
 
 GTEXT(z_arm64_fpu_restore)
 SECTION_FUNC(TEXT, z_arm64_fpu_restore)
 
-	ldr	w1, [x0, #__z_arm64_fp_context_fpsr_OFFSET]
-	ldr	w2, [x0, #__z_arm64_fp_context_fpcr_OFFSET]
-	msr	fpsr, x1
-	msr	fpcr, x2
-
-	/* Restore NEON registers */
-	add	x0, x0, #__z_arm64_fp_context_neon_OFFSET
 	ldp	q0,  q1,  [x0, #(16 *  0)]
 	ldp	q2,  q3,  [x0, #(16 *  2)]
 	ldp	q4,  q5,  [x0, #(16 *  4)]
@@ -67,164 +57,9 @@ SECTION_FUNC(TEXT, z_arm64_fpu_restore)
 	ldp	q28, q29, [x0, #(16 * 28)]
 	ldp	q30, q31, [x0, #(16 * 30)]
 
-	ret
-
-#ifdef CONFIG_ARM64_SVE
-
-GTEXT(z_arm64_sve_save)
-SECTION_FUNC(TEXT, z_arm64_sve_save)
-
-	/* Save control registers */
-	mrs	x2, fpsr
-	mrs	x3, fpcr
-	str	w2, [x0, #__z_arm64_fp_context_fpsr_OFFSET]
-	str	w3, [x0, #__z_arm64_fp_context_fpcr_OFFSET]
-
-	/* Get Z registers base address */
-	add	x2, x0, #__z_arm64_fp_context_sve_z_regs_OFFSET
-
-	/* Save Z registers */
-	str	z0, [x2, #0, MUL VL]
-	str	z1, [x2, #1, MUL VL]
-	str	z2, [x2, #2, MUL VL]
-	str	z3, [x2, #3, MUL VL]
-	str	z4, [x2, #4, MUL VL]
-	str	z5, [x2, #5, MUL VL]
-	str	z6, [x2, #6, MUL VL]
-	str	z7, [x2, #7, MUL VL]
-	str	z8, [x2, #8, MUL VL]
-	str	z9, [x2, #9, MUL VL]
-	str	z10, [x2, #10, MUL VL]
-	str	z11, [x2, #11, MUL VL]
-	str	z12, [x2, #12, MUL VL]
-	str	z13, [x2, #13, MUL VL]
-	str	z14, [x2, #14, MUL VL]
-	str	z15, [x2, #15, MUL VL]
-	str	z16, [x2, #16, MUL VL]
-	str	z17, [x2, #17, MUL VL]
-	str	z18, [x2, #18, MUL VL]
-	str	z19, [x2, #19, MUL VL]
-	str	z20, [x2, #20, MUL VL]
-	str	z21, [x2, #21, MUL VL]
-	str	z22, [x2, #22, MUL VL]
-	str	z23, [x2, #23, MUL VL]
-	str	z24, [x2, #24, MUL VL]
-	str	z25, [x2, #25, MUL VL]
-	str	z26, [x2, #26, MUL VL]
-	str	z27, [x2, #27, MUL VL]
-	str	z28, [x2, #28, MUL VL]
-	str	z29, [x2, #29, MUL VL]
-	str	z30, [x2, #30, MUL VL]
-	str	z31, [x2, #31, MUL VL]
-
-	/* Get P registers base address */
-	mov	x3, #__z_arm64_fp_context_sve_p_regs_OFFSET
-	add	x3, x0, x3
-
-	/* Save P registers */
-	str	p0, [x3, #0, MUL VL]
-	str	p1, [x3, #1, MUL VL]
-	str	p2, [x3, #2, MUL VL]
-	str	p3, [x3, #3, MUL VL]
-	str	p4, [x3, #4, MUL VL]
-	str	p5, [x3, #5, MUL VL]
-	str	p6, [x3, #6, MUL VL]
-	str	p7, [x3, #7, MUL VL]
-	str	p8, [x3, #8, MUL VL]
-	str	p9, [x3, #9, MUL VL]
-	str	p10, [x3, #10, MUL VL]
-	str	p11, [x3, #11, MUL VL]
-	str	p12, [x3, #12, MUL VL]
-	str	p13, [x3, #13, MUL VL]
-	str	p14, [x3, #14, MUL VL]
-	str	p15, [x3, #15, MUL VL]
-
-	/* Get FFR base address */
-	mov	x4, #__z_arm64_fp_context_sve_ffr_OFFSET
-	add	x4, x0, x4
-
-	/* Save FFR */
-	rdffr	p0.b
-	str	p0, [x4]
+	ldr	w1, [x0, #(16 * 32 + 0)]
+	ldr	w2, [x0, #(16 * 32 + 4)]
+	msr	fpsr, x1
+	msr	fpcr, x2
 
 	ret
-
-GTEXT(z_arm64_sve_restore)
-SECTION_FUNC(TEXT, z_arm64_sve_restore)
-
-	/* Get Z registers base address */
-	add	x2, x0, #__z_arm64_fp_context_sve_z_regs_OFFSET
-
-	/* Restore Z registers */
-	ldr	z0, [x2, #0, MUL VL]
-	ldr	z1, [x2, #1, MUL VL]
-	ldr	z2, [x2, #2, MUL VL]
-	ldr	z3, [x2, #3, MUL VL]
-	ldr	z4, [x2, #4, MUL VL]
-	ldr	z5, [x2, #5, MUL VL]
-	ldr	z6, [x2, #6, MUL VL]
-	ldr	z7, [x2, #7, MUL VL]
-	ldr	z8, [x2, #8, MUL VL]
-	ldr	z9, [x2, #9, MUL VL]
-	ldr	z10, [x2, #10, MUL VL]
-	ldr	z11, [x2, #11, MUL VL]
-	ldr	z12, [x2, #12, MUL VL]
-	ldr	z13, [x2, #13, MUL VL]
-	ldr	z14, [x2, #14, MUL VL]
-	ldr	z15, [x2, #15, MUL VL]
-	ldr	z16, [x2, #16, MUL VL]
-	ldr	z17, [x2, #17, MUL VL]
-	ldr	z18, [x2, #18, MUL VL]
-	ldr	z19, [x2, #19, MUL VL]
-	ldr	z20, [x2, #20, MUL VL]
-	ldr	z21, [x2, #21, MUL VL]
-	ldr	z22, [x2, #22, MUL VL]
-	ldr	z23, [x2, #23, MUL VL]
-	ldr	z24, [x2, #24, MUL VL]
-	ldr	z25, [x2, #25, MUL VL]
-	ldr	z26, [x2, #26, MUL VL]
-	ldr	z27, [x2, #27, MUL VL]
-	ldr	z28, [x2, #28, MUL VL]
-	ldr	z29, [x2, #29, MUL VL]
-	ldr	z30, [x2, #30, MUL VL]
-	ldr	z31, [x2, #31, MUL VL]
-
-	/* Get FFR base address */
-	mov	x4, #__z_arm64_fp_context_sve_ffr_OFFSET
-	add	x4, x0, x4
-
-	/* Restore FFR */
-	ldr	p0, [x4]
-	wrffr	p0.b
-
-	/* Get P registers base address */
-	mov	x3, #__z_arm64_fp_context_sve_p_regs_OFFSET
-	add	x3, x0, x3
-
-	/* Restore P registers intervals */
-	ldr	p0, [x3, #0, MUL VL]
-	ldr	p1, [x3, #1, MUL VL]
-	ldr	p2, [x3, #2, MUL VL]
-	ldr	p3, [x3, #3, MUL VL]
-	ldr	p4, [x3, #4, MUL VL]
-	ldr	p5, [x3, #5, MUL VL]
-	ldr	p6, [x3, #6, MUL VL]
-	ldr	p7, [x3, #7, MUL VL]
-	ldr	p8, [x3, #8, MUL VL]
-	ldr	p9, [x3, #9, MUL VL]
-	ldr	p10, [x3, #10, MUL VL]
-	ldr	p11, [x3, #11, MUL VL]
-	ldr	p12, [x3, #12, MUL VL]
-	ldr	p13, [x3, #13, MUL VL]
-	ldr	p14, [x3, #14, MUL VL]
-	ldr	p15, [x3, #15, MUL VL]
-
-	/* Restore control registers */
-	ldr	w2, [x0, #__z_arm64_fp_context_fpsr_OFFSET]
-	ldr	w3, [x0, #__z_arm64_fp_context_fpcr_OFFSET]
-	msr	fpsr, x2
-	msr	fpcr, x3
-
-	ret
-
-#endif /* CONFIG_ARM64_SVE */

arch/arm64/core/fpu.c

@@ -15,8 +15,6 @@
 /* to be found in fpu.S */
 extern void z_arm64_fpu_save(struct z_arm64_fp_context *saved_fp_context);
 extern void z_arm64_fpu_restore(struct z_arm64_fp_context *saved_fp_context);
-extern void z_arm64_sve_save(struct z_arm64_fp_context *saved_fp_context);
-extern void z_arm64_sve_restore(struct z_arm64_fp_context *saved_fp_context);
 
 #define FPU_DEBUG 0
 
@@ -55,7 +53,7 @@ static void DBG(char *msg, struct k_thread *th)
 	if (th == NULL) {
 		th = _current;
 	}
-	v = *(unsigned char *)&th->arch.saved_fp_context.neon;
+	v = *(unsigned char *)&th->arch.saved_fp_context;
 	*p++ = ' ';
 	*p++ = ((v >> 4) < 10) ? ((v >> 4) + '0') : ((v >> 4) - 10 + 'a');
 	*p++ = ((v & 15) < 10) ? ((v & 15) + '0') : ((v & 15) - 10 + 'a');
@@ -93,46 +91,6 @@ static inline void DBG_PC(char *msg, uintptr_t pc) { }
 
 #endif /* FPU_DEBUG */
 
-#ifdef CONFIG_ARM64_SVE
-
-/* Get current SVE vector length */
-static inline uint32_t z_arm64_sve_get_vl(void)
-{
-	uint32_t vl;
-
-	__asm__("rdvl %0, #1" : "=r"(vl));
-	return vl;
-}
-
-#define USE_SVE(t) ((t) && (t)->arch.saved_fp_context.sve.simd_mode == SIMD_SVE)
-
-/* Convert NEON V registers to SVE Z registers in place */
-static void convert_Vx_to_Zx(struct z_arm64_fp_context *context)
-{
-	uint32_t vl = z_arm64_sve_get_vl();
-
-	if (CONFIG_ARM64_SVE_VL_MAX <= 16 || vl <= 16) {
-		return;
-	}
-
-	/*
-	 * Since it's a union, we need to extend each 128-bit NEON register
-	 * to the full SVE vector length, working backwards to avoid overwriting
-	 * data we still need to copy.
-	 */
-	for (int i = 31; i >= 0; i--) {
-		/* Copy the 128-bit NEON value to the low 128 bits of the Z register */
-		*(__int128 *)&context->sve.z_regs[i * vl] = context->neon.v_regs[i];
-
-		/* Zero the upper part of the Z register (beyond 128 bits) */
-		memset(&context->sve.z_regs[i * vl + 16], 0, vl - 16);
-	}
-}
-
-#else
-#define USE_SVE(t) false
-#endif
-
 /*
  * Flush FPU content and disable access.
  * This is called locally and also from flush_fpu_ipi_handler().
@@ -147,30 +105,19 @@ void arch_flush_local_fpu(void)
 		uint64_t cpacr = read_cpacr_el1();
 
 		/* turn on FPU access */
-		cpacr |= CPACR_EL1_FPEN;
-		if (USE_SVE(owner)) {
-			cpacr |= CPACR_EL1_ZEN;
-		}
-		write_cpacr_el1(cpacr);
+		write_cpacr_el1(cpacr | CPACR_EL1_FPEN_NOTRAP);
 		barrier_isync_fence_full();
 
 		/* save current owner's content */
-		if (USE_SVE(owner)) {
-			z_arm64_sve_save(&owner->arch.saved_fp_context);
-		} else {
-			z_arm64_fpu_save(&owner->arch.saved_fp_context);
-		}
-
+		z_arm64_fpu_save(&owner->arch.saved_fp_context);
 		/* make sure content made it to memory before releasing */
 		barrier_dsync_fence_full();
-
 		/* release ownership */
 		atomic_ptr_clear(&_current_cpu->arch.fpu_owner);
 		DBG("disable", owner);
 
 		/* disable FPU access */
-		cpacr &= ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN);
-		write_cpacr_el1(cpacr);
+		write_cpacr_el1(cpacr & ~CPACR_EL1_FPEN_NOTRAP);
 		barrier_isync_fence_full();
 	}
 }
@@ -226,7 +173,7 @@ void z_arm64_fpu_enter_exc(void)
 	__ASSERT(read_daif() & DAIF_IRQ_BIT, "must be called with IRQs disabled");
 
 	/* always deny FPU access whenever an exception is entered */
-	write_cpacr_el1(read_cpacr_el1() & ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN));
+	write_cpacr_el1(read_cpacr_el1() & ~CPACR_EL1_FPEN_NOTRAP);
 	barrier_isync_fence_full();
 }
 
@@ -306,48 +253,29 @@ static bool simulate_str_q_insn(struct arch_esf *esf)
  * don't get interrupted that is. To ensure that we mask interrupts to
  * the triggering exception context.
  */
-void z_arm64_fpu_trap(struct arch_esf *esf, uint32_t exception_class)
+void z_arm64_fpu_trap(struct arch_esf *esf)
 {
 	__ASSERT(read_daif() & DAIF_IRQ_BIT, "must be called with IRQs disabled");
 
 	/* check if a quick simulation can do it */
-	if (!(IS_ENABLED(CONFIG_ARM64_SVE) && exception_class == 0x19) &&
-	    simulate_str_q_insn(esf)) {
+	if (simulate_str_q_insn(esf)) {
 		return;
 	}
 
 	DBG_PC("trap entry", esf->elr);
 
-	struct k_thread *owner = atomic_ptr_get(&_current_cpu->arch.fpu_owner);
-	uint64_t cpacr = read_cpacr_el1();
-
 	/* turn on FPU access */
-	cpacr |= CPACR_EL1_FPEN;
-	if (USE_SVE(owner)) {
-		cpacr |= CPACR_EL1_ZEN;
-	}
-	write_cpacr_el1(cpacr);
+	write_cpacr_el1(read_cpacr_el1() | CPACR_EL1_FPEN_NOTRAP);
 	barrier_isync_fence_full();
 
 	/* save current owner's content  if any */
+	struct k_thread *owner = atomic_ptr_get(&_current_cpu->arch.fpu_owner);
+
 	if (owner) {
-		if (USE_SVE(owner)) {
-			z_arm64_sve_save(&owner->arch.saved_fp_context);
-			DBG("sve_save", owner);
-		} else {
-			z_arm64_fpu_save(&owner->arch.saved_fp_context);
-			DBG("fpu_save", owner);
-		}
+		z_arm64_fpu_save(&owner->arch.saved_fp_context);
 		barrier_dsync_fence_full();
 		atomic_ptr_clear(&_current_cpu->arch.fpu_owner);
-	}
-
-	if (IS_ENABLED(CONFIG_ARM64_SVE) && exception_class == 0x19 &&
-	    !(cpacr & CPACR_EL1_ZEN)) {
-		/* SVE trap - also enable SVE access */
-		cpacr |= CPACR_EL1_ZEN;
-		write_cpacr_el1(cpacr);
-		barrier_isync_fence_full();
+		DBG("save", owner);
 	}
 
 	if (arch_exception_depth() > 1) {
@@ -372,45 +300,9 @@ void z_arm64_fpu_trap(struct arch_esf *esf, uint32_t exception_class)
 	/* become new owner */
 	atomic_ptr_set(&_current_cpu->arch.fpu_owner, _current);
 
-#ifdef CONFIG_ARM64_SVE
-	if (exception_class == 0x19) {
-		/* SVE trap */
-		if (_current->arch.saved_fp_context.sve.simd_mode == SIMD_NEON) {
-			/* upgrade from Neon to SVE before loading regs */
-			convert_Vx_to_Zx(&_current->arch.saved_fp_context);
-		}
-		_current->arch.saved_fp_context.sve.simd_mode = SIMD_SVE;
-	} else if (_current->arch.saved_fp_context.sve.simd_mode != SIMD_SVE) {
-		/* not SVE trap and context is not SVE either */
-		if ((cpacr & CPACR_EL1_ZEN) != 0) {
-			/* disable SVE access leaving only FP */
-			cpacr &= ~CPACR_EL1_ZEN;
-			write_cpacr_el1(cpacr);
-			barrier_isync_fence_full();
-		}
-		_current->arch.saved_fp_context.sve.simd_mode = SIMD_NEON;
-	} else if ((cpacr & CPACR_EL1_ZEN) == 0) {
-		/*
-		 * Not SVE trap but context is SVE and CPACR_EL1_ZEN not set.
-		 * This is an edge case that happens when previous owner
-		 * didn't use SVE and we are not using SVE right now either
-		 * although we did in the past. We're about to restore an
-		 * SVE context so make sure SVE access is enabled.
-		 */
-		cpacr |= CPACR_EL1_ZEN;
-		write_cpacr_el1(cpacr);
-		barrier_isync_fence_full();
-	}
-#endif
-
 	/* restore our content */
-	if (USE_SVE(_current)) {
-		z_arm64_sve_restore(&_current->arch.saved_fp_context);
-		DBG("sve_restore", NULL);
-	} else {
-		z_arm64_fpu_restore(&_current->arch.saved_fp_context);
-		DBG("fpu_restore", NULL);
-	}
+	z_arm64_fpu_restore(&_current->arch.saved_fp_context);
+	DBG("restore", NULL);
 }
 
 /*
@@ -431,14 +323,10 @@ static void fpu_access_update(unsigned int exc_update_level)
 		/* We're about to execute non-exception code */
 		if (atomic_ptr_get(&_current_cpu->arch.fpu_owner) == _current) {
 			/* turn on FPU access */
-			cpacr |= CPACR_EL1_FPEN;
-			if (USE_SVE(_current)) {
-				cpacr |= CPACR_EL1_ZEN;
-			}
-			write_cpacr_el1(cpacr);
+			write_cpacr_el1(cpacr | CPACR_EL1_FPEN_NOTRAP);
 		} else {
 			/* deny FPU access */
-			write_cpacr_el1(cpacr & ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN));
+			write_cpacr_el1(cpacr & ~CPACR_EL1_FPEN_NOTRAP);
 		}
 	} else {
 		/*
@@ -446,7 +334,7 @@ static void fpu_access_update(unsigned int exc_update_level)
 		 * access as we want to make sure IRQs are disabled before
 		 * granting it access (see z_arm64_fpu_trap() documentation).
 		 */
-		write_cpacr_el1(cpacr & ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN));
+		write_cpacr_el1(cpacr & ~CPACR_EL1_FPEN_NOTRAP);
 	}
 	barrier_isync_fence_full();
 }

arch/arm64/core/mmu.c

@@ -54,15 +54,7 @@ static uint64_t *new_table(void)
 		}
 	}
 
-#if defined(CONFIG_LOG)
-	LOG_ERR("CONFIG_MAX_XLAT_TABLES is too small");
-#else
-	printk("ERROR: CONFIG_MAX_XLAT_TABLES is too small\n");
-#endif
-
-	/* Unfortunately many code paths are not ready for failure */
-	k_panic();
-
+	LOG_ERR("CONFIG_MAX_XLAT_TABLES, too small");
 	return NULL;
 }
 

arch/arm64/core/offsets/offsets.c

@@ -29,7 +29,6 @@
 #include <zephyr/kernel.h>
 #include <kernel_arch_data.h>
 #include <kernel_offsets.h>
-#include <zephyr/arch/arm64/thread.h>
 
 GEN_OFFSET_SYM(_thread_arch_t, exception_depth);
 
@@ -78,20 +77,6 @@ GEN_NAMED_OFFSET_SYM(arm_smccc_res_t, a6, a6_a7);
 
 #endif /* CONFIG_HAS_ARM_SMCCC */
 
-#ifdef CONFIG_FPU_SHARING
-GEN_OFFSET_SYM(z_arm64_fp_context, fpsr);
-GEN_OFFSET_SYM(z_arm64_fp_context, fpcr);
-GEN_OFFSET_SYM(z_arm64_fp_context, neon);
-#ifdef CONFIG_ARM64_SVE
-GEN_ABSOLUTE_SYM(__z_arm64_fp_context_sve_z_regs_OFFSET,
-	offsetof(struct z_arm64_fp_context, sve.z_regs));
-GEN_ABSOLUTE_SYM(__z_arm64_fp_context_sve_p_regs_OFFSET,
-	offsetof(struct z_arm64_fp_context, sve.p_regs));
-GEN_ABSOLUTE_SYM(__z_arm64_fp_context_sve_ffr_OFFSET,
-	offsetof(struct z_arm64_fp_context, sve.ffr));
-#endif
-#endif
-
 GEN_ABS_SYM_END
 
 #endif /* _ARM_OFFSETS_INC_ */

arch/arm64/core/reset.c

@@ -78,22 +78,7 @@ void z_arm64_el3_init(void)
 	reg &= ~(CPTR_TTA_BIT |		/* Do not trap sysreg accesses */
 		 CPTR_TFP_BIT |		/* Do not trap SVE, SIMD and FP */
 		 CPTR_TCPAC_BIT);	/* Do not trap CPTR_EL2 / CPACR_EL1 accesses */
-
-#ifdef CONFIG_ARM64_SVE
-	/* Enable SVE for EL2 and below if SVE is implemented */
-	if (is_sve_implemented()) {
-		reg |= CPTR_EZ_BIT;		/* Enable SVE access for lower ELs */
-		write_cptr_el3(reg);
-
-		/* Initialize ZCR_EL3 for full SVE vector length */
-		/* ZCR_EL3.LEN = 0x1ff means full hardware vector length */
-		write_zcr_el3(0x1ff);
-	} else {
-		write_cptr_el3(reg);
-	}
-#else
 	write_cptr_el3(reg);
-#endif
 
 	reg = 0U;			/* Reset */
 #ifdef CONFIG_ARMV8_A_NS
@@ -171,24 +156,8 @@ void z_arm64_el2_init(void)
 	reg = 0U;			/* RES0 */
 	reg |= CPTR_EL2_RES1;		/* RES1 */
 	reg &= ~(CPTR_TFP_BIT |		/* Do not trap SVE, SIMD and FP */
-		 CPTR_TCPAC_BIT |	/* Do not trap CPACR_EL1 accesses */
-		 CPTR_EL2_TZ_BIT);	/* Do not trap SVE to EL2 */
-#ifdef CONFIG_ARM64_SVE
-	/* Enable SVE for EL1 and EL0 if SVE is implemented */
-	if (is_sve_implemented()) {
-		reg &= ~CPTR_EL2_ZEN_MASK;
-		reg |= (CPTR_EL2_ZEN_EL1_EN | CPTR_EL2_ZEN_EL0_EN);
-		write_cptr_el2(reg);
-
-		/* Initialize ZCR_EL2 for full SVE vector length */
-		/* ZCR_EL2.LEN = 0x1ff means full hardware vector length */
-		write_zcr_el2(0x1ff);
-	} else {
-		write_cptr_el2(reg);
-	}
-#else
+		 CPTR_TCPAC_BIT);	/* Do not trap CPACR_EL1 accesses */
 	write_cptr_el2(reg);
-#endif
 
 	zero_cntvoff_el2();		/* Set 64-bit virtual timer offset to 0 */
 	zero_cnthctl_el2();
@@ -222,22 +191,9 @@ void z_arm64_el1_init(void)
 	barrier_isync_fence_full();
 
 	reg = 0U;			/* RES0 */
-	reg |= CPACR_EL1_FPEN;		/* Do not trap NEON/SIMD/FP initially */
+	reg |= CPACR_EL1_FPEN_NOTRAP;	/* Do not trap NEON/SIMD/FP initially */
 					/* TODO: CONFIG_FLOAT_*_FORBIDDEN */
-#ifdef CONFIG_ARM64_SVE
-	/* Enable SVE access if SVE is implemented */
-	if (is_sve_implemented()) {
-		reg |= CPACR_EL1_ZEN;	/* Do not trap SVE initially */
-		write_cpacr_el1(reg);
-
-		/* Initialize ZCR_EL1 SVE vector length */
-		write_zcr_el1(CONFIG_ARM64_SVE_VL_MAX/16 - 1);
-	} else {
-		write_cpacr_el1(reg);
-	}
-#else
 	write_cpacr_el1(reg);
-#endif
 
 	reg = read_sctlr_el1();
 	reg |= (SCTLR_EL1_RES1 |	/* RES1 */

arch/arm64/core/switch.S

@@ -153,15 +153,8 @@ SECTION_FUNC(TEXT, z_arm64_sync_exc)
 
 #ifdef CONFIG_FPU_SHARING
 	cmp	x1, #0x07 /*Access to SIMD or floating-point */
-	beq	fpu_sve_trap
-#ifdef CONFIG_ARM64_SVE
-	cmp	x1, #0x19 /*Trapped access to SVE functionality */
-	beq	fpu_sve_trap
-#endif
-	b	1f
-fpu_sve_trap:
-	mov	x0, sp  /* ESF pointer */
-	/* x1 already contains exception class (EC) - pass as second argument */
+	bne	1f
+	mov	x0, sp
 	bl	z_arm64_fpu_trap
 	b	z_arm64_exit_exc_fpu_done
 1:

arch/arm64/core/xen/Kconfig

@@ -33,25 +33,3 @@ config XEN_INTERFACE_VERSION
 	help
 	  Xen interface version to use. This is the version of the
 	  interface that Zephyr will use to communicate with the hypervisor.
-
-config XEN_DOMCTL_INTERFACE_VERSION
-	hex "Xen Domctl interface version"
-	default 0x17
-	range 0x15 0x17
-	depends on XEN
-	help
-	  Xen Domctl interface version to use. This is the version of the
-	  domctl interface that Zephyr will use to communicate with
-	  the hypervisor. The default value is the latest version supported
-	  by the kernel.
-
-config XEN_SYSCTL_INTERFACE_VERSION
-	hex "Xen Sysctl interface version"
-	default 0x15
-	range 0x15 0x15
-	depends on XEN
-	help
-	  Xen Sysctl interface version to use. This is the version of the
-	  domctl interface that Zephyr will use to communicate with
-	  the hypervisor. The default value is the latest version supported
-	  by the kernel.

arch/arm64/core/xen/hypercall.S

@@ -23,10 +23,7 @@ HYPERCALL(sched_op);
 HYPERCALL(event_channel_op);
 HYPERCALL(hvm_op);
 HYPERCALL(memory_op);
-HYPERCALL(dm_op);
-HYPERCALL(xen_version);
 
 #ifdef CONFIG_XEN_DOM0
 HYPERCALL(domctl);
-HYPERCALL(sysctl);
 #endif

arch/common/init.c

@@ -55,6 +55,11 @@ void arch_bss_zero(void)
 	}
 
 	arch_early_memset(__bss_start, 0, __bss_end - __bss_start);
+#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm))
+	arch_early_memset(&__ccm_bss_start, 0,
+		       (uintptr_t) &__ccm_bss_end
+		       - (uintptr_t) &__ccm_bss_start);
+#endif
 #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm))
 	arch_early_memset(&__dtcm_bss_start, 0,
 		       (uintptr_t) &__dtcm_bss_end

arch/common/xip.c

@@ -38,6 +38,10 @@ void arch_data_copy(void)
 		       (uintptr_t) &_nocache_load_ram_size);
 #endif /* CONFIG_NOCACHE_MEMORY */
 #endif /* CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT */
+#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm))
+	arch_early_memcpy(&__ccm_data_start, &__ccm_data_load_start,
+		       __ccm_data_end - __ccm_data_start);
+#endif
 #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm))
 	arch_early_memcpy(&__itcm_start, &__itcm_load_start,
 		       (uintptr_t) &__itcm_size);

arch/mips/CMakeLists.txt

@@ -7,9 +7,9 @@
 #
 
 if(CONFIG_BIG_ENDIAN)
-  set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-bigmips")
+	set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-bigmips")
 else()
-  set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-littlemips")
+	set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-littlemips")
 endif()
 
 add_subdirectory(core)

arch/posix/CMakeLists.txt

@@ -39,27 +39,32 @@ set_property(TARGET native_simulator PROPERTY LOCALIZE_EXTRA_OPTIONS "")
 
 set(NSI_DIR ${ZEPHYR_BASE}/scripts/native_simulator CACHE PATH "Path to the native simulator")
 
-if(NATIVE_TARGET_HOST) # Allow users to manually select the target for cross-compiling use cases
-  set(TARGET_HOST ${NATIVE_TARGET_HOST})
-else()
-  if("${CMAKE_HOST_SYSTEM_PROCESSOR}" MATCHES "arm.*")
-    # All 32bit arm variants
-    set(TARGET_HOST "arm")
-  elseif("${CMAKE_HOST_SYSTEM_PROCESSOR}" MATCHES ".*86.*")
-    # x86_64/i*86
-    set(TARGET_HOST "x86_64")
-  else()
-    set(TARGET_HOST ${CMAKE_HOST_SYSTEM_PROCESSOR})
-  endif()
-endif()
+if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/${CMAKE_HOST_SYSTEM_NAME}.${CMAKE_HOST_SYSTEM_PROCESSOR}.cmake)
+  # @Intent: Set necessary compiler & linker options for this specific host architecture & OS
+  include(${CMAKE_HOST_SYSTEM_NAME}.${CMAKE_HOST_SYSTEM_PROCESSOR}.cmake)
+else() # Linux.x86_64
+  if(CONFIG_64BIT)
+    # some gcc versions fail to build without -fPIC
+    zephyr_compile_options(-m64 -fPIC)
+    zephyr_link_libraries(-m64)
 
-if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/${TARGET_HOST}.cmake)
-  # Set necessary compiler & linker options for this specific host architecture
-  include(${TARGET_HOST}.cmake)
-elseif(DEFINED NATIVE_TARGET_HOST)
-  message(WARNING "NATIVE_TARGET_HOST set to ${NATIVE_TARGET_HOST}, but ${CMAKE_CURRENT_LIST_DIR}/"
-          "${TARGET_HOST}.cmake not found. No custom target options will be applied."
-  )
+    target_link_options(native_simulator INTERFACE "-m64")
+    target_compile_options(native_simulator INTERFACE "-m64")
+  else()
+    zephyr_compile_options(-m32)
+    zephyr_link_libraries(-m32)
+
+    target_link_options(native_simulator INTERFACE "-m32")
+    target_compile_options(native_simulator INTERFACE "-m32")
+
+    # When building for 32bits x86, gcc defaults to using the old 8087 float arithmetic
+    # which causes some issues with literal float comparisons. So we set it
+    # to use the SSE2 float path instead
+    # (clang defaults to use SSE, but, setting this option for it is safe)
+    check_set_compiler_property(APPEND PROPERTY fpsse2 "SHELL:-msse2 -mfpmath=sse")
+    zephyr_compile_options($<TARGET_PROPERTY:compiler,fpsse2>)
+    target_compile_options(native_simulator INTERFACE "$<TARGET_PROPERTY:compiler,fpsse2>")
+  endif()
 endif()
 
 zephyr_compile_options(

arch/posix/Linux.aarch64.cmake

@@ -4,7 +4,7 @@
 # distributions. Userspace is (generally) either 32-bit or 64-bit but not
 # both.
 
-# Get userspace wordsize for comparison with CONFIG_64BIT
+# @Intent: Call a script to get userspace wordsize for comparison with CONFIG_64BIT
 execute_process(
   COMMAND
   ${PYTHON_EXECUTABLE}

arch/posix/arm.cmake

@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-if(CONFIG_64BIT)
-  message(FATAL_ERROR
-    "CONFIG_64BIT=y while targeting a 32-bit ARM processor.\n"
-    "If you were targeting native_sim/native/64, target native_sim instead.\n"
-    "Otherwise, be sure to define CONFIG_64BIT appropriately.\n"
-  )
-endif()

arch/posix/core/CMakeLists.txt

@@ -3,17 +3,17 @@
 zephyr_library()
 zephyr_library_compile_definitions(NO_POSIX_CHEATS)
 zephyr_library_sources(
-  cpuhalt.c
-  fatal.c
-  irq.c
-  swap.c
-  thread.c
-)
+	cpuhalt.c
+	fatal.c
+	irq.c
+	swap.c
+	thread.c
+	)
 
 if(CONFIG_ARCH_POSIX_TRAP_ON_FATAL)
   target_sources(native_simulator INTERFACE fatal_trap.c)
 endif()
 
 zephyr_library_sources(
-  posix_core_nsi.c
+	posix_core_nsi.c
 )

arch/posix/x86_64.cmake

@@ -1,24 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-if(CONFIG_64BIT)
-  # some gcc versions fail to build without -fPIC
-  zephyr_compile_options(-m64 -fPIC)
-  zephyr_link_libraries(-m64)
-
-  target_link_options(native_simulator INTERFACE "-m64")
-  target_compile_options(native_simulator INTERFACE "-m64")
-else()
-  zephyr_compile_options(-m32)
-  zephyr_link_libraries(-m32)
-
-  target_link_options(native_simulator INTERFACE "-m32")
-  target_compile_options(native_simulator INTERFACE "-m32")
-
-  # When building for 32bits x86, gcc defaults to using the old 8087 float arithmetic
-  # which causes some issues with literal float comparisons. So we set it
-  # to use the SSE2 float path instead
-  # (clang defaults to use SSE, but, setting this option for it is safe)
-  check_set_compiler_property(APPEND PROPERTY fpsse2 "SHELL:-msse2 -mfpmath=sse")
-  zephyr_compile_options($<TARGET_PROPERTY:compiler,fpsse2>)
-  target_compile_options(native_simulator INTERFACE "$<TARGET_PROPERTY:compiler,fpsse2>")
-endif()

arch/riscv/Kconfig

@@ -361,7 +361,6 @@ config RISCV_PMP
 	select THREAD_LOCAL_STORAGE if USERSPACE
 	select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS
 	select MEM_DOMAIN_ISOLATED_STACKS
-	select PMP_KERNEL_MODE_DYNAMIC if MEM_ATTR
 	help
 	  MCU implements Physical Memory Protection.
 
@@ -410,20 +409,11 @@ config PMP_GRANULARITY
 	  (ie 4, 8, 16, ...), but if neither TOR mode nor NA4 mode is
 	  supported, the minimum granularity is 8.
 
-config PMP_NO_LOCK_GLOBAL
-	bool "Do not lock the global PMP entries"
-	select PMP_KERNEL_MODE_DYNAMIC
-	help
-	  Configure the PMP entries as unlocked (L=0) to implement PMP relative
-	  features. This allows application to dynamically reconfigure PMP
-	  entries without requiring hard reset.
-
 endif #RISCV_PMP
 
 config PMP_STACK_GUARD
 	def_bool y
 	depends on HW_STACK_PROTECTION
-	select PMP_KERNEL_MODE_DYNAMIC if MULTITHREADING
 
 config PMP_STACK_GUARD_MIN_SIZE
 	int "Stack Guard area size"
@@ -440,12 +430,6 @@ config PMP_STACK_GUARD_MIN_SIZE
 	  wiggle room to accommodate the eventual overflow exception
 	  stack usage.
 
-config PMP_KERNEL_MODE_DYNAMIC
-	bool
-	help
-	  Enable this to dynamically reconfigure and activate PMP entries for
-	  Machine mode when switching between kernel (ISR, syscall) and threads.
-
 # Implement the null pointer detection using the Physical Memory Protection
 # (PMP) Unit.
 config NULL_POINTER_EXCEPTION_DETECTION_PMP
@@ -476,17 +460,6 @@ config RISCV_IMPRECISE_FPU_STATE_TRACKING
 	  the floating-point register state imprecisely by reporting the state to be
 	  dirty even when it has not been modified. This option reflects that.
 
-config RISCV_SMRNMI_ENABLE_NMI_DELIVERY
-	bool "NMI delivery on SMRNMI hardware (MNSTATUS.NMIE=1)"
-	select RISCV_ISA_EXT_ZICSR
-	help
-	  Set MNSTATUS.NMIE bit to 1 during boot to enable NMI delivery on
-	  RISC-V hardware implementing the SMRNMI extension.
-
-	  This option only enables NMI delivery. It does not provide RNMI
-	  handlers or mnret instruction support. Proper RNMI handlers must
-	  be implemented in SoC-specific code to handle NMI events.
-
 endmenu
 
 config MAIN_STACK_SIZE

arch/riscv/Kconfig.isa

@@ -119,15 +119,6 @@ config RISCV_ISA_EXT_ZICSR
 	  The "Zicsr" extension introduces support for the full set of CSR
 	  instructions that operate on CSRs registers.
 
-config RISCV_ISA_EXT_SMCSRIND
-	bool
-	depends on RISCV_ISA_EXT_ZICSR
-	help
-	  (Smcsrind) - Standard Extension for Indirect CSR Access
-
-	  The Smcsrind extension provides indirect access to CSRs through
-	  the MISELECT and MIREG registers.
-
 config RISCV_ISA_EXT_ZIFENCEI
 	bool
 	help

arch/riscv/core/fatal.c

@@ -221,12 +221,12 @@ void z_riscv_fault(struct arch_esf *esf)
 	unsigned int reason = K_ERR_CPU_EXCEPTION;
 
 	if (bad_stack_pointer(esf)) {
-#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)
+#ifdef CONFIG_PMP_STACK_GUARD
 		/*
 		 * Remove the thread's PMP setting to prevent triggering a stack
 		 * overflow error again due to the previous configuration.
 		 */
-		z_riscv_pmp_kernelmode_disable();
+		z_riscv_pmp_stackguard_disable();
 #endif /* CONFIG_PMP_STACK_GUARD */
 		reason = K_ERR_STACK_CHK_FAIL;
 	}

arch/riscv/core/isr.S

@@ -368,19 +368,19 @@ no_fp:	/* increment _current->arch.exception_depth */
 	li t1, RISCV_EXC_ECALLU
 	beq t0, t1, is_user_syscall
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
+#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)
 	/*
 	 * Determine if we come from user space. If so, reconfigure the PMP for
-	 * kernel mode configuration.
+	 * kernel mode stack guard.
 	 */
 	csrr t0, mstatus
 	li t1, MSTATUS_MPP
 	and t0, t0, t1
 	bnez t0, 1f
 	lr a0, ___cpu_t_current_OFFSET(s0)
-	call z_riscv_pmp_kernelmode_enable
+	call z_riscv_pmp_stackguard_enable
 1:
-#endif /* CONFIG_PMP_KERNEL_MODE_DYNAMIC */
+#endif /* CONFIG_PMP_STACK_GUARD */
 
 #endif /* CONFIG_USERSPACE */
 
@@ -422,7 +422,7 @@ is_kernel_syscall:
 	addi t0, t0, 4
 	sr t0, __struct_arch_esf_mepc_OFFSET(sp)
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
+#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)
 	/* Re-activate PMP for m-mode */
 	li t1, MSTATUS_MPP
 	csrc mstatus, t1
@@ -515,13 +515,13 @@ do_irq_offload:
 #ifdef CONFIG_USERSPACE
 is_user_syscall:
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
+#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)
 	/*
 	 * We came from userspace and need to reconfigure the
-	 * PMP for kernel mode configuration.
+	 * PMP for kernel mode stack guard.
 	 */
 	lr a0, ___cpu_t_current_OFFSET(s0)
-	call z_riscv_pmp_kernelmode_enable
+	call z_riscv_pmp_stackguard_enable
 #endif
 
 	/* It is safe to re-enable IRQs now */
@@ -585,18 +585,18 @@ valid_syscall_id:
 
 is_interrupt:
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
+#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)
 #ifdef CONFIG_USERSPACE
 	/*
 	 * If we came from userspace then we need to reconfigure the
-	 * PMP for kernel mode configuration.
+	 * PMP for kernel mode stack guard.
 	 */
 	lr t0, __struct_arch_esf_mstatus_OFFSET(sp)
 	li t1, MSTATUS_MPP
 	and t0, t0, t1
 	bnez t0, 1f
 	lr a0, ___cpu_t_current_OFFSET(s0)
-	call z_riscv_pmp_kernelmode_enable
+	call z_riscv_pmp_stackguard_enable
 	j 2f
 #endif /* CONFIG_USERSPACE */
 1:	/* Re-activate PMP for m-mode */
@@ -769,8 +769,8 @@ fp_trap_exit:
 	and t0, t2, t1
 	bnez t0, 1f
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
-	/* Remove kernel mode configuration and Reconfigure PMP for user mode */
+#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)
+	/* Remove kernel stack guard and Reconfigure PMP for user mode */
 	lr a0, ___cpu_t_current_OFFSET(s0)
 	call z_riscv_pmp_usermode_enable
 #endif

arch/riscv/core/pmp.S

@@ -93,18 +93,6 @@ pmpcfg_done:
 	add t0, t0, a0
 	jr t0
 
-/*
- * Prototype:
- *
- * void z_riscv_clear_all_pmp_entries(void)
- *
- * Called from pmp.c to clear all PMP entries.
- *
- * Note: this is shared with tail clearing code above, hence the same section.
- */
-GTEXT(z_riscv_clear_all_pmp_entries)
-z_riscv_clear_all_pmp_entries:
-
 pmpcfg_zerotail:
 
 	.option push

arch/riscv/core/pmp.c

@@ -15,26 +15,22 @@
  * cycles on corresponding CSR registers. Relevant CSR registers are always
  * written in batch from their shadow copy in RAM for better efficiency.
  *
- * In the kernel mode case we keep an m-mode copy for each thread. Each user
+ * In the stackguard case we keep an m-mode copy for each thread. Each user
  * mode threads also has a u-mode copy. This makes faster context switching
  * as precomputed content just have to be written to actual registers with
  * no additional processing.
  *
  * Thread-specific m-mode and u-mode PMP entries start from the PMP slot
- * indicated by global_pmp_end_index[M_MODE] and global_pmp_end_index[U_MODE],
- * respectively. Lower slots are used by global entries which are never
- * modified.
+ * indicated by global_pmp_end_index. Lower slots are used by global entries
+ * which are never modified.
  */
 
-#include "zephyr/toolchain.h"
 #include <zephyr/kernel.h>
 #include <kernel_internal.h>
 #include <zephyr/linker/linker-defs.h>
 #include <pmp.h>
 #include <zephyr/arch/arch_interface.h>
 #include <zephyr/arch/riscv/csr.h>
-#include <zephyr/dt-bindings/memory-attr/memory-attr-riscv.h>
-#include <zephyr/mem_mgmt/mem_attr.h>
 
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
 #include <zephyr/logging/log.h>
@@ -58,47 +54,6 @@ LOG_MODULE_REGISTER(mpu);
 
 #define PMP_NONE 0
 
-#define PMP_PERM_MASK (PMP_R | PMP_W | PMP_X)
-
-/**
- * @brief Decodes PMP configuration and address registers into a memory region's
- * start/end addresses.
- *
- * @param cfg_byte The PMP configuration byte (pmpcfg_n).
- * @param pmp_addr A pointer to the full array of PMP address registers (pmpaddr_n).
- * @param index The current PMP entry index.
- * @param start Pointer to where the calculated start address should be stored.
- * @param end Pointer to where the calculated end address should be stored.
- */
-IF_DISABLED(CONFIG_ZTEST, (static))
-void pmp_decode_region(uint8_t cfg_byte, unsigned long *pmp_addr, unsigned int index,
-		       unsigned long *start, unsigned long *end)
-{
-	unsigned long tmp;
-	unsigned long pmp_addr_val = pmp_addr[index];
-	unsigned long pmp_prev_addr_val = (index == 0) ? 0 : pmp_addr[index - 1];
-
-	switch (cfg_byte & PMP_A) {
-	case PMP_TOR:
-		*start = (index == 0) ? 0 : (pmp_prev_addr_val << 2);
-		*end   = (pmp_addr_val << 2) - 1;
-		break;
-	case PMP_NA4:
-		*start = pmp_addr_val << 2;
-		*end   = *start + 3;
-		break;
-	case PMP_NAPOT:
-		tmp = (pmp_addr_val << 2) | 0x3;
-		*start = tmp & (tmp + 1);
-		*end   = tmp | (tmp + 1);
-		break;
-	default:
-		*start = 0;
-		*end   = 0;
-		break;
-	}
-}
-
 static void print_pmp_entries(unsigned int pmp_start, unsigned int pmp_end,
 			      unsigned long *pmp_addr, unsigned long *pmp_cfg,
 			      const char *banner)
@@ -108,9 +63,27 @@ static void print_pmp_entries(unsigned int pmp_start, unsigned int pmp_end,
 
 	LOG_DBG("PMP %s:", banner);
 	for (index = pmp_start; index < pmp_end; index++) {
-		unsigned long start, end;
+		unsigned long start, end, tmp;
 
-		pmp_decode_region(pmp_n_cfg[index], pmp_addr, index, &start, &end);
+		switch (pmp_n_cfg[index] & PMP_A) {
+		case PMP_TOR:
+			start = (index == 0) ? 0 : (pmp_addr[index - 1] << 2);
+			end = (pmp_addr[index] << 2) - 1;
+			break;
+		case PMP_NA4:
+			start = pmp_addr[index] << 2;
+			end = start + 3;
+			break;
+		case PMP_NAPOT:
+			tmp = (pmp_addr[index] << 2) | 0x3;
+			start = tmp & (tmp + 1);
+			end   = tmp | (tmp + 1);
+			break;
+		default:
+			start = 0;
+			end = 0;
+			break;
+		}
 
 		if (end == 0) {
 			LOG_DBG("%3d: "PR_ADDR" 0x%02x", index,
@@ -139,8 +112,7 @@ static void print_pmp_entries(unsigned int pmp_start, unsigned int pmp_end,
  * @param pmp_cfg Pointer to the array where the CSR contents will be stored.
  * @param pmp_cfg_size The size of the pmp_cfg array, measured in unsigned long entries.
  */
-IF_DISABLED(CONFIG_ZTEST, (static inline))
-void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size)
+static inline void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size)
 {
 	__ASSERT(pmp_cfg_size == (size_t)(CONFIG_PMP_SLOTS / PMPCFG_STRIDE),
 		 "Invalid PMP config array size");
@@ -172,8 +144,7 @@ void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size)
  * @param pmp_addr Pointer to the array where the CSR contents will be stored.
  * @param pmp_addr_size The size of the pmp_addr array, measured in unsigned long entries.
  */
-IF_DISABLED(CONFIG_ZTEST, (static inline))
-void z_riscv_pmp_read_addr(unsigned long *pmp_addr, size_t pmp_addr_size)
+static inline void z_riscv_pmp_read_addr(unsigned long *pmp_addr, size_t pmp_addr_size)
 {
 	__ASSERT(pmp_addr_size == (size_t)(CONFIG_PMP_SLOTS), "PMP address array size mismatch");
 
@@ -265,7 +236,7 @@ static bool set_pmp_entry(unsigned int *index_p, uint8_t perm,
 	return ok;
 }
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
+#ifdef CONFIG_PMP_STACK_GUARD
 static inline bool set_pmp_mprv_catchall(unsigned int *index_p,
 					 unsigned long *pmp_addr, unsigned long *pmp_cfg,
 					 unsigned int index_limit)
@@ -293,7 +264,7 @@ static inline bool set_pmp_mprv_catchall(unsigned int *index_p,
 
 	return ok;
 }
-#endif /* CONFIG_PMP_KERNEL_MODE_DYNAMIC */
+#endif /* CONFIG_PMP_STACK_GUARD */
 
 /**
  * @brief Write a range of PMP entries to corresponding PMP registers
@@ -377,86 +348,6 @@ static void write_pmp_entries(unsigned int start, unsigned int end,
 				  pmp_addr, pmp_cfg);
 }
 
-#ifdef CONFIG_MEM_ATTR
-/**
- * @brief Install PMP entries from devicetree mem-attr regions.
- *
- * Iterates over devicetree-provided memory-attr regions and programs PMP
- * via set_pmp_entry(). Ordering matters because PMP checks entries from lowest
- * to highest index and uses the first entry that matches the address.
- *
- * @param index_p Location of the current PMP slot index to use. This index
- *                will be updated according to the number of slots used.
- * @param pmp_addr Array of pmpaddr values (starting at entry 0).
- * @param pmp_cfg Array of pmpcfg values (starting at entry 0).
- * @param index_limit Index value representing the size of the provided arrays.
- * @return Number of PMP slots consumed by installed mem-attr regions.
- *
- * @note DT_MEM_RISCV_TYPE_IO_X Limitation:
- * Since the current PMP entries are non-locked, the eXecute (X)
- * permission restriction applied by DT_MEM_RISCV_TYPE_IO_X does
- * not prevent execution in higher privilege modes (M-mode/kernel).
- * This is because the mstatus.MPRV register bit only affects
- * M-mode load/store operations, not instruction fetches.
- * The execute restriction still applies to User mode because PMP
- * is always enforced for lower privilege modes.
- */
-static unsigned int set_pmp_mem_attr(unsigned int *index_p,
-				     unsigned long *pmp_addr, unsigned long *pmp_cfg,
-				     unsigned int index_limit)
-{
-	const struct mem_attr_region_t *region;
-	unsigned int entry_cnt = *index_p;
-	size_t num_regions;
-
-	num_regions = mem_attr_get_regions(&region);
-
-	for (size_t idx = 0; idx < num_regions; ++idx) {
-
-		uint8_t perm = DT_MEM_RISCV_TO_PMP_PERM(region[idx].dt_attr);
-
-		if (perm || (region[idx].dt_attr & DT_MEM_RISCV_TYPE_EMPTY)) {
-			set_pmp_entry(index_p, perm,
-				(uintptr_t)(region[idx].dt_addr),
-				(size_t)(region[idx].dt_size),
-				pmp_addr, pmp_cfg, index_limit);
-		}
-	}
-
-	entry_cnt = *index_p - entry_cnt;
-
-	return entry_cnt;
-}
-#endif /* CONFIG_MEM_ATTR */
-
-/**
- * @brief Clear and disable all Physical Memory Protection (PMP) entries.
- *
- * This function clears all PMP configuration CSRs (pmpcfgX) by writing
- * zero to them for all entries defined by CONFIG_PMP_SLOTS.
- *
- * This unconditional write sets the Address Matching Mode ('A' field) to
- * 'OFF' (0x00) for every entry, effectively disabling the PMP mechanism.
- *
- * This routine does not check the Lock bit. Changes to locked PMP entries
- * will be silently ignored by the hardware.
- *
- * It is implemented in assembly (pmp.S) for efficient RISC-V CSR access.
- */
-extern void z_riscv_clear_all_pmp_entries(void);
-
-void z_riscv_pmp_clear_all(void)
-{
-	/*
-	 * Ensure we are in M-mode and that memory accesses use M-mode privileges
-	 * (MPRV=0). We also set MPP to M-mode to establish a predictable prior privilege level.
-	 */
-	csr_clear(mstatus, MSTATUS_MPRV);
-	csr_set(mstatus, MSTATUS_MPP);
-
-	z_riscv_clear_all_pmp_entries();
-}
-
 /**
  * @brief Abstract the last 3 arguments to set_pmp_entry() and
  *        write_pmp_entries( for m-mode.
@@ -477,115 +368,16 @@ void z_riscv_pmp_clear_all(void)
 
 /*
  * Stores the initial values of the pmpcfg CSRs, covering all global
- * m-mode and u-mode PMP entries. This array is sized to hold all pmpcfg
- * registers necessary for CONFIG_PMP_SLOTS. It is used to seed the
- * per-thread PMP configuration copies. Locked entries aren't modifiable
- * but we could have non-locked entries here too.
+ * m-mode PMP entries. This array is sized to hold all pmpcfg registers
+ * necessary for CONFIG_PMP_SLOTS. It is used to seed the per-thread
+ * PMP configuration copies. Locked entries aren't modifiable but
+ * we could have non-locked entries here too.
  */
 static unsigned long global_pmp_cfg[CONFIG_PMP_SLOTS / PMPCFG_STRIDE];
+static unsigned long global_pmp_last_addr;
 
-/*
- * Defines an enumeration for PMP operating modes (M or U) to index the
- * PMP state arrays.
- */
-enum pmp_mode {
-	M_MODE = 0,
-#if defined(CONFIG_USERSPACE)
-	U_MODE,
-#endif /* CONFIG_USERSPACE */
-	MODE_TOTAL
-};
-
-/* Last address of global PMP entry range for each mode (M or U). */
-static unsigned long global_pmp_last_addr[MODE_TOTAL];
-/* End of global PMP entry range for each mode (M or U). */
-static unsigned int global_pmp_end_index[MODE_TOTAL];
-
-#if defined(CONFIG_MEM_ATTR) && defined(CONFIG_USERSPACE)
-/* Stores the initial pmpaddr values for the memory attribute region. */
-static unsigned long mem_attr_pmp_addr[CONFIG_PMP_SLOTS];
-#endif
-
-#ifdef CONFIG_MEM_ATTR
-int z_riscv_pmp_change_permissions(size_t region_idx, uint8_t perm)
-{
-	if (perm & ~PMP_PERM_MASK) {
-		LOG_ERR("Invalid PMP permission 0x%x. Only R, W, X (0x%x) are allowed.", perm,
-			PMP_PERM_MASK);
-		return -EINVAL;
-	}
-
-	const struct mem_attr_region_t *region;
-	size_t num_regions;
-
-	num_regions = mem_attr_get_regions(&region);
-
-	if (region_idx >= num_regions) {
-		LOG_ERR("region_idx %zu is out of bounds (num_regions: %zu)", region_idx,
-			num_regions);
-		return -EINVAL;
-	}
-
-	uintptr_t region_start_address = region[region_idx].dt_addr;
-	size_t region_size = region[region_idx].dt_size;
-	int entry_index = -1;
-
-	size_t pmp_cfg_size = CONFIG_PMP_SLOTS / PMPCFG_STRIDE;
-	unsigned long pmp_addr[CONFIG_PMP_SLOTS];
-	unsigned long pmp_cfg[pmp_cfg_size];
-
-	/*
-	 * The PMP configuration update (reading and writing) must be performed with
-	 * interrupts disabled. This prevents thread preemption from splitting the
-	 * atomic read-modify-write operation, which could lead to a catastrophic
-	 * half-configured state. Unlike other PMP functions, this is not called
-	 * from an already-atomic context.
-	 */
-	unsigned int key = arch_irq_lock();
-
-	z_riscv_pmp_read_addr(pmp_addr, (size_t)(CONFIG_PMP_SLOTS));
-	z_riscv_pmp_read_config(pmp_cfg, pmp_cfg_size);
-
-	uint8_t *pmp_n_cfg = (uint8_t *)pmp_cfg;
-
-	for (unsigned int index = 0; index < CONFIG_PMP_SLOTS; ++index) {
-		unsigned long start, end;
-
-		pmp_decode_region(pmp_n_cfg[index], pmp_addr, index, &start, &end);
-		if (start == region_start_address &&
-		    end == (region_start_address + region_size - 1)) {
-			entry_index = index;
-			break;
-		}
-	}
-
-	if (entry_index == -1) {
-		LOG_ERR("PMP entry for address 0x%lx not found", region_start_address);
-		arch_irq_unlock(key);
-		return -ENOENT;
-	}
-
-	/*
-	 * Clear the old R/W/X bits while preserving all other bits and tet the new R/W/X bits from
-	 * the 'perm' variable.
-	 */
-	pmp_n_cfg[entry_index] &= ~PMP_PERM_MASK;
-	pmp_n_cfg[entry_index] |= perm;
-
-	/*
-	 * Disable (non-locked) PMP entries for m-mode while we update them.
-	 * While at it, also clear MSTATUS_MPP as it must be cleared for
-	 * MSTATUS_MPRV to be effective later.
-	 */
-	csr_clear(mstatus, MSTATUS_MPRV | MSTATUS_MPP);
-	write_pmp_entries(entry_index, entry_index + 1, false, pmp_addr, pmp_cfg,
-			  ARRAY_SIZE(pmp_addr));
-	csr_set(mstatus, MSTATUS_MPRV);
-	arch_irq_unlock(key);
-
-	return 0;
-}
-#endif /* CONFIG_MEM_ATTR */
+/* End of global PMP entry range */
+static unsigned int global_pmp_end_index;
 
 /**
  * @Brief Initialize the PMP with global entries on each CPU
@@ -593,26 +385,22 @@ int z_riscv_pmp_change_permissions(size_t region_idx, uint8_t perm)
 void z_riscv_pmp_init(void)
 {
 	unsigned long pmp_addr[CONFIG_PMP_SLOTS];
-	unsigned long pmp_cfg[CONFIG_PMP_SLOTS / PMPCFG_STRIDE] = {0};
+	unsigned long pmp_cfg[CONFIG_PMP_SLOTS / PMPCFG_STRIDE];
 	unsigned int index = 0;
-	unsigned int attr_cnt = 0;
-
-	ARG_UNUSED(attr_cnt);
 
 #ifdef CONFIG_NULL_POINTER_EXCEPTION_DETECTION_PMP
 	/*
 	 * Use a PMP slot to make region (starting at address 0x0) inaccessible
 	 * for detecting null pointer dereferencing.
 	 */
-	set_pmp_entry(&index, PMP_NONE | COND_CODE_1(CONFIG_PMP_NO_LOCK_GLOBAL, (0x0), (PMP_L)),
+	set_pmp_entry(&index, PMP_NONE | PMP_L,
 		      0,
 		      CONFIG_NULL_POINTER_EXCEPTION_REGION_SIZE,
 		      pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
 #endif
 
 	/* The read-only area is always there for every mode */
-	set_pmp_entry(&index,
-		      PMP_R | PMP_X | COND_CODE_1(CONFIG_PMP_NO_LOCK_GLOBAL, (0x0), (PMP_L)),
+	set_pmp_entry(&index, PMP_R | PMP_X | PMP_L,
 		      (uintptr_t)__rom_region_start,
 		      (size_t)__rom_region_size,
 		      pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
@@ -621,60 +409,48 @@ void z_riscv_pmp_init(void)
 #ifdef CONFIG_MULTITHREADING
 	/*
 	 * Set the stack guard for this CPU's IRQ stack by making the bottom
-	 * addresses inaccessible. This will never change so we do it here.
+	 * addresses inaccessible. This will never change so we do it here
+	 * and lock it too.
 	 */
-	set_pmp_entry(&index, PMP_NONE | COND_CODE_1(CONFIG_PMP_NO_LOCK_GLOBAL, (0x0), (PMP_L)),
+	set_pmp_entry(&index, PMP_NONE | PMP_L,
 		      (uintptr_t)z_interrupt_stacks[_current_cpu->id],
 		      Z_RISCV_STACK_GUARD_SIZE,
 		      pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
-#else
-	/* Without multithreading setup stack guards for IRQ and main stacks */
-	set_pmp_entry(&index, PMP_NONE | COND_CODE_1(CONFIG_PMP_NO_LOCK_GLOBAL, (0x0), (PMP_L)),
-		      (uintptr_t)z_interrupt_stacks,
-		      Z_RISCV_STACK_GUARD_SIZE,
-		      pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
 
-	set_pmp_entry(&index, PMP_NONE | COND_CODE_1(CONFIG_PMP_NO_LOCK_GLOBAL, (0x0), (PMP_L)),
-		      (uintptr_t)z_main_stack,
-		      Z_RISCV_STACK_GUARD_SIZE,
-		      pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
-
-#endif /* CONFIG_MULTITHREADING */
-#ifdef CONFIG_SMP
-	unsigned int irq_index = index;
-#endif /* CONFIG_SMP */
-#endif
-
-#ifdef CONFIG_MEM_ATTR
 	/*
-	 * Set the memory attribute region as temporary PMP entries for early
-	 * kernel initialization. This provides essential protection before
-	 * the kernel mode memory attribute permission is fully operational.
-	 */
-	attr_cnt = set_pmp_mem_attr(&index, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
-#endif /* CONFIG_MEM_ATTR */
-
-#if defined(CONFIG_MEM_ATTR) || defined(CONFIG_PMP_NO_LOCK_GLOBAL)
-	/*
-	 * This early, we want to protect unlock PMP entries as soon as
-	 * possible. But we need a temporary default "catch all" PMP entry for
-	 * MPRV to work. Later on, this entry will be set for each thread by
-	 * z_riscv_pmp_kernelmode_prepare().
+	 * This early, the kernel init code uses the IRQ stack and we want to
+	 * safeguard it as soon as possible. But we need a temporary default
+	 * "catch all" PMP entry for MPRV to work. Later on, this entry will
+	 * be set for each thread by z_riscv_pmp_stackguard_prepare().
 	 */
 	set_pmp_mprv_catchall(&index, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
 
-	/* Write those entries to PMP regs. */
+	 /* Write those entries to PMP regs. */
 	write_pmp_entries(0, index, true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
 
 	/* Activate our non-locked PMP entries for m-mode */
-	csr_clear(mstatus, MSTATUS_MPP);
 	csr_set(mstatus, MSTATUS_MPRV);
 
 	/* And forget about that last entry as we won't need it later */
 	index--;
 #else
+	/* Without multithreading setup stack guards for IRQ and main stacks */
+	set_pmp_entry(&index, PMP_NONE | PMP_L,
+		      (uintptr_t)z_interrupt_stacks,
+		      Z_RISCV_STACK_GUARD_SIZE,
+		      pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
+
+	set_pmp_entry(&index, PMP_NONE | PMP_L,
+		      (uintptr_t)z_main_stack,
+		      Z_RISCV_STACK_GUARD_SIZE,
+		      pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
+
 	/* Write those entries to PMP regs. */
 	write_pmp_entries(0, index, true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
+#endif /* CONFIG_MULTITHREADING */
+#else
+	 /* Write those entries to PMP regs. */
+	write_pmp_entries(0, index, true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
 #endif
 
 #ifdef CONFIG_SMP
@@ -684,36 +460,21 @@ void z_riscv_pmp_init(void)
 	 * Make sure TOR entry sharing won't be attempted with it by
 	 * remembering a bogus address for those entries.
 	 */
-	pmp_addr[irq_index - 1] = -1L;
+	pmp_addr[index - 1] = -1L;
 #endif
 
 	/* Make sure secondary CPUs produced the same values */
-	if (global_pmp_end_index[M_MODE] != 0) {
-		__ASSERT(global_pmp_end_index[M_MODE] == index, "");
+	if (global_pmp_end_index != 0) {
+		__ASSERT(global_pmp_end_index == index, "");
 		__ASSERT(global_pmp_cfg[index / PMPCFG_STRIDE] == pmp_cfg[index / PMPCFG_STRIDE],
 			 "");
-		__ASSERT(global_pmp_last_addr[M_MODE] == pmp_addr[index - 1], "");
+		__ASSERT(global_pmp_last_addr == pmp_addr[index - 1], "");
 	}
 #endif
 
 	memcpy(global_pmp_cfg, pmp_cfg, sizeof(pmp_cfg));
-	global_pmp_last_addr[M_MODE] = pmp_addr[index - 1];
-	global_pmp_end_index[M_MODE] = index;
-
-#ifdef CONFIG_USERSPACE
-	global_pmp_last_addr[U_MODE] = pmp_addr[index - attr_cnt - 1];
-	global_pmp_end_index[U_MODE] = index - attr_cnt;
-#endif /* CONFIG_USERSPACE */
-
-#if defined(CONFIG_MEM_ATTR) && defined(CONFIG_USERSPACE)
-	/*
-	 * Copy the memory attribute pmpaddr entries to the global buffer.
-	 * These kernel mode pmpaddr entries are saved for restoration when
-	 * switching back from user mode.
-	 */
-	memcpy(mem_attr_pmp_addr, &pmp_addr[global_pmp_end_index[U_MODE]],
-	       attr_cnt * PMPCFG_STRIDE);
-#endif
+	global_pmp_last_addr = pmp_addr[index - 1];
+	global_pmp_end_index = index;
 
 	if (PMP_DEBUG_DUMP) {
 		dump_pmp_regs("initial register dump");
@@ -723,9 +484,9 @@ void z_riscv_pmp_init(void)
 /**
  * @Brief Initialize the per-thread PMP register copy with global values.
  */
-#if defined(CONFIG_PMP_KERNEL_MODE_DYNAMIC) || defined(CONFIG_USERSPACE)
-static inline unsigned int z_riscv_pmp_thread_init(enum pmp_mode mode,
-						   unsigned long *pmp_addr, unsigned long *pmp_cfg,
+#if (defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)) || defined(CONFIG_USERSPACE)
+static inline unsigned int z_riscv_pmp_thread_init(unsigned long *pmp_addr,
+						   unsigned long *pmp_cfg,
 						   unsigned int index_limit)
 {
 	ARG_UNUSED(index_limit);
@@ -739,38 +500,23 @@ static inline unsigned int z_riscv_pmp_thread_init(enum pmp_mode mode,
 	 * Retrieve the pmpaddr value matching the last global PMP slot.
 	 * This is so that set_pmp_entry() can safely attempt TOR with it.
 	 */
-	unsigned int pmp_end_index = global_pmp_end_index[mode];
+	pmp_addr[global_pmp_end_index - 1] = global_pmp_last_addr;
 
-	pmp_addr[pmp_end_index - 1] = global_pmp_last_addr[mode];
-
-#if defined(CONFIG_MEM_ATTR) && defined(CONFIG_USERSPACE)
-	/*
-	 * This block restores the PMP entries used for memory attributes (set in
-	 * mem_attr_pmp_addr) that were overwritten when switching from user mode
-	 * back to kernel mode. It only applies when running in M_MODE pmp mode.
-	 */
-	if (mode == M_MODE) {
-		memcpy(&pmp_addr[global_pmp_end_index[U_MODE]], mem_attr_pmp_addr,
-		       (global_pmp_end_index[M_MODE] - global_pmp_end_index[U_MODE]) *
-			       PMPCFG_STRIDE);
-	}
-#endif
-
-	return pmp_end_index;
+	return global_pmp_end_index;
 }
 #endif
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
+#ifdef CONFIG_PMP_STACK_GUARD
+
+#ifdef CONFIG_MULTITHREADING
 /**
- * @brief Prepare the PMP kernelmode content for given thread.
+ * @brief Prepare the PMP stackguard content for given thread.
  *
  * This is called once during new thread creation.
  */
-void z_riscv_pmp_kernelmode_prepare(struct k_thread *thread)
+void z_riscv_pmp_stackguard_prepare(struct k_thread *thread)
 {
-	unsigned int index = z_riscv_pmp_thread_init(M_MODE, PMP_M_MODE(thread));
-
-#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING)
+	unsigned int index = z_riscv_pmp_thread_init(PMP_M_MODE(thread));
 	uintptr_t stack_bottom;
 
 	/* make the bottom addresses of our stack inaccessible */
@@ -781,12 +527,10 @@ void z_riscv_pmp_kernelmode_prepare(struct k_thread *thread)
 	} else if (z_stack_is_user_capable(thread->stack_obj)) {
 		stack_bottom = thread->stack_info.start - K_THREAD_STACK_RESERVED;
 	}
-#endif /* CONFIG_USERSPACE */
+#endif
 	set_pmp_entry(&index, PMP_NONE,
 		      stack_bottom, Z_RISCV_STACK_GUARD_SIZE,
 		      PMP_M_MODE(thread));
-#endif /* CONFIG_PMP_STACK_GUARD */
-
 	set_pmp_mprv_catchall(&index, PMP_M_MODE(thread));
 
 	/* remember how many entries we use */
@@ -794,13 +538,13 @@ void z_riscv_pmp_kernelmode_prepare(struct k_thread *thread)
 }
 
 /**
- * @brief Write PMP kernel mode content to actual PMP registers
+ * @brief Write PMP stackguard content to actual PMP registers
  *
  * This is called on every context switch.
  */
-void z_riscv_pmp_kernelmode_enable(struct k_thread *thread)
+void z_riscv_pmp_stackguard_enable(struct k_thread *thread)
 {
-	LOG_DBG("pmp_kernelmode_enable for thread %p", thread);
+	LOG_DBG("pmp_stackguard_enable for thread %p", thread);
 
 	/*
 	 * Disable (non-locked) PMP entries for m-mode while we update them.
@@ -810,17 +554,9 @@ void z_riscv_pmp_kernelmode_enable(struct k_thread *thread)
 	csr_clear(mstatus, MSTATUS_MPRV | MSTATUS_MPP);
 
 	/* Write our m-mode MPP entries */
-#ifdef CONFIG_USERSPACE
-	write_pmp_entries(global_pmp_end_index[U_MODE],
-			  thread->arch.m_mode_pmp_end_index,
+	write_pmp_entries(global_pmp_end_index, thread->arch.m_mode_pmp_end_index,
 			  false /* no need to clear to the end */,
 			  PMP_M_MODE(thread));
-#else
-	write_pmp_entries(global_pmp_end_index[M_MODE],
-			  thread->arch.m_mode_pmp_end_index,
-			  false /* no need to clear to the end */,
-			  PMP_M_MODE(thread));
-#endif /* CONFIG_USERSPACE */
 
 	if (PMP_DEBUG_DUMP) {
 		dump_pmp_regs("m-mode register dump");
@@ -830,18 +566,20 @@ void z_riscv_pmp_kernelmode_enable(struct k_thread *thread)
 	csr_set(mstatus, MSTATUS_MPRV);
 }
 
+#endif /* CONFIG_MULTITHREADING */
+
 /**
- * @brief Remove PMP kernel mode content to actual PMP registers
+ * @brief Remove PMP stackguard content to actual PMP registers
  */
-void z_riscv_pmp_kernelmode_disable(void)
+void z_riscv_pmp_stackguard_disable(void)
 {
 
 	unsigned long pmp_addr[CONFIG_PMP_SLOTS];
 	unsigned long pmp_cfg[CONFIG_PMP_SLOTS / PMPCFG_STRIDE];
-	unsigned int index = global_pmp_end_index[M_MODE];
+	unsigned int index = global_pmp_end_index;
 
 	/* Retrieve the pmpaddr value matching the last global PMP slot. */
-	pmp_addr[index - 1] = global_pmp_last_addr[M_MODE];
+	pmp_addr[global_pmp_end_index - 1] = global_pmp_last_addr;
 
 	/* Disable (non-locked) PMP entries for m-mode while we update them. */
 	csr_clear(mstatus, MSTATUS_MPRV);
@@ -853,14 +591,15 @@ void z_riscv_pmp_kernelmode_disable(void)
 	set_pmp_mprv_catchall(&index, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
 
 	/* Write "catch all" entry and clear unlocked entries to PMP regs. */
-	write_pmp_entries(global_pmp_end_index[M_MODE], index,
+	write_pmp_entries(global_pmp_end_index, index,
 			  true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr));
 
 	if (PMP_DEBUG_DUMP) {
 		dump_pmp_regs("catch all register dump");
 	}
 }
-#endif /* CONFIG_PMP_KERNEL_MODE_DYNAMIC */
+
+#endif /* CONFIG_PMP_STACK_GUARD */
 
 #ifdef CONFIG_USERSPACE
 
@@ -882,7 +621,7 @@ void z_riscv_pmp_usermode_init(struct k_thread *thread)
  */
 void z_riscv_pmp_usermode_prepare(struct k_thread *thread)
 {
-	unsigned int index = z_riscv_pmp_thread_init(U_MODE, PMP_U_MODE(thread));
+	unsigned int index = z_riscv_pmp_thread_init(PMP_U_MODE(thread));
 
 	LOG_DBG("pmp_usermode_prepare for thread %p", thread);
 
@@ -926,52 +665,8 @@ static void resync_pmp_domain(struct k_thread *thread,
 			continue;
 		}
 
-#ifdef CONFIG_MEM_ATTR
-		/*
-		 * Determine whether the partition is covered by a memory
-		 * attribute region.
-		 *
-		 * Constraint due to number of PMP entry limitation:
-		 * The logic asserts against any cases that requires splitting
-		 * a partition into multiple permissions, such as partial
-		 * overlap or the partition fully containing the memory
-		 * attribute region but not fully match.
-		 *
-		 * Supported cases:
-		 * 1. Partition excludes all memory attribute regions
-		 *    The partition's permission is applied directly.
-		 * 2. Partition is contained in a memory attribute region:
-		 *    The partition's permission is masked with the memory
-		 *    attribute.
-		 */
-		const struct mem_attr_region_t *region;
-		uint8_t attr_mask = PMP_R | PMP_W | PMP_X;
-
-		for (int idx = 0; idx < mem_attr_get_regions(&region); idx++) {
-			uintptr_t dt_start = (uintptr_t)(region[idx].dt_addr);
-			uintptr_t dt_end = dt_start + (size_t)(region[idx].dt_size);
-			bool covered = false;
-
-			/* No overlap at all, skip this memory region */
-			if ((part->start + part->size) <= dt_start || part->start >= dt_end) {
-				continue;
-			}
-
-			/* Check if the partition is contained in the memory attribute region. */
-			covered = part->start >= dt_start && (part->start + part->size) <= dt_end;
-			__ASSERT(covered, "No allowed partition partially overlaps memory region");
-
-			attr_mask = DT_MEM_RISCV_TO_PMP_PERM(region[idx].dt_attr);
-			break;
-		}
-
-		ok = set_pmp_entry(&index, part->attr.pmp_attr & attr_mask, part->start, part->size,
-				   PMP_U_MODE(thread));
-#else
-		ok = set_pmp_entry(&index, part->attr.pmp_attr, part->start, part->size,
-				   PMP_U_MODE(thread));
-#endif
-
+		ok = set_pmp_entry(&index, part->attr.pmp_attr,
+				   part->start, part->size, PMP_U_MODE(thread));
 		__ASSERT(ok,
 			 "no PMP slot left for %d remaining partitions in domain %p",
 			 remaining_partitions + 1, domain);
@@ -1007,14 +702,13 @@ void z_riscv_pmp_usermode_enable(struct k_thread *thread)
 		resync_pmp_domain(thread, domain);
 	}
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
+#ifdef CONFIG_PMP_STACK_GUARD
 	/* Make sure m-mode PMP usage is disabled before we reprogram it */
 	csr_clear(mstatus, MSTATUS_MPRV);
 #endif
 
 	/* Write our u-mode MPP entries */
-	write_pmp_entries(global_pmp_end_index[U_MODE],
-			  thread->arch.u_mode_pmp_end_index,
+	write_pmp_entries(global_pmp_end_index, thread->arch.u_mode_pmp_end_index,
 			  true /* must clear to the end */,
 			  PMP_U_MODE(thread));
 
@@ -1028,7 +722,7 @@ int arch_mem_domain_max_partitions_get(void)
 	int available_pmp_slots = CONFIG_PMP_SLOTS;
 
 	/* remove those slots dedicated to global entries */
-	available_pmp_slots -= global_pmp_end_index[U_MODE];
+	available_pmp_slots -= global_pmp_end_index;
 
 	/*
 	 * User thread stack mapping:

arch/riscv/core/reset.S

@@ -9,7 +9,6 @@
 #include <zephyr/linker/sections.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/offsets.h>
-#include <zephyr/arch/riscv/csr.h>
 #include "asm_macros.inc"
 
 /* exports */
@@ -83,10 +82,6 @@ aa_loop:
 	li t0, __z_interrupt_stack_SIZEOF
 	add sp, sp, t0
 
-#ifdef CONFIG_RISCV_SMRNMI_ENABLE_NMI_DELIVERY
-	csrs CSR_MNSTATUS, MNSTATUS_NMIE
-#endif
-
 #ifdef CONFIG_WDOG_INIT
 	call _WdogInit
 #endif

arch/riscv/core/stacktrace.c

@@ -41,17 +41,8 @@ static inline bool in_kernel_thread_stack_bound(uintptr_t addr, const struct k_t
 #ifdef CONFIG_THREAD_STACK_INFO
 	uintptr_t start, end;
 
-	/*
-	 * Special handling to support stacktrace in dummy thread during system initialization,
-	 * as its stack info isn't initialized.
-	 */
-	if (is_thread_dummy(thread)) {
-		start = (uintptr_t)z_interrupt_stacks;
-		end = Z_STACK_PTR_ALIGN(start + __z_interrupt_stack_SIZEOF);
-	} else {
-		start = thread->stack_info.start;
-		end = Z_STACK_PTR_ALIGN(thread->stack_info.start + thread->stack_info.size);
-	}
+	start = thread->stack_info.start;
+	end = Z_STACK_PTR_ALIGN(thread->stack_info.start + thread->stack_info.size);
 
 	return (addr >= start) && (addr < end);
 #else

arch/riscv/core/switch.S

@@ -61,17 +61,16 @@ SECTION_FUNC(TEXT, z_riscv_switch)
 	mv a0, s0
 #endif
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
-	/* Kernel mode has priority over user space for PMP usage. */
+#if defined(CONFIG_PMP_STACK_GUARD)
+	/* Stack guard has priority over user space for PMP usage. */
 	mv s0, a0
-	call z_riscv_pmp_kernelmode_enable
+	call z_riscv_pmp_stackguard_enable
 	mv a0, s0
 #elif defined(CONFIG_USERSPACE)
 	/*
-	 * When kernel mode dynamic configuration is not enabled, we need to
-	 * configure the PMP only at context switch time as the PMP is not
-	 * in effect while in m-mode. (it is done on every exception return
-	 * otherwise).
+	 * When stackguard is not enabled, we need to configure the PMP only
+	 * at context switch time as the PMP is not in effect while inm-mode.
+	 * (it is done on every exception return otherwise).
 	 */
 	lb t0, _thread_offset_to_user_options(a0)
 	andi t0, t0, K_USER

arch/riscv/core/thread.c

@@ -89,18 +89,18 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 		/* Supervisor thread */
 		stack_init->mepc = (unsigned long)z_thread_entry;
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
+#if defined(CONFIG_PMP_STACK_GUARD)
 		/* Enable PMP in mstatus.MPRV mode for RISC-V machine mode
 		 * if thread is supervisor thread.
 		 */
 		stack_init->mstatus |= MSTATUS_MPRV;
-#endif /* CONFIG_PMP_KERNEL_MODE_DYNAMIC */
+#endif /* CONFIG_PMP_STACK_GUARD */
 	}
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
-	/* Setup PMP regions of kernel mode configuration of thread. */
-	z_riscv_pmp_kernelmode_prepare(thread);
-#endif /* CONFIG_PMP_KERNEL_MODE_DYNAMIC */
+#if defined(CONFIG_PMP_STACK_GUARD)
+	/* Setup PMP regions of PMP stack guard of thread. */
+	z_riscv_pmp_stackguard_prepare(thread);
+#endif /* CONFIG_PMP_STACK_GUARD */
 
 #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
 	stack_init->soc_context = soc_esf_init;
@@ -176,9 +176,9 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
 	csr_write(mstatus, status);
 	csr_write(mepc, z_thread_entry);
 
-#ifdef CONFIG_PMP_KERNEL_MODE_DYNAMIC
-	/* reconfigure as the kernel mode configuration will be different */
-	z_riscv_pmp_kernelmode_prepare(_current);
+#ifdef CONFIG_PMP_STACK_GUARD
+	/* reconfigure as the kernel mode stack will be different */
+	z_riscv_pmp_stackguard_prepare(_current);
 #endif
 
 	/* Set up Physical Memory Protection */

arch/riscv/custom/CMakeLists.txt

@@ -6,5 +6,4 @@ add_subdirectory_ifdef(CONFIG_DT_HAS_OPENHWGROUP_CVA6_ENABLED openhwgroup/cva6)
 add_subdirectory_ifdef(CONFIG_DT_HAS_NUCLEI_BUMBLEBEE_ENABLED nuclei)
 add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_RI5CY_ENABLED openisa/ri5cy)
 add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_ZERO_RI5CY_ENABLED openisa/zero_riscy)
-add_subdirectory_ifdef(CONFIG_DT_HAS_SPINALHDL_VEXRISCV_ENABLED vexriscv)
 add_subdirectory_ifdef(CONFIG_DT_HAS_XUANTIE_E907_ENABLED thead)

arch/riscv/custom/Kconfig

@@ -7,12 +7,6 @@ rsource "andes/Kconfig"
 
 endif # DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED
 
-if DT_HAS_SPINALHDL_VEXRISCV_ENABLED
-
-rsource "vexriscv/Kconfig"
-
-endif # DT_HAS_SPINALHDL_VEXRISCV_ENABLED
-
 if DT_HAS_XUANTIE_E907_ENABLED
 
 rsource "thead/Kconfig"

arch/riscv/custom/vexriscv/CMakeLists.txt

@@ -1,4 +0,0 @@
-# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_VEXRISCV_CACHE cache_vexriscv.c)

arch/riscv/custom/vexriscv/Kconfig

@@ -1,9 +0,0 @@
-# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
-# SPDX-License-Identifier: Apache-2.0
-
-config RISCV_CUSTOM_CSR_VEXRISCV_CACHE
-	bool
-	default y
-	depends on ARCH_CACHE
-	help
-	  This option enables cache support for VexRiscv family of CPUs.

arch/riscv/custom/vexriscv/cache_vexriscv.c

@@ -1,122 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/cache.h>
-
-#ifdef CONFIG_DCACHE
-void arch_dcache_enable(void)
-{
-	/* Nothing */
-}
-
-void arch_dcache_disable(void)
-{
-	/* Nothing */
-}
-
-int arch_dcache_invd_all(void)
-{
-	/* Invalidate whole data cache instruction: 0x500F
-	 * https://github.com/SpinalHDL/VexRiscv?tab=readme-ov-file#dbuscachedplugin
-	 */
-	__asm__ volatile(".insn 0x500F\n");
-
-	return 0;
-}
-
-int arch_dcache_invd_range(void *addr, size_t size)
-{
-	/* Invalidate cache line instruction: 0x500f | (rs1 << 15)
-	 * https://github.com/SpinalHDL/VexRiscv?tab=readme-ov-file#dbuscachedplugin
-	 */
-	__asm__ volatile(
-		"mv a0, %1\n"
-		"j 2f\n"
-		"3:\n"
-		".insn 0x5500F\n" /* 0x500f | (a0 << 15) */
-		"add a0, a0, %0\n"
-		"2:\n"
-		"bltu a0, %2, 3b\n"
-		: : "r"(CONFIG_DCACHE_LINE_SIZE),
-			"r"((unsigned int)(addr) & ~((CONFIG_DCACHE_LINE_SIZE) - 1UL)),
-			"r"((unsigned int)(addr) + (size))
-		: "a0");
-
-	return 0;
-}
-
-
-int arch_dcache_flush_all(void)
-{
-	/* VexRiscv cache is write-through */
-	return 0;
-}
-
-int arch_dcache_flush_range(void *addr __unused, size_t size __unused)
-{
-	return 0;
-}
-
-int arch_dcache_flush_and_invd_all(void)
-{
-	return arch_dcache_invd_all();
-}
-
-int arch_dcache_flush_and_invd_range(void *addr, size_t size)
-{
-	return arch_dcache_invd_range(addr, size);
-}
-#endif /* CONFIG_DCACHE */
-
-#ifdef CONFIG_ICACHE
-void arch_icache_enable(void)
-{
-	/* Nothing */
-}
-
-void arch_icache_disable(void)
-{
-	/* Nothing */
-}
-
-int arch_icache_flush_all(void)
-{
-	__asm__ volatile("fence.i\n");
-
-	return 0;
-}
-
-int arch_icache_invd_all(void)
-{
-	return arch_icache_flush_all();
-}
-
-int arch_icache_invd_range(void *addr_in __unused, size_t size __unused)
-{
-	return arch_icache_flush_all();
-}
-
-int arch_icache_flush_and_invd_all(void)
-{
-	return arch_icache_flush_all();
-}
-
-int arch_icache_flush_range(void *addr __unused, size_t size __unused)
-{
-	return arch_icache_flush_all();
-}
-
-int arch_icache_flush_and_invd_range(void *addr __unused, size_t size __unused)
-{
-	return arch_icache_flush_all();
-}
-#endif /* CONFIG_ICACHE */
-
-void arch_cache_init(void)
-{
-	/* Nothing */
-}

arch/riscv/include/pmp.h

@@ -7,28 +7,14 @@
 #ifndef PMP_H_
 #define PMP_H_
 
-#include <zephyr/dt-bindings/memory-attr/memory-attr-riscv.h>
-
 #define PMPCFG_STRIDE (__riscv_xlen / 8)
 
-#define DT_MEM_RISCV_TO_PMP_PERM(dt_attr) (		\
-	(((dt_attr) & DT_MEM_RISCV_TYPE_IO_R) ? PMP_R : 0) |	\
-	(((dt_attr) & DT_MEM_RISCV_TYPE_IO_W) ? PMP_W : 0) |	\
-	(((dt_attr) & DT_MEM_RISCV_TYPE_IO_X) ? PMP_X : 0))
-
 void z_riscv_pmp_init(void);
-void z_riscv_pmp_kernelmode_prepare(struct k_thread *thread);
-void z_riscv_pmp_kernelmode_enable(struct k_thread *thread);
-void z_riscv_pmp_kernelmode_disable(void);
+void z_riscv_pmp_stackguard_prepare(struct k_thread *thread);
+void z_riscv_pmp_stackguard_enable(struct k_thread *thread);
+void z_riscv_pmp_stackguard_disable(void);
 void z_riscv_pmp_usermode_init(struct k_thread *thread);
 void z_riscv_pmp_usermode_prepare(struct k_thread *thread);
 void z_riscv_pmp_usermode_enable(struct k_thread *thread);
 
-#ifdef CONFIG_ZTEST
-void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size);
-void z_riscv_pmp_read_addr(unsigned long *pmp_addr, size_t pmp_addr_size);
-void pmp_decode_region(uint8_t cfg_byte, unsigned long *pmp_addr, unsigned int index,
-		       unsigned long *start, unsigned long *end);
-#endif /* CONFIG_ZTEST */
-
 #endif /* PMP_H_ */

arch/x86/gen_gdt.py

@@ -36,14 +36,16 @@ flat code/data segments for ring 3 execution.
 """
 
 import argparse
-import os
-import struct
 import sys
+import struct
+import os
+
+from packaging import version
 
 import elftools
 from elftools.elf.elffile import ELFFile
 from elftools.elf.sections import SymbolTableSection
-from packaging import version
+
 
 if version.parse(elftools.__version__) < version.parse('0.24'):
     sys.exit("pyelftools is out of date, need version 0.24 or later")
@@ -73,7 +75,7 @@ ACCESS_RW = 1 << 1  # read or write permission
 
 def create_gdt_pseudo_desc(addr, size):
     """Create pseudo GDT descriptor"""
-    debug(f"create pseudo descriptor: {addr:x} {size:x}")
+    debug("create pseudo descriptor: %x %x" % (addr, size))
     # ...and take back one byte for the Intel god whose Ark this is...
     size = size - 1
     return struct.pack(GDT_PD_FMT, size, addr, 0)
@@ -96,9 +98,11 @@ GDT_ENT_FMT = "<HHBBBB"
 
 def create_code_data_entry(base, limit, dpl, flags, access):
     """Create GDT entry for code or data"""
-    debug(f"create code or data entry: {base:x} {limit:x} {dpl:x} {flags:x} {access:x}")
+    debug("create code or data entry: %x %x %x %x %x" %
+          (base, limit, dpl, flags, access))
 
-    base_lo, base_mid, base_hi, limit_lo, limit_hi = chop_base_limit(base, limit)
+    base_lo, base_mid, base_hi, limit_lo, limit_hi = chop_base_limit(base,
+                                                                     limit)
 
     # This is a valid descriptor
     present = 1
@@ -117,21 +121,17 @@ def create_code_data_entry(base, limit, dpl, flags, access):
     access = access | (present << 7) | (dpl << 5) | (desc_type << 4) | accessed
     flags = flags | (size << 6) | limit_hi
 
-    return struct.pack(GDT_ENT_FMT, limit_lo, base_lo, base_mid, access, flags, base_hi)
+    return struct.pack(GDT_ENT_FMT, limit_lo, base_lo, base_mid,
+                       access, flags, base_hi)
 
 
 def create_tss_entry(base, limit, dpl):
     """Create GDT TSS entry"""
-    debug(f"create TSS entry: {base:x} {limit:x} {dpl:x}")
+    debug("create TSS entry: %x %x %x" % (base, limit, dpl))
     present = 1
 
-    (
-        base_lo,
-        base_mid,
-        base_hi,
-        limit_lo,
-        limit_hi,
-    ) = chop_base_limit(base, limit)
+    base_lo, base_mid, base_hi, limit_lo, limit_hi, = chop_base_limit(base,
+                                                                      limit)
 
     type_code = 0x9  # non-busy 32-bit TSS descriptor
     gran = 0
@@ -139,14 +139,16 @@ def create_tss_entry(base, limit, dpl):
     flags = (gran << 7) | limit_hi
     type_byte = (present << 7) | (dpl << 5) | type_code
 
-    return struct.pack(GDT_ENT_FMT, limit_lo, base_lo, base_mid, type_byte, flags, base_hi)
+    return struct.pack(GDT_ENT_FMT, limit_lo, base_lo, base_mid,
+                       type_byte, flags, base_hi)
 
 
 def get_symbols(obj):
     """Extract all symbols from ELF file object"""
     for section in obj.iter_sections():
         if isinstance(section, SymbolTableSection):
-            return {sym.name: sym.entry.st_value for sym in section.iter_symbols()}
+            return {sym.name: sym.entry.st_value
+                    for sym in section.iter_symbols()}
 
     raise LookupError("Could not find symbol table")
 
@@ -156,15 +158,14 @@ def parse_args():
     global args
     parser = argparse.ArgumentParser(
         description=__doc__,
-        formatter_class=argparse.RawDescriptionHelpFormatter,
-        allow_abbrev=False,
-    )
+        formatter_class=argparse.RawDescriptionHelpFormatter, allow_abbrev=False)
 
-    parser.add_argument("-k", "--kernel", required=True, help="Zephyr kernel image")
-    parser.add_argument(
-        "-v", "--verbose", action="store_true", help="Print extra debugging information"
-    )
-    parser.add_argument("-o", "--output-gdt", required=True, help="output GDT binary")
+    parser.add_argument("-k", "--kernel", required=True,
+                        help="Zephyr kernel image")
+    parser.add_argument("-v", "--verbose", action="store_true",
+                        help="Print extra debugging information")
+    parser.add_argument("-o", "--output-gdt", required=True,
+                        help="output GDT binary")
     args = parser.parse_args()
     if "VERBOSE" in os.environ:
         args.verbose = 1
@@ -204,10 +205,12 @@ def main():
         output_fp.write(create_gdt_pseudo_desc(gdt_base, num_entries * 8))
 
         # Selector 0x08: code descriptor
-        output_fp.write(create_code_data_entry(0, 0xFFFFF, 0, FLAGS_GRAN, ACCESS_EX | ACCESS_RW))
+        output_fp.write(create_code_data_entry(0, 0xFFFFF, 0,
+                                        FLAGS_GRAN, ACCESS_EX | ACCESS_RW))
 
         # Selector 0x10: data descriptor
-        output_fp.write(create_code_data_entry(0, 0xFFFFF, 0, FLAGS_GRAN, ACCESS_RW))
+        output_fp.write(create_code_data_entry(0, 0xFFFFF, 0,
+                                        FLAGS_GRAN, ACCESS_RW))
 
         if num_entries >= 5:
             main_tss = syms["_main_tss"]
@@ -221,12 +224,12 @@ def main():
 
         if num_entries >= 7:
             # Selector 0x28: code descriptor, dpl = 3
-            output_fp.write(
-                create_code_data_entry(0, 0xFFFFF, 3, FLAGS_GRAN, ACCESS_EX | ACCESS_RW)
-            )
+            output_fp.write(create_code_data_entry(0, 0xFFFFF, 3,
+                                            FLAGS_GRAN, ACCESS_EX | ACCESS_RW))
 
             # Selector 0x30: data descriptor, dpl = 3
-            output_fp.write(create_code_data_entry(0, 0xFFFFF, 3, FLAGS_GRAN, ACCESS_RW))
+            output_fp.write(create_code_data_entry(0, 0xFFFFF, 3,
+                                            FLAGS_GRAN, ACCESS_RW))
 
         if use_tls:
             # Selector 0x18, 0x28 or 0x38 (depending on entries above):
@@ -234,7 +237,8 @@ def main():
             #
             # for use with thread local storage while this will be
             # modified at runtime.
-            output_fp.write(create_code_data_entry(0, 0xFFFFF, 3, FLAGS_GRAN, ACCESS_RW))
+            output_fp.write(create_code_data_entry(0, 0xFFFFF, 3,
+                                            FLAGS_GRAN, ACCESS_RW))
 
 
 if __name__ == "__main__":

arch/x86/gen_idt.py

@@ -29,14 +29,13 @@ This script outputs three binary tables:
 """
 
 import argparse
-import os
-import struct
 import sys
-
+import struct
+import os
 import elftools
+from packaging import version
 from elftools.elf.elffile import ELFFile
 from elftools.elf.sections import SymbolTableSection
-from packaging import version
 
 if version.parse(elftools.__version__) < version.parse('0.24'):
     sys.exit("pyelftools is out of date, need version 0.24 or later")
@@ -70,7 +69,8 @@ def create_irq_gate(handler, dpl):
     offset_hi = handler >> 16
     offset_lo = handler & 0xFFFF
 
-    data = struct.pack(gate_desc_format, offset_lo, KERNEL_CODE_SEG, 0, type_attr, offset_hi)
+    data = struct.pack(gate_desc_format, offset_lo, KERNEL_CODE_SEG, 0,
+                       type_attr, offset_hi)
     return data
 
 
@@ -121,14 +121,15 @@ def update_irq_vec_map(irq_vec_map, irq, vector, max_irq):
         return
 
     if irq >= max_irq:
-        error(f"irq {irq:d} specified, but CONFIG_MAX_IRQ_LINES is {max_irq:d}")
+        error("irq %d specified, but CONFIG_MAX_IRQ_LINES is %d" %
+              (irq, max_irq))
 
     # This table will never have values less than 32 since those are for
     # exceptions; 0 means unconfigured
     if irq_vec_map[irq] != 0:
-        error(f"multiple vector assignments for interrupt line {irq:d}")
+        error("multiple vector assignments for interrupt line %d" % irq)
 
-    debug(f"assign IRQ {irq:d} to vector {vector:d}")
+    debug("assign IRQ %d to vector %d" % (irq, vector))
     irq_vec_map[irq] = vector
 
 
@@ -144,10 +145,11 @@ def setup_idt(spur_code, spur_nocode, intlist, max_vec, max_irq):
             continue
 
         if vec >= max_vec:
-            error(f"Vector {vec:d} specified, but size of IDT is only {max_vec:d} vectors")
+            error("Vector %d specified, but size of IDT is only %d vectors" %
+                  (vec, max_vec))
 
         if vectors[vec] is not None:
-            error(f"Multiple assignments for vector {vec:d}")
+            error("Multiple assignments for vector %d" % vec)
 
         vectors[vec] = (handler, tss, dpl)
         update_irq_vec_map(irq_vec_map, irq, vec, max_irq)
@@ -165,7 +167,7 @@ def setup_idt(spur_code, spur_nocode, intlist, max_vec, max_irq):
                 break
 
         if vec == -1:
-            error(f"can't find a free vector in priority level {prio:d}")
+            error("can't find a free vector in priority level %d" % prio)
 
         vectors[vec] = (handler, tss, dpl)
         update_irq_vec_map(irq_vec_map, irq, vec, max_irq)
@@ -188,27 +190,27 @@ def setup_idt(spur_code, spur_nocode, intlist, max_vec, max_irq):
 def get_symbols(obj):
     for section in obj.iter_sections():
         if isinstance(section, SymbolTableSection):
-            return {sym.name: sym.entry.st_value for sym in section.iter_symbols()}
+            return {sym.name: sym.entry.st_value
+                    for sym in section.iter_symbols()}
 
     raise LookupError("Could not find symbol table")
 
-
 # struct genidt_header_s {
-# uint32_t spurious_addr;
-# uint32_t spurious_no_error_addr;
-# int32_t num_entries;
+#	uint32_t spurious_addr;
+#	uint32_t spurious_no_error_addr;
+#	int32_t num_entries;
 # };
 
 
 intlist_header_fmt = "<II"
 
 # struct genidt_entry_s {
-# uint32_t isr;
-# int32_t irq;
-# int32_t priority;
-# int32_t vector_id;
-# int32_t dpl;
-# int32_t tss;
+#	uint32_t isr;
+#	int32_t irq;
+#	int32_t priority;
+#	int32_t vector_id;
+#	int32_t dpl;
+#	int32_t tss;
 # };
 
 intlist_entry_fmt = "<Iiiiii"
@@ -224,23 +226,23 @@ def get_intlist(elf):
     spurious_code = header[0]
     spurious_nocode = header[1]
 
-    debug(f"spurious handler (code)    : {hex(header[0]):s}")
-    debug(f"spurious handler (no code) : {hex(header[1]):s}")
+    debug("spurious handler (code)    : %s" % hex(header[0]))
+    debug("spurious handler (no code) : %s" % hex(header[1]))
 
-    intlist = [i for i in struct.iter_unpack(intlist_entry_fmt, intdata)]
+    intlist = [i for i in
+               struct.iter_unpack(intlist_entry_fmt, intdata)]
 
     debug("Configured interrupt routing")
     debug("handler    irq pri vec dpl")
     debug("--------------------------")
 
     for irq in intlist:
-        debug(
-            f"{hex(irq[0]):<10} "
-            f"{'-' if irq[1] == -1 else irq[1]:<3} "
-            f"{'-' if irq[2] == -1 else irq[2]:<3} "
-            f"{'-' if irq[3] == -1 else irq[3]:<3} "
-            f"{irq[4]:<2}"
-        )
+        debug("{0:<10} {1:<3} {2:<3} {3:<3} {4:<2}".format(
+            hex(irq[0]),
+            "-" if irq[1] == -1 else irq[1],
+            "-" if irq[2] == -1 else irq[2],
+            "-" if irq[3] == -1 else irq[3],
+            irq[4]))
 
     return (spurious_code, spurious_nocode, intlist)
 
@@ -249,26 +251,18 @@ def parse_args():
     global args
     parser = argparse.ArgumentParser(
         description=__doc__,
-        formatter_class=argparse.RawDescriptionHelpFormatter,
-        allow_abbrev=False,
-    )
+        formatter_class=argparse.RawDescriptionHelpFormatter, allow_abbrev=False)
 
-    parser.add_argument(
-        "-m", "--vector-map", required=True, help="Output file mapping IRQ lines to IDT vectors"
-    )
-    parser.add_argument(
-        "-o", "--output-idt", required=True, help="Output file containing IDT binary"
-    )
-    parser.add_argument(
-        "-a",
-        "--output-vectors-alloc",
-        required=False,
-        help="Output file indicating allocated vectors",
-    )
-    parser.add_argument("-k", "--kernel", required=True, help="Zephyr kernel image")
-    parser.add_argument(
-        "-v", "--verbose", action="store_true", help="Print extra debugging information"
-    )
+    parser.add_argument("-m", "--vector-map", required=True,
+                        help="Output file mapping IRQ lines to IDT vectors")
+    parser.add_argument("-o", "--output-idt", required=True,
+                        help="Output file containing IDT binary")
+    parser.add_argument("-a", "--output-vectors-alloc", required=False,
+                        help="Output file indicating allocated vectors")
+    parser.add_argument("-k", "--kernel", required=True,
+                        help="Zephyr kernel image")
+    parser.add_argument("-v", "--verbose", action="store_true",
+                        help="Print extra debugging information")
     args = parser.parse_args()
     if "VERBOSE" in os.environ:
         args.verbose = 1
@@ -280,7 +274,7 @@ def create_irq_vectors_allocated(vectors, spur_code, spur_nocode, filename):
     # interrupt handlers installed, they are free for runtime installation
     # of interrupts
     num_chars = (len(vectors) + 7) // 8
-    vbits = num_chars * [0]
+    vbits = num_chars*[0]
     for i, (handler, _, _) in enumerate(vectors):
         if handler not in (spur_code, spur_nocode):
             continue
@@ -306,12 +300,14 @@ def main():
     max_irq = syms["CONFIG_MAX_IRQ_LINES"]
     max_vec = syms["CONFIG_IDT_NUM_VECTORS"]
 
-    vectors, irq_vec_map = setup_idt(spur_code, spur_nocode, intlist, max_vec, max_irq)
+    vectors, irq_vec_map = setup_idt(spur_code, spur_nocode, intlist, max_vec,
+                                     max_irq)
 
     create_idt_binary(vectors, args.output_idt)
     create_irq_vec_map_binary(irq_vec_map, args.vector_map)
     if args.output_vectors_alloc:
-        create_irq_vectors_allocated(vectors, spur_code, spur_nocode, args.output_vectors_alloc)
+        create_irq_vectors_allocated(vectors, spur_code, spur_nocode,
+                                     args.output_vectors_alloc)
 
 
 if __name__ == "__main__":

arch/x86/gen_mmu.py

@@ -65,19 +65,20 @@ to the end of the binary produced by this script, minus the size of the
 top-level paging structure as it is written out last.
 """
 
-import argparse
+import sys
 import array
+import argparse
 import ctypes
 import os
-import re
 import struct
-import sys
+import re
 import textwrap
 
+from packaging import version
+
 import elftools
 from elftools.elf.elffile import ELFFile
 from elftools.elf.sections import SymbolTableSection
-from packaging import version
 
 if version.parse(elftools.__version__) < version.parse('0.24'):
     sys.exit("pyelftools is out of date, need version 0.24 or later")
@@ -133,9 +134,9 @@ def error(text):
 def align_check(base, size, scope=4096):
     """Make sure base and size are page-aligned"""
     if (base % scope) != 0:
-        error(f"unaligned base address {base:x}")
+        error("unaligned base address %x" % base)
     if (size % scope) != 0:
-        error(f"Unaligned region size 0x{size:x} for base {base:x}")
+        error("Unaligned region size 0x%x for base %x" % (size, base))
 
 
 def dump_flags(flags):
@@ -183,12 +184,12 @@ def round_down(val, align):
 # access or set caching properties at leaf levels.
 INT_FLAGS = FLAG_P | FLAG_RW | FLAG_US
 
-
-class MMUTable:
+class MMUTable():
     """Represents a particular table in a set of page tables, at any level"""
 
     def __init__(self):
-        self.entries = array.array(self.type_code, [0 for i in range(self.num_entries)])
+        self.entries = array.array(self.type_code,
+                                   [0 for i in range(self.num_entries)])
 
     def get_binary(self):
         """Return a bytearray representation of this table"""
@@ -260,110 +261,82 @@ class MMUTable:
         this is the physical address of the next level table"""
         index = self.entry_index(virt_addr)
 
-        verbose(
-            f"{self.__class__.__name__:s}: "
-            f"mapping 0x{phys_addr:x} to 0x{virt_addr:x} : "
-            f"{dump_flags(entry_flags):s}"
-        )
+        verbose("%s: mapping 0x%x to 0x%x : %s" %
+                (self.__class__.__name__,
+                 phys_addr, virt_addr, dump_flags(entry_flags)))
 
-        self.entries[index] = (phys_addr & self.addr_mask) | (entry_flags & self.supported_flags)
+        self.entries[index] = ((phys_addr & self.addr_mask) |
+                               (entry_flags & self.supported_flags))
 
     def set_perms(self, virt_addr, entry_flags):
-        """For the table entry corresponding to the provided virtual address,
+        """"For the table entry corresponding to the provided virtual address,
         update just the flags, leaving the physical mapping alone.
         Unsupported flags will be filtered out."""
         index = self.entry_index(virt_addr)
 
-        verbose(
-            f"{self.__class__.__name__:s}: "
-            f"changing perm at 0x{virt_addr:x} : "
-            f"{dump_flags(entry_flags):s}"
-        )
+        verbose("%s: changing perm at 0x%x : %s" %
+                (self.__class__.__name__,
+                 virt_addr, dump_flags(entry_flags)))
 
-        self.entries[index] = (self.entries[index] & self.addr_mask) | (
-            entry_flags & self.supported_flags
-        )
+        self.entries[index] = ((self.entries[index] & self.addr_mask) |
+                               (entry_flags & self.supported_flags))
 
 
 # Specific supported table types
 class Pml4(MMUTable):
     """Page mapping level 4 for IA-32e"""
-
     addr_shift = 39
     addr_mask = 0x7FFFFFFFFFFFF000
     type_code = 'Q'
     num_entries = 512
     supported_flags = INT_FLAGS
 
-
 class Pdpt(MMUTable):
     """Page directory pointer table for IA-32e"""
-
     addr_shift = 30
     addr_mask = 0x7FFFFFFFFFFFF000
     type_code = 'Q'
     num_entries = 512
     supported_flags = INT_FLAGS | FLAG_SZ | FLAG_CD
 
-
 class PdptPAE(Pdpt):
     """Page directory pointer table for PAE"""
-
     num_entries = 4
 
-
 class Pd(MMUTable):
     """Page directory for 32-bit"""
-
     addr_shift = 22
     addr_mask = 0xFFFFF000
     type_code = 'I'
     num_entries = 1024
     supported_flags = INT_FLAGS | FLAG_SZ | FLAG_CD
 
-
 class PdXd(Pd):
     """Page directory for either PAE or IA-32e"""
-
     addr_shift = 21
     addr_mask = 0x7FFFFFFFFFFFF000
     num_entries = 512
     type_code = 'Q'
 
-
 class Pt(MMUTable):
     """Page table for 32-bit"""
-
     addr_shift = 12
     addr_mask = 0xFFFFF000
     type_code = 'I'
     num_entries = 1024
-    supported_flags = (
-        FLAG_P | FLAG_RW | FLAG_US | FLAG_G | FLAG_CD | FLAG_D | FLAG_IGNORED0 | FLAG_IGNORED1
-    )
-
+    supported_flags = (FLAG_P | FLAG_RW | FLAG_US | FLAG_G | FLAG_CD | FLAG_D |
+                       FLAG_IGNORED0 | FLAG_IGNORED1)
 
 class PtXd(Pt):
     """Page table for either PAE or IA-32e"""
-
     addr_mask = 0x07FFFFFFFFFFF000
     type_code = 'Q'
     num_entries = 512
-    supported_flags = (
-        FLAG_P
-        | FLAG_RW
-        | FLAG_US
-        | FLAG_G
-        | FLAG_XD
-        | FLAG_CD
-        | FLAG_D
-        | FLAG_IGNORED0
-        | FLAG_IGNORED1
-        | FLAG_IGNORED2
-    )
+    supported_flags = (FLAG_P | FLAG_RW | FLAG_US | FLAG_G | FLAG_XD | FLAG_CD |
+                       FLAG_D | FLAG_IGNORED0 | FLAG_IGNORED1 | FLAG_IGNORED2)
 
 
-class PtableSet:
+class PtableSet():
     """Represents a complete set of page tables for any paging mode"""
 
     def __init__(self, pages_start):
@@ -372,7 +345,8 @@ class PtableSet:
         self.toplevel = self.levels[0]()
         self.page_pos = pages_start
 
-        debug(f"{self.__class__.__name__:s} starting at physical address 0x{self.page_pos:x}")
+        debug("%s starting at physical address 0x%x" %
+              (self.__class__.__name__, self.page_pos))
 
         # Database of page table pages. Maps physical memory address to
         # MMUTable objects, excluding the top-level table which is tracked
@@ -434,7 +408,8 @@ class PtableSet:
         """Create a new child table"""
         new_table_addr = self.get_new_mmutable_addr()
         new_table = self.levels[depth]()
-        debug(f"new {self.levels[depth].__name__:s} at physical addr 0x{new_table_addr:x}")
+        debug("new %s at physical addr 0x%x"
+                      % (self.levels[depth].__name__, new_table_addr))
         self.tables[new_table_addr] = new_table
         table.map(virt_addr, new_table_addr, INT_FLAGS)
 
@@ -461,7 +436,8 @@ class PtableSet:
 
     def reserve(self, virt_base, size, to_level=PT_LEVEL):
         """Reserve page table space with already aligned virt_base and size"""
-        debug(f"Reserving paging structures for 0x{virt_base:x} (0x{size:x})")
+        debug("Reserving paging structures for 0x%x (0x%x)" %
+              (virt_base, size))
 
         align_check(virt_base, size)
 
@@ -469,9 +445,8 @@ class PtableSet:
         scope = 1 << self.levels[PD_LEVEL].addr_shift
 
         if virt_base % scope != 0:
-            error(
-                f"misaligned virtual address space, 0x{virt_base:x} not a multiple of 0x{scope:x}"
-            )
+            error("misaligned virtual address space, 0x%x not a multiple of 0x%x" %
+                  (virt_base, scope))
 
         for addr in range(virt_base, virt_base + size, scope):
             self.map_page(addr, 0, 0, True, to_level)
@@ -498,7 +473,8 @@ class PtableSet:
 
         scope = 1 << self.levels[level].addr_shift
 
-        debug(f"Mapping 0x{phys_base:x} (0x{size:x}) to 0x{virt_base:x}: {dump_flags(flags):s}")
+        debug("Mapping 0x%x (0x%x) to 0x%x: %s" %
+                (phys_base, size, virt_base, dump_flags(flags)))
 
         align_check(phys_base, size, scope)
         align_check(virt_base, size, scope)
@@ -561,7 +537,8 @@ class PtableSet:
         if size == 0:
             return
 
-        debug(f"change flags for {name:s} at 0x{base:x} (0x{size:x}): {dump_flags(flags):s}")
+        debug("change flags for %s at 0x%x (0x%x): %s" %
+              (name, base, size, dump_flags(flags)))
 
         num_levels = len(self.levels) + level + 1
         scope = 1 << self.levels[level].addr_shift
@@ -579,7 +556,8 @@ class PtableSet:
                     table = self.tables[table.lookup(addr)]
                 table.set_perms(addr, flags)
         except KeyError:
-            error(f"no mapping for {name:s} region 0x{base:x} (size 0x{size:x})")
+            error("no mapping for %s region 0x%x (size 0x%x)" %
+                  (name, base, size))
 
     def write_output(self, filename):
         """Write the page tables to the output file in binary format"""
@@ -596,33 +574,26 @@ class PtableSet:
             # in PAE, the top-level PDPT has only 4 entries and is not a
             # full page in size. We do not put it in the tables dictionary
             # and treat it as a special case.
-            debug(
-                f"top-level {self.toplevel.__class__.__name__:s} at "
-                f"physical addr 0x{self.get_new_mmutable_addr():x}"
-            )
+            debug("top-level %s at physical addr 0x%x" %
+                  (self.toplevel.__class__.__name__,
+                   self.get_new_mmutable_addr()))
             top_level_bin = self.toplevel.get_binary()
             output_fp.write(top_level_bin)
             written_size += len(top_level_bin)
 
         return written_size
 
-
 # Paging mode classes, we'll use one depending on configuration
 class Ptables32bit(PtableSet):
     """32-bit Page Tables"""
-
     levels = [Pd, Pt]
 
-
 class PtablesPAE(PtableSet):
     """PAE Page Tables"""
-
     levels = [PdptPAE, PdXd, PtXd]
 
-
 class PtablesIA32e(PtableSet):
     """Page Tables under IA32e mode"""
-
     levels = [Pml4, Pdpt, PdXd, PtXd]
 
 
@@ -632,16 +603,14 @@ def parse_args():
 
     parser = argparse.ArgumentParser(
         description=__doc__,
-        formatter_class=argparse.RawDescriptionHelpFormatter,
-        allow_abbrev=False,
-    )
+        formatter_class=argparse.RawDescriptionHelpFormatter, allow_abbrev=False)
 
-    parser.add_argument("-k", "--kernel", required=True, help="path to prebuilt kernel ELF binary")
-    parser.add_argument("-o", "--output", required=True, help="output file")
-    parser.add_argument(
-        "--map",
-        action='append',
-        help=textwrap.dedent('''\
+    parser.add_argument("-k", "--kernel", required=True,
+                        help="path to prebuilt kernel ELF binary")
+    parser.add_argument("-o", "--output", required=True,
+                        help="output file")
+    parser.add_argument("--map", action='append',
+                        help=textwrap.dedent('''\
                             Map extra memory:
                             <physical address>,<size>[,<flags:LUWXD>[,<virtual address>]]
                             where flags can be empty or combination of:
@@ -655,9 +624,9 @@ def parse_args():
                                 supervisor only,
                                 read only,
                                 and execution disabled.
-                            '''),
-    )
-    parser.add_argument("-v", "--verbose", action="count", help="Print extra debugging information")
+                            '''))
+    parser.add_argument("-v", "--verbose", action="count",
+                        help="Print extra debugging information")
     args = parser.parse_args()
     if "VERBOSE" in os.environ:
         args.verbose = 1
@@ -667,11 +636,11 @@ def get_symbols(elf_obj):
     """Get all symbols from the ELF file"""
     for section in elf_obj.iter_sections():
         if isinstance(section, SymbolTableSection):
-            return {sym.name: sym.entry.st_value for sym in section.iter_symbols()}
+            return {sym.name: sym.entry.st_value
+                    for sym in section.iter_symbols()}
 
     raise LookupError("Could not find symbol table")
 
-
 def isdef(sym_name):
     """True if symbol is defined in ELF file"""
     return sym_name in syms
@@ -697,13 +666,13 @@ def map_extra_regions(pt):
         elements = entry.split(',')
 
         if len(elements) < 2:
-            error(f"Not enough arguments for --map {entry:s}")
+            error("Not enough arguments for --map %s" % entry)
 
         one_map = {}
 
         one_map['cmdline'] = entry
         one_map['phys'] = int(elements[0], 0)
-        one_map['size'] = int(elements[1], 0)
+        one_map['size']= int(elements[1], 0)
         one_map['large_page'] = False
 
         flags = FLAG_P | ENTRY_XD
@@ -712,7 +681,7 @@ def map_extra_regions(pt):
 
             # Check for allowed flags
             if not bool(re.match('^[LUWXD]*$', map_flags)):
-                error(f"Unrecognized flags: {map_flags:s}")
+                error("Unrecognized flags: %s" % map_flags)
 
             flags = FLAG_P | ENTRY_XD
             if 'W' in map_flags:
@@ -722,7 +691,7 @@ def map_extra_regions(pt):
             if 'U' in map_flags:
                 flags |= ENTRY_US
             if 'L' in map_flags:
-                flags |= FLAG_SZ
+                flags |=  FLAG_SZ
                 one_map['large_page'] = True
             if 'D' in map_flags:
                 flags |= FLAG_CD
@@ -747,9 +716,8 @@ def map_extra_regions(pt):
         # Check if addresses have already been mapped.
         # Error out if so as they could override kernel mappings.
         if pt.is_region_mapped(virt, size, level):
-            error(
-                f"Region 0x{virt:x} ({size:d}) already been mapped for --map {one_map['cmdline']:x}"
-            )
+            error(("Region 0x%x (%d) already been mapped "
+                   "for --map %s" % (virt, size, one_map['cmdline'])))
 
         # Reserve space in page table, and map the region
         pt.reserve_unaligned(virt, size, level)
@@ -778,7 +746,7 @@ def main():
     else:
         pclass = Ptables32bit
 
-    debug(f"building {pclass.__name__:s}")
+    debug("building %s" % pclass.__name__)
 
     vm_base = syms["CONFIG_KERNEL_VM_BASE"]
     vm_size = syms["CONFIG_KERNEL_VM_SIZE"]
@@ -810,17 +778,15 @@ def main():
 
     ptables_phys = syms["z_x86_pagetables_start"] + virt_to_phys_offset
 
-    debug(f"Address space: 0x{vm_base:x} - 0x{vm_base + vm_size - 1:x} size 0x{vm_size:x}")
+    debug("Address space: 0x%x - 0x%x size 0x%x" %
+          (vm_base, vm_base + vm_size - 1, vm_size))
 
-    debug(
-        f"Zephyr image: 0x{image_base:x} - 0x{image_base + image_size - 1:x} size 0x{image_size:x}"
-    )
+    debug("Zephyr image: 0x%x - 0x%x size 0x%x" %
+          (image_base, image_base + image_size - 1, image_size))
 
     if virt_to_phys_offset != 0:
-        debug(
-            f"Physical address space: 0x{sram_base:x} - 0x{sram_base + sram_size - 1:x} "
-            f"size 0x{sram_size:x}"
-        )
+        debug("Physical address space: 0x%x - 0x%x size 0x%x" %
+              (sram_base, sram_base + sram_size - 1, sram_size))
 
     is_perm_regions = isdef("CONFIG_SRAM_REGION_PERMISSIONS")
 
@@ -828,7 +794,7 @@ def main():
     is_generic_section_present = isdef("CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT")
 
     if image_size >= vm_size:
-        error(f"VM size is too small (have 0x{vm_size:x} need more than 0x{image_size:x})")
+        error("VM size is too small (have 0x%x need more than 0x%x)" % (vm_size, image_size))
 
     map_flags = 0
 
@@ -861,26 +827,22 @@ def main():
         # Note that this only does the identity mapping
         # at the page directory level to minimize wasted space.
         pt.reserve_unaligned(image_base_phys, image_size, to_level=PD_LEVEL)
-        pt.identity_map_unaligned(
-            image_base_phys, image_size, FLAG_P | FLAG_RW | FLAG_SZ, level=PD_LEVEL
-        )
+        pt.identity_map_unaligned(image_base_phys, image_size,
+                                  FLAG_P | FLAG_RW | FLAG_SZ, level=PD_LEVEL)
 
     if isdef("CONFIG_X86_64"):
         # 64-bit has a special region in the first 64K to bootstrap other CPUs
         # from real mode
         locore_base = syms["_locore_start"]
         locore_size = syms["_lodata_end"] - locore_base
-        debug(f"Base addresses: physical 0x{locore_base:x} size 0x{locore_size:x}")
+        debug("Base addresses: physical 0x%x size 0x%x" % (locore_base,
+                                                         locore_size))
         pt.map(locore_base, None, locore_size, map_flags | FLAG_P | ENTRY_RW)
 
     if isdef("CONFIG_XIP"):
         # Additionally identity-map all ROM as read-only
-        pt.map(
-            syms["CONFIG_FLASH_BASE_ADDRESS"],
-            None,
-            syms["CONFIG_FLASH_SIZE"] * 1024,
-            map_flags | FLAG_P,
-        )
+        pt.map(syms["CONFIG_FLASH_BASE_ADDRESS"], None,
+               syms["CONFIG_FLASH_SIZE"] * 1024, map_flags | FLAG_P)
 
     if isdef("CONFIG_LINKER_USE_BOOT_SECTION"):
         pt.map_region("lnkr_boot", map_flags | FLAG_P | ENTRY_RW, virt_to_phys_offset)
@@ -931,7 +893,8 @@ def main():
         if isdef("CONFIG_COVERAGE_GCOV") and isdef("CONFIG_USERSPACE"):
             # If GCOV is enabled, user mode must be able to write to its
             # common data area
-            pt.set_region_perms("__gcov_bss", FLAG_P | ENTRY_RW | ENTRY_US | ENTRY_XD)
+            pt.set_region_perms("__gcov_bss",
+                                FLAG_P | ENTRY_RW | ENTRY_US | ENTRY_XD)
 
         if isdef("CONFIG_X86_64"):
             # Set appropriate permissions for locore areas much like we did
@@ -954,7 +917,7 @@ def main():
             pt.set_region_perms("__x86shadowstack", FLAG_P | FLAG_D | ENTRY_XD)
 
     written_size = pt.write_output(args.output)
-    debug(f"Written {written_size:d} bytes to {args.output:s}")
+    debug("Written %d bytes to %s" % (written_size, args.output))
 
     # Warn if reserved page table is not of correct size
     if reserved_pt_size and written_size != reserved_pt_size:
@@ -972,10 +935,9 @@ def main():
 
         reason = "big" if reserved_pt_size > written_size else "small"
 
-        error(
-            f"Reserved space for page table is too {reason:s}."
-            f" Set CONFIG_X86_EXTRA_PAGE_TABLE_PAGES={extra_pages_needed:d}"
-        )
+        error(("Reserved space for page table is too %s."
+               " Set CONFIG_X86_EXTRA_PAGE_TABLE_PAGES=%d") %
+               (reason, extra_pages_needed))
 
 
 if __name__ == "__main__":

arch/x86/include/ia32/kernel_arch_data.h

@@ -11,8 +11,8 @@
  * This file contains private kernel structures definitions and various
  * other definitions for the Intel Architecture 32 bit (IA-32) processor
  * architecture.
- * The header include/zephyr/kernel.h contains the public kernel interface
- * definitions, with include/zephyr/arch/x86/ia32/arch.h supplying the
+ * The header include/kernel.h contains the public kernel interface
+ * definitions, with include/arch/x86/ia32/arch.h supplying the
  * IA-32 specific portions of the public kernel interface.
  *
  * This file is also included by assembly language files which must #define

arch/xtensa/Kconfig

@@ -44,6 +44,32 @@ config XTENSA_SMALL_VECTOR_TABLE_ENTRY
 	  handlers to the end of vector table, renaming them to
 	  _Level\LVL\()VectorHelper.
 
+config XTENSA_RPO_CACHE
+	bool "Cached/uncached RPO mapping"
+	help
+	  Support Cached/uncached RPO mapping.
+
+	  A design trick on multi-core hardware is to map memory twice
+	  so that it can be seen in both (incoherent) cached mappings
+	  and a coherent "shared" area.
+
+if XTENSA_RPO_CACHE
+config XTENSA_CACHED_REGION
+	int "Cached RPO mapping"
+	range 0 7
+	help
+	  This specifies which 512M region (0-7, as defined by the Xtensa
+	  Region Protection Option) contains the "cached" mapping.
+
+config XTENSA_UNCACHED_REGION
+	int "Uncached RPO mapping"
+	range 0 7
+	help
+	  As for XTENSA_CACHED_REGION, this specifies which 512M
+	  region (0-7) contains the "uncached" mapping.
+
+endif
+
 config XTENSA_CCOUNT_HZ
 	int "CCOUNT cycle rate"
 	default 1000000
@@ -168,27 +194,13 @@ config XTENSA_MMU
 	bool "Xtensa MMU Support"
 	select MMU
 	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
+	select KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK if XTENSA_RPO_CACHE
 	select CURRENT_THREAD_USE_NO_TLS if USERSPACE
 	help
 	  Enable support for Xtensa Memory Management Unit.
 
 if XTENSA_MMU
 
-config XTENSA_MMU_USE_DEFAULT_MAPPINGS
-	bool "Use architecture default MMU mappings"
-	default y
-	help
-	  If enabled, the MMU will be initialized with a few default
-	  MMU mappings covering text, data, BSS, rodata, etc. which
-	  should provide a reasonable default. See mmu_zephyr_ranges[]
-	  for details.
-
-	  If disabled, the SoC must provide all the necessary mappings
-	  via xtensa_soc_mmu_ranges[]. This allows SoC to have more
-	  fine control over the mappings.
-
-	  If unsure, just say Y.
-
 choice
 	prompt "PageTable virtual address"
 	default XTENSA_MMU_PTEVADDR_20000000
@@ -229,6 +241,12 @@ config XTENSA_MMU_NUM_L2_TABLES
 	help
 	  Each table can address up to 4MB memory address.
 
+config XTENSA_MMU_DOUBLE_MAP
+	bool "Map memory in cached and uncached region"
+	help
+	  This option specifies that the memory is mapped in two
+	  distinct region, cached and uncached.
+
 config PRIVILEGED_STACK_SIZE
 	# Must be multiple of CONFIG_MMU_PAGE_SIZE
 	default 4096
@@ -240,12 +258,6 @@ config XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP
 	  This flushes (invalidates) all auto-refill data TLBs when page
 	  tables are swapped.
 
-config XTENSA_MMU_PAGE_TABLE_STATS
-	bool "Page table statistics"
-	help
-	  Enable this for page table statistics, including current usage and
-	  maximum number of page tables used.
-
 endif # XTENSA_MMU
 
 endif # CPU_HAS_MMU

arch/xtensa/core/crt1.S

@@ -30,9 +30,19 @@
 #if __XTENSA_CALL0_ABI__
 # define CALL	call0
 # define CALLX	callx0
+# define ARG1	a2	/* 1st outgoing call argument */
+# define ARG2	a3	/* 2nd outgoing call argument */
+# define ARG3	a4	/* 3rd outgoing call argument */
+# define ARG4	a5	/* 4th outgoing call argument */
+# define ARG5	a6	/* 5th outgoing call argument */
 #else
 # define CALL	call4
 # define CALLX	callx4
+# define ARG1	a6	/* 1st outgoing call argument */
+# define ARG2	a7	/* 2nd outgoing call argument */
+# define ARG3	a8	/* 3rd outgoing call argument */
+# define ARG4	a9	/* 4th outgoing call argument */
+# define ARG5	a10	/* 5th outgoing call argument */
 #endif
 
 	.text

arch/xtensa/core/prep_c.c

@@ -85,9 +85,6 @@ FUNC_NORETURN void z_prep_c(void)
 #if CONFIG_ARCH_CACHE
 	arch_cache_init();
 #endif
-#if CONFIG_SOC_CACHE
-	soc_cache_init();
-#endif
 
 #ifdef CONFIG_XTENSA_MMU
 	xtensa_mmu_init();

arch/xtensa/include/xtensa_mmu_priv.h

@@ -28,6 +28,12 @@
 /** Mask for PPN in PTE */
 #define XTENSA_MMU_PTE_PPN_MASK			0xFFFFF000U
 
+/** Mask for attributes in PTE */
+#define XTENSA_MMU_PTE_ATTR_MASK		0x0000000FU
+
+/** Mask for cache mode in PTE */
+#define XTENSA_MMU_PTE_ATTR_CACHED_MASK		0x0000000CU
+
 /** Mask used to figure out which L1 page table to use */
 #define XTENSA_MMU_L1_MASK			0x3FF00000U
 
@@ -39,6 +45,96 @@
 /** Number of bits to shift for PPN in PTE */
 #define XTENSA_MMU_PTE_PPN_SHIFT		12U
 
+/** Mask for ring in PTE */
+#define XTENSA_MMU_PTE_RING_MASK		0x00000030U
+
+/** Number of bits to shift for ring in PTE */
+#define XTENSA_MMU_PTE_RING_SHIFT		4U
+
+/** Number of bits to shift for SW reserved ared in PTE */
+#define XTENSA_MMU_PTE_SW_SHIFT			6U
+
+/** Mask for SW bits in PTE */
+#define XTENSA_MMU_PTE_SW_MASK			0x00000FC0U
+
+/**
+ * Number of bits to shift for backup attributes in PTE SW field.
+ *
+ * This is relative to the SW field, not the PTE entry.
+ */
+#define XTENSA_MMU_PTE_SW_ATTR_SHIFT		0U
+
+/**
+ * Mask for backup attributes in PTE SW field.
+ *
+ * This is relative to the SW field, not the PTE entry.
+ */
+#define XTENSA_MMU_PTE_SW_ATTR_MASK		0x0000000FU
+
+/**
+ * Number of bits to shift for backup ring value in PTE SW field.
+ *
+ * This is relative to the SW field, not the PTE entry.
+ */
+#define XTENSA_MMU_PTE_SW_RING_SHIFT		4U
+
+/**
+ * Mask for backup ring value in PTE SW field.
+ *
+ * This is relative to the SW field, not the PTE entry.
+ */
+#define XTENSA_MMU_PTE_SW_RING_MASK		0x00000030U
+
+/** Construct a page table entry (PTE) */
+#define XTENSA_MMU_PTE(paddr, ring, sw, attr) \
+	(((paddr) & XTENSA_MMU_PTE_PPN_MASK) | \
+	 (((ring) << XTENSA_MMU_PTE_RING_SHIFT) & XTENSA_MMU_PTE_RING_MASK) | \
+	 (((sw) << XTENSA_MMU_PTE_SW_SHIFT) & XTENSA_MMU_PTE_SW_MASK) | \
+	 ((attr) & XTENSA_MMU_PTE_ATTR_MASK))
+
+/** Get the attributes from a PTE */
+#define XTENSA_MMU_PTE_ATTR_GET(pte) \
+	((pte) & XTENSA_MMU_PTE_ATTR_MASK)
+
+/** Set the attributes in a PTE */
+#define XTENSA_MMU_PTE_ATTR_SET(pte, attr) \
+	(((pte) & ~XTENSA_MMU_PTE_ATTR_MASK) | (attr & XTENSA_MMU_PTE_ATTR_MASK))
+
+/** Set the SW field in a PTE */
+#define XTENSA_MMU_PTE_SW_SET(pte, sw) \
+	(((pte) & ~XTENSA_MMU_PTE_SW_MASK) | (sw << XTENSA_MMU_PTE_SW_SHIFT))
+
+/** Get the SW field from a PTE */
+#define XTENSA_MMU_PTE_SW_GET(pte) \
+	(((pte) & XTENSA_MMU_PTE_SW_MASK) >> XTENSA_MMU_PTE_SW_SHIFT)
+
+/** Construct a PTE SW field to be used for backing up PTE ring and attributes. */
+#define XTENSA_MMU_PTE_SW(ring, attr) \
+	((((ring) << XTENSA_MMU_PTE_SW_RING_SHIFT) & XTENSA_MMU_PTE_SW_RING_MASK) | \
+	 (((attr) << XTENSA_MMU_PTE_SW_ATTR_SHIFT) & XTENSA_MMU_PTE_SW_ATTR_MASK))
+
+/** Get the backed up attributes from the PTE SW field. */
+#define XTENSA_MMU_PTE_SW_ATTR_GET(sw) \
+	(((sw) & XTENSA_MMU_PTE_SW_ATTR_MASK) >> XTENSA_MMU_PTE_SW_ATTR_SHIFT)
+
+/** Get the backed up ring value from the PTE SW field. */
+#define XTENSA_MMU_PTE_SW_RING_GET(sw) \
+	(((sw) & XTENSA_MMU_PTE_SW_RING_MASK) >> XTENSA_MMU_PTE_SW_RING_SHIFT)
+
+/** Set the ring in a PTE */
+#define XTENSA_MMU_PTE_RING_SET(pte, ring) \
+	(((pte) & ~XTENSA_MMU_PTE_RING_MASK) | \
+	((ring) << XTENSA_MMU_PTE_RING_SHIFT))
+
+/** Get the ring from a PTE */
+#define XTENSA_MMU_PTE_RING_GET(pte) \
+	(((pte) & XTENSA_MMU_PTE_RING_MASK) >> XTENSA_MMU_PTE_RING_SHIFT)
+
+/** Get the ASID from the RASID register corresponding to the ring in a PTE */
+#define XTENSA_MMU_PTE_ASID_GET(pte, rasid) \
+	(((rasid) >> ((((pte) & XTENSA_MMU_PTE_RING_MASK) \
+		       >> XTENSA_MMU_PTE_RING_SHIFT) * 8)) & 0xFF)
+
 /** Calculate the L2 page table position from a virtual address */
 #define XTENSA_MMU_L2_POS(vaddr) \
 	(((vaddr) & XTENSA_MMU_L2_MASK) >> 12U)
@@ -68,6 +164,15 @@
 /** Fixed data TLB way to map the vecbase */
 #define XTENSA_MMU_VECBASE_WAY			8
 
+/** Kernel specific ASID. Ring field in the PTE */
+#define XTENSA_MMU_KERNEL_RING			0
+
+/** User specific ASID. Ring field in the PTE */
+#define XTENSA_MMU_USER_RING			2
+
+/** Ring value for MMU_SHARED_ASID */
+#define XTENSA_MMU_SHARED_RING			3
+
 /** Number of data TLB ways [0-9] */
 #define XTENSA_MMU_NUM_DTLB_WAYS		10
 
@@ -77,6 +182,19 @@
 /** Number of auto-refill ways */
 #define XTENSA_MMU_NUM_TLB_AUTOREFILL_WAYS	4
 
+/** Attribute indicating PTE is illegal. */
+#define XTENSA_MMU_PTE_ATTR_ILLEGAL		(BIT(3) | BIT(2))
+
+/** Illegal PTE entry for Level 1 page tables */
+#define XTENSA_MMU_PTE_L1_ILLEGAL		XTENSA_MMU_PTE_ATTR_ILLEGAL
+
+/** Illegal PTE entry for Level 2 page tables */
+#define XTENSA_MMU_PTE_L2_ILLEGAL \
+	XTENSA_MMU_PTE(0, XTENSA_MMU_KERNEL_RING, \
+		       XTENSA_MMU_PTE_SW(XTENSA_MMU_KERNEL_RING, \
+					 XTENSA_MMU_PTE_ATTR_ILLEGAL), \
+		       XTENSA_MMU_PTE_ATTR_ILLEGAL)
+
 /**
  * PITLB HIT bit.
  *

boards/01space/esp32c3_042_oled/esp32c3_042_oled-pinctrl.dtsi

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
-#include <zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h>
+#include <dt-bindings/pinctrl/esp32c3-pinctrl.h>
 #include <zephyr/dt-bindings/pinctrl/esp32c3-gpio-sigmap.h>
 
 &pinctrl {

boards/96boards/aerocore2/96b_aerocore2.dts

@@ -18,7 +18,7 @@
 		zephyr,shell-uart = &uart7;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
-		zephyr,dtcm = &ccm0;
+		zephyr,ccm = &ccm0;
 	};
 
 	leds {

boards/96boards/stm32_sensor_mez/support/openocd.cfg

@@ -1,8 +1,6 @@
-source [find interface/stlink-dap.cfg]
-transport select dapdirect_swd
-# If your ST-Link adapter embedded firmware dates prior version v2j24
-# DAP transport/intereface is not supported. In this case, refer to
-# https://docs.zephyrproject.org/latest/develop/flash_debug/probes.html#OpenOCD-deprecates-hla-st-link-interface
+source [find interface/stlink.cfg]
+
+transport select hla_swd
 
 set WORKAREASIZE 0x2000
 

boards/CMakeLists.txt

@@ -5,14 +5,14 @@
 
 if(EXISTS ${BOARD_DIR}/CMakeLists.txt)
   if(USING_OUT_OF_TREE_BOARD)
-    set(build_dir boards/${ARCH}/${BOARD})
+	set(build_dir boards/${ARCH}/${BOARD})
   else()
-    unset(build_dir)
+	unset(build_dir)
 
-    # FIXME: SHADOW_VARS: Remove this once we have enabled -Wshadow globally.
-    #
-    # For now, only enable warning for shadow variables for in-tree boards.
-    add_compile_options($<TARGET_PROPERTY:compiler,warning_shadow_variables>)
+	# FIXME: SHADOW_VARS: Remove this once we have enabled -Wshadow globally.
+	#
+	# For now, only enable warning for shadow variables for in-tree boards.
+	add_compile_options($<TARGET_PROPERTY:compiler,warning_shadow_variables>)
   endif()
 
   add_subdirectory(${BOARD_DIR} ${build_dir})

boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include "actinius_icarus_som_dk_common-pinctrl.dtsi"
-#include <zephyr/dt-bindings/led/led.h>
+#include <dt-bindings/led/led.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {

boards/adafruit/feather_adalogger_rp2040/adafruit_feather_adalogger_rp2040-pinctrl.dtsi

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
 
 &pinctrl {
 	uart0_default: uart0_default {

boards/adafruit/feather_adalogger_rp2040/adafruit_feather_adalogger_rp2040.dts

@@ -9,7 +9,7 @@
 /dts-v1/;
 
 #include <raspberrypi/rpi_pico/rp2040.dtsi>
-#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <zephyr/dt-bindings/led/led.h>
 #include "adafruit_feather_adalogger_rp2040-pinctrl.dtsi"

boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040-pinctrl.dtsi

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
 
 &pinctrl {
 	uart0_default: uart0_default {

boards/adafruit/feather_canbus_rp2040/adafruit_feather_canbus_rp2040.dts

@@ -9,7 +9,7 @@
 /dts-v1/;
 
 #include <raspberrypi/rpi_pico/rp2040.dtsi>
-#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <zephyr/dt-bindings/led/led.h>
 #include "adafruit_feather_canbus_rp2040-pinctrl.dtsi"

boards/adafruit/feather_esp32/adafruit_feather_esp32-pinctrl.dtsi

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
-#include <zephyr/dt-bindings/pinctrl/esp32-pinctrl.h>
+#include <dt-bindings/pinctrl/esp32-pinctrl.h>
 #include <zephyr/dt-bindings/pinctrl/esp32-gpio-sigmap.h>
 
 &pinctrl {

boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
-#include <zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h>
+#include <dt-bindings/pinctrl/esp32s2-pinctrl.h>
 #include <zephyr/dt-bindings/pinctrl/esp32s2-gpio-sigmap.h>
 
 &pinctrl {

boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi

@@ -11,8 +11,8 @@
 #include "adafruit_feather_esp32s2-pinctrl.dtsi"
 #include <espressif/partitions_0x1000_default.dtsi>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <zephyr/dt-bindings/led/led.h>
-#include <zephyr/dt-bindings/led/worldsemi_ws2812c.h>
+#include <dt-bindings/led/led.h>
+#include <dt-bindings/led/worldsemi_ws2812c.h>
 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
 
 / {

boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3-pinctrl.dtsi

@@ -6,7 +6,7 @@
  */
 
 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
-#include <zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
 #include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
 
 &pinctrl {

boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft-pinctrl.dtsi

@@ -6,7 +6,7 @@
  */
 
 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
-#include <zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
 #include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
 
 &pinctrl {

boards/adafruit/feather_esp32s3_tft_reverse/adafruit_feather_esp32s3_tft_reverse-pinctrl.dtsi

@@ -7,7 +7,7 @@
  */
 
 #include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
-#include <zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
 #include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
 
 &pinctrl {

boards/adafruit/feather_rfm95_rp2040/adafruit_feather_rfm95_rp2040-pinctrl.dtsi

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
 
 &pinctrl {
 	uart0_default: uart0_default {

boards/adafruit/feather_rfm95_rp2040/adafruit_feather_rfm95_rp2040.dts

@@ -9,7 +9,7 @@
 /dts-v1/;
 
 #include <raspberrypi/rpi_pico/rp2040.dtsi>
-#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <zephyr/dt-bindings/led/led.h>
 #include "adafruit_feather_rfm95_rp2040-pinctrl.dtsi"
@@ -65,7 +65,7 @@
 		gpio-map-mask = <0xffffffff 0xffffffc0>;
 		gpio-map-pass-thru = <0 0x3f>;
 		gpio-map = <0 0 &gpio0 3 0>, /* SCL */
-			   <1 0 &gpio0 2 0>; /* SDA */
+			<1 0 &gpio0 2 0>; /* SDA */
 	};
 };
 
@@ -125,11 +125,11 @@ zephyr_i2c: &i2c1 {
 		compatible = "semtech,sx1276";
 		reset-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 		dio-gpios = <&gpio0 21 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO0 */
-			    <&gpio0 22 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO1 */
-			    <&gpio0 23 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO2 */
-			    <&gpio0 19 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO3 */
-			    <&gpio0 20 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO4 */
-			    <&gpio0 18 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* SX1276 DIO5 */
+			<&gpio0 22 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO1 */
+			<&gpio0 23 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO2 */
+			<&gpio0 19 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO3 */
+			<&gpio0 20 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* SX1276 DIO4 */
+			<&gpio0 18 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* SX1276 DIO5 */
 		spi-max-frequency = <10000000>;
 		power-amplifier-output = "pa-boost";
 	};
@@ -198,8 +198,8 @@ zephyr_i2c: &i2c1 {
 			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
 			chain-length = <1>;
 			color-mapping = <LED_COLOR_ID_GREEN
-					 LED_COLOR_ID_RED
-					 LED_COLOR_ID_BLUE>;
+				LED_COLOR_ID_RED
+				LED_COLOR_ID_BLUE>;
 			reset-delay = <280>;
 			frequency = <800000>;
 		};

boards/adafruit/feather_rfm95_rp2040/feather_connector.dtsi

@@ -11,31 +11,29 @@
 		gpio-map-mask = <0xffffffff 0xffffffc0>;
 		gpio-map-pass-thru = <0 0x3f>;
 		gpio-map = <0 0 &gpio0 26 0>,	/* A0 */
-			   <1 0 &gpio0 27 0>,	/* A1 */
-			   <2 0 &gpio0 28 0>,	/* A2 */
-			   <3 0 &gpio0 29 0>,	/* A3 */
-			   <4 0 &gpio0 24 0>,	/* D24 */
-			   <5 0 &gpio0 25 0>,	/* D25 */
-			   <6 0 &gpio0 14 0>,	/* SCK */
-			   <7 0 &gpio0 15 0>,	/* MOSI */
-			   <8 0 &gpio0 8 0>,	/* MISO */
-			   <9 0 &gpio0 1 0>,	/* RX */
-			   <10 0 &gpio0 0 0>,	/* TX */
-			   /* GND */
-			   <12 0 &gpio0 2 0>,	/* SDA */
-			   <13 0 &gpio0 3 0>,	/* SCL */
-			   <14 0 &gpio0 5 0>,	/* D5 */
-			   <15 0 &gpio0 6 0>,	/* D6 */
-			   <16 0 &gpio0 9 0>,	/* D9 */
-			   <17 0 &gpio0 10 0>,	/* D10 */
-			   <18 0 &gpio0 11 0>,	/* D11 */
-			   <19 0 &gpio0 12 0>,	/* D12 */
-			   <20 0 &gpio0 13 0>;	/* D13 */
+			<1 0 &gpio0 27 0>,	/* A1 */
+			<2 0 &gpio0 28 0>,	/* A2 */
+			<3 0 &gpio0 29 0>,	/* A3 */
+			<4 0 &gpio0 24 0>,	/* D24 */
+			<5 0 &gpio0 25 0>,	/* D25 */
+			<6 0 &gpio0 14 0>,	/* SCK */
+			<7 0 &gpio0 15 0>,	/* MOSI */
+			<8 0 &gpio0 8 0>,	/* MISO */
+			<9 0 &gpio0 1 0>,	/* RX */
+			<10 0 &gpio0 0 0>,	/* TX */
+			/* GND */
+			<12 0 &gpio0 2 0>,	/* SDA */
+			<13 0 &gpio0 3 0>,	/* SCL */
+			<14 0 &gpio0 5 0>,	/* D5 */
+			<15 0 &gpio0 6 0>,	/* D6 */
+			<16 0 &gpio0 9 0>,	/* D9 */
+			<17 0 &gpio0 10 0>,	/* D10 */
+			<18 0 &gpio0 11 0>,	/* D11 */
+			<19 0 &gpio0 12 0>,	/* D12 */
+			<20 0 &gpio0 13 0>;	/* D13 */
 	};
 };
 
 feather_serial: &uart0 {};
-
 feather_i2c: &i2c1 {};
-
 feather_spi: &spi1 {};

boards/adafruit/feather_rp2040/adafruit_feather_rp2040-pinctrl.dtsi

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
 
 &pinctrl {
 	uart0_default: uart0_default {

boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts

@@ -18,7 +18,7 @@
 		zephyr,shell-uart = &usart3;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
-		zephyr,dtcm = &ccm0;
+		zephyr,ccm = &ccm0;
 	};
 
 	leds {

boards/adafruit/feather_stm32f405/support/openocd.cfg

@@ -1,8 +1,6 @@
-source [find interface/stlink-dap.cfg]
-transport select dapdirect_swd
-# If your ST-Link adapter embedded firmware dates prior version v2j24
-# DAP transport/intereface is not supported. In this case, refer to
-# https://docs.zephyrproject.org/latest/develop/flash_debug/probes.html#OpenOCD-deprecates-hla-st-link-interface
+source [find interface/stlink.cfg]
+
+transport select hla_swd
 
 source [find target/stm32f4x.cfg]