Zephyr 1.5.0

Change-Id: Ie7a145c02a320bdb3c5cbce149d84d43bd194d76
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.checkpatch.conf

@@ -3,14 +3,16 @@
 --emacs
 --summary-file
 --show-types
---max-line-length=100
+--max-line-length=80
+--min-conf-desc-length=1
 
 --ignore BRACES
 --ignore PRINTK_WITHOUT_KERN_LEVEL
 --ignore SPLIT_STRING
---ignore FILE_PATH_CHANGES
 --ignore VOLATILE
 --ignore CONFIG_EXPERIMENTAL
 --ignore PREFER_KERNEL_TYPES
 --ignore AVOID_EXTERNS
 --ignore NETWORKING_BLOCK_COMMENT_STYLE
+--exclude ext
+--exclude net/ip/contiki

.gitignore

@@ -2,14 +2,15 @@
 *.a
 *.d
 *.cmd
+*.log
 *.pyc
 *.swp
 *.swo
-!arch/*/*/**/*.cmd
 *~
 cscope.*
 .dir
 outdir
+outdir-*
 scripts/basic/fixdep
 scripts/gen_idt/gen_idt
 scripts/gen_offset_header/gen_offset_header
@@ -19,9 +20,9 @@ scripts/kconfig/zconf.hash.c
 scripts/kconfig/zconf.lex.c
 scripts/kconfig/zconf.tab.c
 doc/_build
-xml
-html/
-doc/latex/
+doc/xml
+doc/html
+doc/latex
 sanity-out/
 scripts/grub
 doc/reference/kconfig/CONFIG_*

.known-issues/README

@@ -0,0 +1,55 @@
+This directory contains configuration files to ignore errors found in
+the build and test process which are known to the developers and for
+now can be safely ignored.
+
+To use:
+
+ $ cd zephyr
+ $ make SOMETHING >& result
+ $ scripts/filter-known-issues.py result
+
+It is included in the source tree so if anyone has to submit anything
+that triggers some kind of error that is a false positive, it can
+include the "ignore me" file, properly documented.
+
+Each file can contain one or more multiline Python regular expressions
+(https://docs.python.org/2/library/re.html#regular-expression-syntax)
+that match an error message. Multiple regular expressions are
+separated by comment blocks (that start with #). Note that an empty
+line still is considered part of the multiline regular expression.
+
+For example
+
+---beginning---
+#
+# This testcase always fails, pending fix ZEP-1234
+#
+.*/tests/kernel/grumpy .* FAIL
+#
+# Documentation issue, masks:
+#
+# /home/e/inaky/z/kernel.git/doc/api/io_interfaces.rst:28: WARNING: Invalid definition: Expected identifier in nested name. [error at 19]
+#  struct dev_config::@65  dev_config::bits
+#  -------------------^
+#
+^(?P<filename>.+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^\s+struct dev_config::@[0-9]+  dev_config::bits.*
+^\s+-+\^
+---end---
+
+Note you want to:
+
+- use relateive paths; instead of
+  /home/me/mydir/zephyr/something/somewhere.c you will want
+  ^.*/something/somewhere.c (as they will depend on where it is being
+  built)
+
+- Replace line numbers with [0-9]+, as they will change
+
+- (?P<filename>[-._/\w]+/something/somewhere.c) saves the match on
+  that file path in a "variable" called 'filename' that later you can
+  match with (?P=filename) if you want to match multiple lines of the
+  same error message.
+
+Can get really twisted and interesting in terms of regexps; they are
+powerful, so start small :)

.known-issues/doc/bluetooth.conf

@@ -0,0 +1,38 @@
+#
+# Bluetooth unnamed struct definition
+#
+# FIXME: all these should match the relative filename
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]$
+^.*bt_conn_info.__unnamed__.*$
+^[- \t]*\^$
+#
+# bt_gatt_discover_params unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_gatt_discover_params.__unnamed__.*
+^[- \t]*\^
+#
+# Bluetooth GATT unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_gatt_read_params.__unnamed__.*
+^[- \t]*\^

.known-issues/doc/header_footer.conf

@@ -0,0 +1,18 @@
+#
+# KERNELVERSION not being defined in local builds, kill that warning,
+# can ignore it
+#
+^.*/Kconfig.zephyr:[0-9]+: warning: The symbol KERNELVERSION references the non-existent environment variable KERNELVERSION.*
+#
+# Documentation generation, early message
+#
+^cd .* && doxygen doc/doxygen.config
+^srctree=.* SRCARCH=\w+ python scripts/genrest/genrest.py .*$
+# This cuts the sphinx build line; has to be separate because in the
+# middle, we have removed the KERNELVERSION one and a full regex won't match
+^sphinx-build -t \w+ -b html -d [-._/\w]+  -q \. .*
+#
+# Documentation generation, footer message
+#
+^[ \t]*
+^Build finished. The HTML pages are in [-._/\w]+

.known-issues/doc/sensor.conf

@@ -0,0 +1,12 @@
+#
+# Sensor value unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*sensor_value.__unnamed__.*
+^[- \t]*\^

.known-issues/doc/uart.conf

@@ -0,0 +1,15 @@
+#
+# UART unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*uart_device_config.__unnamed__.*
+^[- \t]*\^

.known-issues/make.conf

@@ -0,0 +1,4 @@
+#
+# Make blurbs
+#
+^make: (Entering|Leaving) directory .*

.mailmap

@@ -5,3 +5,10 @@ Leona Cook <leonax.cook@intel.com> <lsc@hackeress.com>
 Leona Cook <leonax.cook@intel.com> <leonax.cook@intel.com>
 Thomas Heeley <thomas.heeley@intel.com> <thomas.heeley@intel.com>
 Shuang He <shuang.he@intel.com> <shuang.he@intel.com>
+Chuck Jordan <cjordan@synopsys.com> <cjordan@synopsys.com>
+Jeremie Garcia <jeremie.garcia@intel.com> <jeremie.garcia@intel.com>
+Bit Pathe <bitpathe@gmail.com> <bitpathe@gmail.com>
+Carles Cufi <carles.cufi@nordicsemi.no> <carles.cufi@nordicsemi.no>
+Kuo-Lang Tseng <kuo-lang.tseng@intel.com> <kuo-lang.tseng@intel.com>
+Gerardo Aceves <gerardo.aceves@intel.com> <gerardo.aceves@intel.com>
+Evan Couzens <evanx.couzens@intel.com> <evanx.couzens@intel.com>

Kbuild

@@ -47,8 +47,12 @@ misc/generated/sysgen/prj.mdef:	$(MDEF_FILE_PATH) \
 				include/config/auto.conf FORCE
 	$(call filechk,prj.mdef)
 
-misc/generated/sysgen/kernel_main.c: misc/generated/sysgen/prj.mdef
-	$(Q)$(srctree)/scripts/sysgen $(CURDIR)/misc/generated/sysgen/prj.mdef $(CURDIR)/misc/generated/sysgen/
+misc/generated/sysgen/kernel_main.c: misc/generated/sysgen/prj.mdef \
+				     kernel/microkernel/include/micro_private_types.h \
+				     kernel/microkernel/include/kernel_main.h
+	$(Q)$(PYTHON) $(srctree)/scripts/sysgen \
+			$(CURDIR)/misc/generated/sysgen/prj.mdef \
+			$(CURDIR)/misc/generated/sysgen/
 
 define filechk_configs.c
 	(echo "/* file is auto-generated, do not modify ! */"; \
@@ -94,7 +98,7 @@ OFFSETS_INCLUDE = $(strip \
 
 cmd_cc_o_c_1 = $(CC) $(KBUILD_CFLAGS) $(OFFSETS_INCLUDE) -c -o $@ $<
 
-arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c
+arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c $(KCONFIG_CONFIG)
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed,cc_o_c_1)
 

Kconfig.zephyr

@@ -17,8 +17,8 @@
 # limitations under the License.
 #
 config KERNELVERSION
-        string
-        option env="KERNELVERSION"
+	string
+	option env="KERNELVERSION"
 
 source "arch/Kconfig"
 
@@ -30,6 +30,14 @@ source "net/Kconfig"
 
 source "misc/Kconfig"
 
+source "lib/Kconfig"
+
+source "fs/Kconfig"
+
+source "ext/Kconfig"
+
+source "usb/Kconfig"
+
 #
 # The following are for Kconfig files for default values only.
 # These should be parsed at the end.

MAINTAINERS

@@ -0,0 +1,280 @@
+Originally from the Linux Kernel.
+# Licensed under the terms of the GNU GPL License version 2
+
+Descriptions of section entries:
+
+	P: Person (obsolete)
+	M: Mail patches to: FullName <address@domain>
+	R: Designated reviewer: FullName <address@domain>
+	   These reviewers should be CCed on patches.
+	L: Mailing list that is relevant to this area
+	W: Web-page with status/info
+	Q: Patchwork web based patch tracking system site
+	T: SCM tree type and location.
+	   Type is one of: git, hg, quilt, stgit, topgit
+	S: Status, one of the following:
+	   Supported:	Someone is actually paid to look after this.
+	   Maintained:	Someone actually looks after it.
+	   Odd Fixes:	It has a maintainer but they don't have time to do
+			much other than throw the odd patch in. See below..
+	   Orphan:	No current maintainer [but maybe you could take the
+			role as you write your new code].
+	   Obsolete:	Old code. Something tagged obsolete generally means
+			it has been replaced by a better system and you
+			should be using that.
+	F: Files and directories with wildcard patterns.
+	   A trailing slash includes all files and subdirectory files.
+	   F:	drivers/net/	all files in and below drivers/net
+	   F:	drivers/net/*	all files in drivers/net, but not below
+	   F:	*/net/*		all files in "any top level directory"/net
+	   One pattern per line.  Multiple F: lines acceptable.
+	N: Files and directories with regex patterns.
+	   N:	[^a-z]tegra	all files whose path contains the word tegra
+	   One pattern per line.  Multiple N: lines acceptable.
+	   scripts/get_maintainer.pl has different behavior for files that
+	   match F: pattern and matches of N: patterns.  By default,
+	   get_maintainer will not look at git log history when an F: pattern
+	   match occurs.  When an N: match occurs, git log history is used
+	   to also notify the people that have git commit signatures.
+	X: Files and directories that are NOT maintained, same rules as F:
+	   Files exclusions are tested before file matches.
+	   Can be useful for excluding a specific subdirectory, for instance:
+	   F:	net/
+	   X:	net/ipv6/
+	   matches all files in and below net excluding net/ipv6/
+	K: Keyword perl extended regex pattern to match content in a
+	   patch or file.  For instance:
+	   K: of_get_profile
+	      matches patches or files that contain "of_get_profile"
+	   K: \b(printk|pr_(info|err))\b
+	      matches patches or files that contain one or more of the words
+	      printk, pr_info or pr_err
+	   One regex pattern per line.  Multiple K: lines acceptable.
+
+Note: For the hard of thinking, this list is meant to remain in alphabetical
+order. If you could add yourselves to it in alphabetical order that would be
+so much easier [Ed]
+
+Maintainers List (try to look for most precise areas first)
+
+		-----------------------------------
+
+ARC ARCHITECTURE
+M:	Ruud Derwig <Ruud.Derwig@synopsys.com>
+M:	Chuck Jordan <Chuck.Jordan@synopsys.com
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+S:	Supported
+F:	arch/arc/
+F:	include/arch/arc/
+
+ARM ARCHITECTURE
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	arch/arm/
+F:	include/arch/arm/
+
+BLUETOOTH
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Luiz Augusto von Dentz <luiz.dentz@gmail.com>
+M:	Szymon Janc <szymon.janc@gmail.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/bluetooth/bluetooth.html
+F:	net/bluetooth/
+F:	include/bluetooth/
+F:	drivers/bluetooth/
+F:	samples/bluetooth/
+F:	tests/bluetooth/
+
+DOCUMENTATION
+M:	Kinder, David <david.b.kinder@intel.com>
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	doc/
+
+FILE SYSTEM
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	ext/fs/
+F:	fs/
+F:	include/fs/
+F:	include/fs.h
+F:	samples/fs/
+
+FLASH DRIVER
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/flash/
+
+INTERRUPTS
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	drivers/interrupt_controller/
+F:	arch/arc/core/
+F:	arch/arm/core/
+F:	arch/nios2/core/
+F:	arch/x86/core/
+F:	include/irq.h
+F:	include/arch/x86/arch.h
+F:	include/arch/arm/cortex_m/irq.h
+F:	include/arch/nios2/arch.h
+F:	include/arch/arc/arch.h
+F:	include/arch/arc/v2/irq.h
+F:	include/drivers/loapic.h
+F:	include/drivers/ioapic.h
+F:	include/drivers/mvic.h
+
+KERNEL CORE
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Allan Stephens <allan.stephens@windriver.com>
+S:	Supported
+F:	kernel/
+F:	include/nanokernel.h
+F:	include/microkernel.h
+F:	include/microkernel/
+F:	include/misc/
+F:	include/toolchain/
+F:	include/atomic.h
+F:	include/cache.h
+F:	include/init.h
+F:	include/irq.h
+F:	include/irq_offload.h
+F:	include/kernel_version.h
+F:	include/linker-defs.h
+F:	include/linker-tool-gcc.h
+F:	include/linker-tool.h
+F:	include/section_tags.h
+F:	include/sections.h
+F:	include/shared_irq.h
+F:	include/sw_isr_table.h
+F:	include/sys_clock.h
+F:	include/sys_io.h
+F:	include/toolchain.h
+F:	include/zephyr.h
+
+KNOWN ISSUES
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
+F:	.known-issues/
+
+MAINTAINERS
+M:	Javier B Perez <javier.b.perez.hernandez@intel.com>
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	MAINTAINERS
+
+MBEDTLS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Jithu Joseph <jithu.joseph@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	ext/lib/crypto/mbedtls/
+F:	samples/net/mbedtls_sslclient/
+F:	tests/crypto/test_mbedtls/
+
+NETWORKING
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/networking/networking.html
+F:	net/ip/
+F:	include/net/
+F:	samples/net/
+F:	tests/net/
+
+NETWORK APPLICATIONS
+M:	Flavio Santes <flavio.santes@intel.com>
+S:	Supported
+F:	samples/net/dns_client/
+F:	samples/net/nats_clients/
+F:	samples/net/paho_mqtt_clients/
+
+NETWORK BUFFERS
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/networking/buffers.html
+F:	net/buf.c
+F:	include/net/buf.h
+F:	tests/net/buf/
+
+NIOS II
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	arch/nios2/
+F:	include/arch/nios2/
+F:	drivers/serial/uart_altera_jtag.c
+F:	drivers/timer/altera_avalon_timer.c
+F:	tests/kernel/test_intmath/
+
+NORDIC MDK
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	ext/hal/nordic/mdk/
+
+POWER MANAGEMENT
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	arch/x86/core/crt0.S
+F:	include/device.h
+F:	include/init.h
+F:	include/power.h
+F:	kernel/microkernel/k_idle.c
+F:	kernel/nanokernel/device.c
+F:	samples/power/
+
+QMSI
+M:	Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	ext/hal/qmsi/
+
+QMSI DRIVERS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/*/*qmsi*
+F:	drivers/*/*/*qmsi*
+
+SANITYCHECK
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	scripts/sanitycheck
+F:	scripts/expr_parser.py
+F:	scripts/sanity_chk/
+
+SENSOR DRIVERS
+M:	Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
+M:	Laurentiu Palcu <laurentiu.palcu@intel.com>
+M:	Murtaza Alexandru <alexandru.murtaza@intel.com>
+M:	Vlad Dogaru <vlad.dogaru@intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/sensor.html
+F:	include/sensor.h
+F:	drivers/sensor/
+F:	samples/sensor/
+
+TINYCRYPT
+M:	Constanza Heath <constanza.m.heath@intel.com>
+M:	Flavio Santes <flavio.santes@intel.com>
+S:	Supported
+F:	ext/lib/crypto/tinycrypt/
+F:	tests/crypto/
+
+X86 ARCH
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Allan Stephens <allan.stephens@windriver.com>
+S:	Supported
+F:	arch/x86/
+F:	include/arch/x86/
+
+THE REST
+M:	Anas Nashif <anas.nashif@intel.com>
+L:	devel@lists.zephyrproject.com
+T:	git https://gerrit.zephyrproject.org/r/a/zephyr
+S:	Buried alive in reporters
+F:	*
+F:	*/

Makefile

@@ -1,5 +1,5 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 2
+VERSION_MINOR 	   = 5
 PATCHLEVEL 	   = 0
 VERSION_RESERVED   = 0
 EXTRAVERSION       =
@@ -28,6 +28,9 @@ ifeq (MINGW, $(findstring MINGW, $(UNAME)))
 HOST_OS=MINGW
 PWD_OPT=-W
 DISABLE_TRYRUN=y
+CPATH ?= $(MIGW_DIR)/include
+LIBRARY_PATH ?= $(MINGW_DIR)/lib
+export CPATH LIBRARY_PATH
 else ifeq (Linux, $(findstring Linux, $(UNAME)))
 HOST_OS=Linux
 else ifeq (Darwin, $(findstring Darwin, $(UNAME)))
@@ -46,6 +49,7 @@ unexport GREP_OPTIONS
 
 DQUOTE = "
 #This comment line is to fix the highlighting of some editors due the quote effect."
+export DQUOTE
 
 # We are using a recursive build, so we need to do a little thinking
 # to get the ordering right.
@@ -99,9 +103,11 @@ endif
 ifeq ($(KBUILD_VERBOSE),1)
   quiet =
   Q =
+  GENIDT_EXTRA_ARGS = -d
 else
   quiet=quiet_
   Q = @
+  GENIDT_EXTRA_ARGS =
 endif
 
 # If the user is running make -s (silent mode), suppress echoing of
@@ -214,7 +220,7 @@ objtree		:= .
 src		:= $(srctree)
 obj		:= $(objtree)
 
-VPATH		:= $(srctree)
+VPATH		:= $(SOURCE_DIR_PARENT) $(srctree)
 
 export srctree objtree VPATH
 
@@ -263,8 +269,8 @@ CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
 	  else if [ -x /bin/bash ]; then echo /bin/bash; \
 	  else echo sh; fi ; fi)
 
-HOSTCC       = gcc
-HOSTCXX      = g++
+HOSTCC       ?= gcc
+HOSTCXX      ?= g++
 HOSTCFLAGS   = -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer -std=gnu89
 HOSTCXXFLAGS = -O2
 
@@ -281,15 +287,6 @@ KBUILD_BUILTIN := 1
 export KBUILD_BUILTIN
 export KBUILD_CHECKSRC KBUILD_SRC
 
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
 # Look for make include files relative to root of kernel src
 MAKEFLAGS += --include-dir=$(srctree)
 
@@ -307,8 +304,8 @@ ifeq ($(USE_CCACHE),1)
 CC		= $(CCACHE) $(CROSS_COMPILE)gcc
 CXX		= $(CCACHE) $(CROSS_COMPILE)g++
 else
-CC		= $(CROSS_COMPILE)gcc
-CXX		= $(CROSS_COMPILE)g++
+CC		?= $(CROSS_COMPILE)gcc
+CXX		?= $(CROSS_COMPILE)g++
 endif
 CPP		= $(CC) -E
 AR		= $(CROSS_COMPILE)ar
@@ -317,6 +314,7 @@ STRIP		= $(CROSS_COMPILE)strip
 OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
 GDB		= $(CROSS_COMPILE)gdb
+READELF		= $(CROSS_COMPILE)readelf
 AWK		= awk
 GENIDT		= scripts/gen_idt/gen_idt
 GENOFFSET_H	= scripts/gen_offset_header/gen_offset_header
@@ -345,18 +343,23 @@ endif
 USERINCLUDE    := -include $(CURDIR)/include/generated/autoconf.h
 
 SOC_NAME = $(subst $(DQUOTE),,$(CONFIG_SOC))
+SOC_SERIES = $(subst $(DQUOTE),,$(CONFIG_SOC_SERIES))
+SOC_FAMILY = $(subst $(DQUOTE),,$(CONFIG_SOC_FAMILY))
+
 override ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 BOARD_NAME = $(subst $(DQUOTE),,$(CONFIG_BOARD))
 KERNEL_NAME = $(subst $(DQUOTE),,$(CONFIG_KERNEL_BIN_NAME))
 KERNEL_ELF_NAME = $(KERNEL_NAME).elf
 KERNEL_BIN_NAME = $(KERNEL_NAME).bin
+KERNEL_STAT_NAME = $(KERNEL_NAME).stat
 
-export SOC_NAME BOARD_NAME ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
+export SOC_FAMILY SOC_SERIES SOC_PATH SOC_NAME BOARD_NAME
+export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
 # Use ZEPHYRINCLUDE when you must reference the include/ directory.
 # Needed to be compatible with the O= option
 ZEPHYRINCLUDE    = \
 		-I$(srctree)/arch/$(ARCH)/include \
-		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_NAME) \
+		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH) \
 		-I$(srctree)/boards/$(BOARD_NAME) \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
 		-I$(srctree)/include \
@@ -369,7 +372,6 @@ KBUILD_CPPFLAGS := -DKERNEL
 
 KBUILD_CFLAGS   := -c -g -std=c99 \
 		-fno-asynchronous-unwind-tables \
-		-fno-omit-frame-pointer \
 		-Wall \
 		-Wno-format-zero-length \
 		-Wno-main -ffreestanding
@@ -377,7 +379,6 @@ KBUILD_CFLAGS   := -c -g -std=c99 \
 KBUILD_CXXFLAGS   := -c -g -std=c++11 \
 		-fno-reorder-functions \
 		-fno-asynchronous-unwind-tables \
-		-fno-omit-frame-pointer \
 		-fcheck-new \
 		-fno-defer-pop -Wall \
 		-Wno-unused-but-set-variable \
@@ -515,8 +516,9 @@ PHONY += scripts
 scripts: scripts_basic include/config/auto.conf include/config/tristate.conf
 	$(Q)$(MAKE) $(build)=$(@)
 
-
-core-y := lib/ kernel/ misc/ net/ boards/ arch/
+# arch/ must be last here so that .gnu.linkonce magic for interrupts/exceptions
+# works as expected
+core-y := lib/ kernel/ misc/ net/ boards/ ext/ usb/ fs/ arch/
 drivers-y := drivers/
 
 ifneq ($(strip $(MAKEFILE_APP_DIR)),)
@@ -559,15 +561,9 @@ else
 include/config/auto.conf: ;
 endif # $(dot-config)
 
-ifdef CONFIG_TINYCRYPT
-# Objects we will link into the kernel / subdirs we need to visit
-KCRYPTO_DIR := lib/crypto/tinycrypt
-libs-y += $(KCRYPTO_DIR)/
- ZEPHYRINCLUDE += -I$(srctree)/lib/crypto/tinycrypt/include
-endif
-
 ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 export ARCH
+
 ifdef ZEPHYR_GCC_VARIANT
 include $(srctree)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
 else
@@ -575,23 +571,18 @@ $(if $(CROSS_COMPILE),, \
      $(error ZEPHYR_GCC_VARIANT is not set. ))
 endif
 
-ifdef CONFIG_QMSI_DRIVERS
-LIB_INCLUDE_DIR += -L$(CONFIG_QMSI_INSTALL_PATH:"%"=%)/lib
-ALL_LIBS += qmsi
-endif
+-include $(srctree)/ext/Makefile
+-include $(srctree)/lib/Makefile
 
-ifdef CONFIG_MINIMAL_LIBC
-ZEPHYRINCLUDE += -I$(srctree)/lib/libc/minimal/include
+ifneq ($(CC),)
+ifeq ($(shell $(CC) -v 2>&1 | grep -Ec "clang version|icx version"), 1)
+COMPILER := clang
+else
+COMPILER := gcc
 endif
-
-ifdef CONFIG_NEWLIB_LIBC
-ZEPHYRINCLUDE += $(TOOLCHAIN_CFLAGS)
-ALL_LIBS += c m
+export COMPILER
 endif
 
-QEMU_BIN_PATH	?= /usr/bin
-QEMU		= $(QEMU_BIN_PATH)/$(QEMU_$(ARCH))
-
 # The all: target is the default when no target is given on the
 # command line.
 # This allow a user to issue only 'make' to build a kernel including modules
@@ -609,7 +600,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-reorder-blocks,) \
 endif
 
 ifeq ($(CONFIG_DEBUG),y)
-KBUILD_CFLAGS  += -O0
+KBUILD_CFLAGS  += -Og
 else
 KBUILD_CFLAGS  += -Os
 endif
@@ -620,10 +611,23 @@ else
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector,)
 endif
 
+ifeq ($(CONFIG_OMIT_FRAME_POINTER),y)
+fp_arg := $(call cc-option,-fomit-frame-pointer,)
+else
+fp_arg := $(call cc-option,-fno-omit-frame-pointer,)
+endif
+KBUILD_CFLAGS += $(fp_arg)
+KBUILD_CXXFLAGS += $(fp_arg)
+
 KBUILD_CFLAGS += $(subst $(DQUOTE),,$(CONFIG_COMPILER_OPT))
 
 export LDFLAG_LINKERCMD
 
+ifeq ($(SOC_SERIES),)
+SOC_PATH = $(SOC_NAME)
+else
+SOC_PATH = $(SOC_FAMILY)/$(SOC_SERIES)
+endif
 include arch/$(ARCH)/Makefile
 
 KBUILD_CFLAGS += $(CFLAGS)
@@ -632,7 +636,6 @@ KBUILD_AFLAGS += $(CFLAGS)
 
 
 ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
 KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
 KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
 KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
@@ -655,6 +658,7 @@ endif
 
 # arch Makefile may override CC so keep this after arch Makefile is included
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+NOSTDINC_FLAGS += -isystem $(shell $(CC) -print-file-name=include-fixed)
 CHECKFLAGS     += $(NOSTDINC_FLAGS)
 
 # disable pointer signed / unsigned warnings in gcc 4.0
@@ -688,11 +692,12 @@ KBUILD_CFLAGS += $(KCFLAGS)
 
 # Use --build-id when available.
 
+LINKFLAGPREFIX ?= -Wl,
 LDFLAGS_zephyr += $(LDFLAGS)
-LDFLAGS_zephyr += $(call ld-option,-X)
-LDFLAGS_zephyr += $(call ld-option,-N)
-LDFLAGS_zephyr += $(call ld-option,--gc-sections)
-LDFLAGS_zephyr += $(call ld-option,--build-id=none)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-X)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-N)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--gc-sections)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--build-id=none)
 
 LD_TOOLCHAIN ?= -D__GCC_LINKER_CMD__
 
@@ -700,21 +705,30 @@ ifdef CONFIG_HAVE_CUSTOM_LINKER_SCRIPT
 KBUILD_LDS         := $(subst $(DQUOTE),,$(CONFIG_CUSTOM_LINKER_SCRIPT))
 else
 # Try a board specific linker file
-KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.cmd
+KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.ld
 
 # If not available, try an SoC specific linker file
 ifeq ($(wildcard $(KBUILD_LDS)),)
-KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/linker.cmd
+KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/linker.ld
 endif
 endif
 
 export LD_TOOLCHAIN KBUILD_LDS
 
+ifdef MAKEFILE_TOOLCHAIN_DO_PASS2
+# KBUILD_CFLAGS known at this point.
+# We can now determine which multilib libraries to use
+include $(srctree)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
+endif
+
+QEMU_BIN_PATH	?= /usr/bin
+QEMU		= $(QEMU_BIN_PATH)/$(QEMU_$(ARCH))
+
 # The all: target is the default when no target is given on the
 # command line.
 # This allow a user to issue only 'make' to build a kernel including modules
 # Defaults to zephyr, but the arch makefile usually adds further targets
-all: $(KERNEL_BIN_NAME)
+all: $(KERNEL_BIN_NAME) $(KERNEL_STAT_NAME)
 
 # Default kernel image to build when no specific target is given.
 # KBUILD_IMAGE may be overruled on the command line or
@@ -724,22 +738,26 @@ all: $(KERNEL_BIN_NAME)
 export KBUILD_IMAGE ?= zephyr
 
 zephyr-dirs	:= $(patsubst %/,%,$(filter %/, $(core-y) $(drivers-y) \
-		     $(libs-y) $(app-y)))
+		     $(libs-y)))
+zephyr-app-dir-root := $(abspath $(patsubst %, %/.., $(SOURCE_DIR)))
 
-zephyr-alldirs	:= $(sort $(zephyr-dirs) $(patsubst %/,%,$(filter %/, \
+zephyr-alldirs	:= $(sort $(zephyr-dirs) $(SOURCE_DIR) $(patsubst %/,%,$(filter %/, \
 		     $(core-) $(drivers-) $(libs-) $(app-))))
 
 core-y		:= $(patsubst %/, %/built-in.o, $(core-y))
-app-y		:= $(patsubst %/, %/built-in.o, $(app-y))
+app-y		:= $(patsubst %, %/built-in.o, $(notdir $(SOURCE_DIR)))
 drivers-y	:= $(patsubst %/, %/built-in.o, $(drivers-y))
 libs-y1		:= $(patsubst %/, %/lib.a, $(libs-y))
 libs-y2		:= $(patsubst %/, %/built-in.o, $(libs-y))
 libs-y		:= $(libs-y1) $(libs-y2)
 
-export KBUILD_ZEPHYR_MAIN := $(drivers-y) $(libs-y) $(app-y) $(core-y)
+# core-y must be last here. several arches use .gnu.linkonce magic
+# to register interrupt or exception handlers, and defaults under
+# arch/ (part of core-y) must be linked after drivers or libs.
+export KBUILD_ZEPHYR_MAIN := $(drivers-y) $(libs-y) $(core-y)
 export LDFLAGS_zephyr
 
-zephyr-deps := $(KBUILD_LDS) $(KBUILD_ZEPHYR_MAIN)
+zephyr-deps := $(KBUILD_LDS) $(KBUILD_ZEPHYR_MAIN) $(app-y)
 
 ALL_LIBS += $(TOOLCHAIN_LIBS)
 export ALL_LIBS
@@ -749,23 +767,31 @@ LINK_LIBS := $(foreach l,$(ALL_LIBS), -l$(l))
 OUTPUT_FORMAT ?= elf32-i386
 OUTPUT_ARCH ?= i386
 
+quiet_cmd_ar_target = AR      $@
+cmd_ar_target = rm -f $@; $(AR) rcT$(KBUILD_ARFLAGS) $@ $(KBUILD_ZEPHYR_MAIN)
+libzephyr.a: $(zephyr-deps)
+	$(call cmd,ar_target)
+
 quiet_cmd_create-lnk = LINK    $@
       cmd_create-lnk =								\
 (										\
 	echo $(LDFLAGS_zephyr); 						\
-	echo "-Map ./$(KERNEL_NAME).map"; 					\
+	echo "$(LINKFLAGPREFIX)-Map=$(KERNEL_NAME).map"; 			\
 	echo "-L $(objtree)/include/generated";					\
 	echo "-u _OffsetAbsSyms -u _ConfigAbsSyms"; 				\
 	echo "-e __start"; 						 	\
-	echo "--start-group";							\
-	echo "--whole-archive $(KBUILD_ZEPHYR_APP) --no-whole-archive";         \
-	echo "$(KBUILD_ZEPHYR_MAIN)";						\
+	echo "$(LINKFLAGPREFIX)--start-group";					\
+	echo "$(LINKFLAGPREFIX)--whole-archive";				\
+	echo "$(KBUILD_ZEPHYR_APP)";						\
+	echo "$(app-y)";							\
+	echo "libzephyr.a";							\
+	echo "$(LINKFLAGPREFIX)--no-whole-archive";         			\
 	echo "$(objtree)/arch/$(ARCH)/core/offsets/offsets.o"; 			\
-	echo "--end-group"; 							\
+	echo "$(LINKFLAGPREFIX)--end-group"; 					\
 	echo "$(LIB_INCLUDE_DIR) $(LINK_LIBS)";					\
 ) > $@
 
-$(KERNEL_NAME).lnk:
+$(KERNEL_NAME).lnk: $(zephyr-deps)
 	$(call cmd,create-lnk)
 
 linker.cmd: $(zephyr-deps)
@@ -780,8 +806,8 @@ final-linker.cmd: $(zephyr-deps)
 
 TMP_ELF = .tmp_$(KERNEL_NAME).prebuilt
 
-$(TMP_ELF): $(zephyr-deps) $(KBUILD_ZEPHYR_APP) linker.cmd $(KERNEL_NAME).lnk
-	$(Q)$(LD) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
+$(TMP_ELF): $(zephyr-deps) libzephyr.a $(KBUILD_ZEPHYR_APP) $(app-y) linker.cmd $(KERNEL_NAME).lnk
+	$(Q)$(CC) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
 
 quiet_cmd_gen_idt = SIDT    $@
       cmd_gen_idt =								\
@@ -789,7 +815,7 @@ quiet_cmd_gen_idt = SIDT    $@
 	$(OBJCOPY) -I $(OUTPUT_FORMAT)  -O binary -j intList $< isrList.bin &&	\
 	$(GENIDT) -i isrList.bin -n $(CONFIG_IDT_NUM_VECTORS) -o staticIdt.bin 	\
 		-b int_vector_alloc.bin -m irq_int_vector_map.bin		\
-		-l $(CONFIG_MAX_IRQ_LINES) &&					\
+		-l $(CONFIG_MAX_IRQ_LINES) $(GENIDT_EXTRA_ARGS) &&		\
 	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
 		--rename-section .data=staticIdt staticIdt.bin staticIdt.o &&	\
 	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
@@ -807,19 +833,29 @@ staticIdt.o: $(TMP_ELF)
 quiet_cmd_lnk_elf = LINK    $@
       cmd_lnk_elf =									\
 (											\
-	$(LD) -T final-linker.cmd @$(KERNEL_NAME).lnk staticIdt.o int_vector_alloc.o 	\
+	$(CC) -T final-linker.cmd @$(KERNEL_NAME).lnk staticIdt.o int_vector_alloc.o 	\
 	irq_int_vector_map.o -o $@;							\
 	${OBJCOPY} --change-section-address intList=${CONFIG_PHYS_LOAD_ADDR} $@ elf.tmp;\
 	$(OBJCOPY) -R intList elf.tmp $@;						\
 	rm elf.tmp									\
 )
 
+ASSERT_WARNING_STR := \
+    "\n      ------------------------------------------------------------" \
+    "\n      --- WARNING:  __ASSERT() statements are globally ENABLED ---" \
+    "\n      --- The kernel will run more slowly and uses more memory ---" \
+    "\n      ------------------------------------------------------------\n\n" \
+
+WARN_ABOUT_ASSERT := $(if $(CONFIG_ASSERT),echo -e -n $(ASSERT_WARNING_STR),true)
+
 ifeq ($(ARCH),x86)
 $(KERNEL_ELF_NAME): staticIdt.o final-linker.cmd
 	$(call cmd,lnk_elf)
+	@$(WARN_ABOUT_ASSERT)
 else
 $(KERNEL_ELF_NAME): $(TMP_ELF)
 	@cp $(TMP_ELF) $(KERNEL_ELF_NAME)
+	@$(WARN_ABOUT_ASSERT)
 endif
 
 
@@ -834,11 +870,19 @@ quiet_cmd_gen_bin = BIN     $@
 $(KERNEL_BIN_NAME): $(KERNEL_ELF_NAME)
 	$(call cmd,gen_bin)
 
+$(KERNEL_STAT_NAME): $(KERNEL_BIN_NAME) $(KERNEL_ELF_NAME)
+	@$(READELF) -e $(KERNEL_ELF_NAME) > $@
+
+ram_report: $(KERNEL_STAT_NAME)
+	@$(srctree)/scripts/size_report -r -o $(O)
+rom_report: $(KERNEL_STAT_NAME)
+	@$(srctree)/scripts/size_report -F -o $(O)
+
 zephyr: $(zephyr-deps) $(KERNEL_BIN_NAME)
 
 # The actual objects are generated when descending,
 # make sure no implicit rule kicks in
-$(sort $(zephyr-deps)): $(zephyr-dirs) ;
+$(sort $(zephyr-deps)): $(zephyr-dirs) zephyr-app-dir ;
 
 # Handle descending into subdirectories listed in $(zephyr-dirs)
 # Preset locale variables to speed up the build process. Limit locale
@@ -850,6 +894,10 @@ PHONY += $(zephyr-dirs)
 $(zephyr-dirs): prepare scripts
 	$(Q)$(MAKE) $(build)=$@
 
+PHONY += zephyr-app-dir
+zephyr-app-dir: prepare scripts
+	$(Q)$(MAKE) $(build)=$(notdir $(SOURCE_DIR)) srctree=$(zephyr-app-dir-root)
+
 # Things we need to do before we recursively start building the kernel
 # or the modules are listed in "prepare".
 # A multi level approach is used. prepareN is processed before prepareN-1.
@@ -948,6 +996,8 @@ CLEAN_DIRS  += $(MODVERDIR)
 CLEAN_FILES += 	misc/generated/sysgen/kernel_main.c \
 		misc/generated/sysgen/sysgen.h \
 		misc/generated/sysgen/prj.mdef \
+		misc/generated/sysgen/micro_private_types.h \
+		misc/generated/sysgen/kernel_main.h \
 		.old_version .tmp_System.map .tmp_version \
 		.tmp_* System.map *.lnk *.map *.elf *.lst \
 		*.bin *.strip staticIdt.o linker.cmd final-linker.cmd
@@ -967,9 +1017,9 @@ clean: rm-dirs  := $(CLEAN_DIRS)
 clean: rm-files := $(CLEAN_FILES)
 clean-dirs      := $(addprefix _clean_, . $(zephyr-alldirs) )
 
-PHONY += $(clean-dirs) clean archclean zephyrclean
-$(clean-dirs):
-	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
+PHONY += clean-dirs-target clean archclean zephyrclean
+clean-dirs-target:
+	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$(clean-dirs))
 
 clean: archclean
 
@@ -1025,6 +1075,7 @@ help:
 	@echo  '  all		  - Build all targets marked with [*]'
 	@echo  '* zephyr	  - Build a zephyr application'
 	@echo  '  qemu		  - Build a zephyr application and run it in qemu'
+	@echo  '  qemugdb         - Same as 'qemu' but start a GDB server on port 1234'
 	@echo  '  flash		  - Build and flash an application'
 	@echo  '  debug		  - Build and debug an application using GDB'
 	@echo  ''
@@ -1081,7 +1132,7 @@ $(help-board-dirs): help-%:
 %docs: FORCE
 	$(Q)$(MAKE) -C doc htmldocs
 
-clean: $(clean-dirs)
+clean: clean-dirs-target
 	$(call cmd,rmdirs)
 	$(call cmd,rmfiles)
 	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
@@ -1126,12 +1177,16 @@ tools/%: FORCE
 
 QEMU_FLAGS = $(QEMU_FLAGS_$(ARCH)) -pidfile qemu.pid
 
+ifneq ($(QEMU_PTY),)
+    QEMU_FLAGS += -serial pty
+else
 ifneq ($(QEMU_PIPE),)
     # Send console output to a pipe, used for running automated sanity tests
     QEMU_FLAGS += -serial pipe:$(QEMU_PIPE)
 else
     QEMU_FLAGS += -serial mon:stdio
 endif
+endif
 
 qemu: zephyr
 	$(if $(QEMU_PIPE),,@echo "To exit from QEMU enter: 'CTRL+a, x'")
@@ -1139,6 +1194,9 @@ qemu: zephyr
 	$(if $(CONFIG_X86_IAMCU),python $(ZEPHYR_BASE)/scripts/qemu-machine-hack.py $(KERNEL_ELF_NAME))
 	$(Q)$(QEMU) $(QEMU_FLAGS) $(QEMU_EXTRA_FLAGS) -kernel $(KERNEL_ELF_NAME)
 
+qemugdb: QEMU_EXTRA_FLAGS += -s -S
+qemugdb: qemu
+
 -include $(srctree)/boards/$(BOARD_NAME)/Makefile.board
 ifneq ($(FLASH_SCRIPT),)
 flash: zephyr

Makefile.inc

@@ -1,12 +1,19 @@
 # vim: filetype=make
 #
 
-DQUOTE = "
-# "
-
 ARCH ?= x86
 
+UNAME := $(shell uname)
+ifeq (MINGW, $(findstring MINGW, $(UNAME)))
+DQUOTE = '
+# '
+PROJECT_BASE ?= $(shell sh -c "pwd -W")
+else
+DQUOTE = "
+# "
 PROJECT_BASE ?= $(CURDIR)
+endif
+
 O ?= $(PROJECT_BASE)/outdir
 
 # Turn O into an absolute path; we call the main Kbuild with $(MAKE) -C
@@ -25,17 +32,20 @@ override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
 
 ifdef BOARD
 KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD)_defconfig)
-export KBUILD_DEFCONFIG_PATH
+ifeq ($(KBUILD_DEFCONFIG_PATH),)
+$(error Board $(BOARD) not found!)
+endif
 else
 $(error BOARD is not defined!)
 endif
 
 SOURCE_DIR ?= $(PROJECT_BASE)/src/
-# Kbuild doesn't work correctly if this is an absolute path
-# FIXME Do not depend on python
-override SOURCE_DIR := $(shell python -c "import os.path; print(\"%s\" % os.path.relpath(os.path.realpath('$(SOURCE_DIR)'), os.path.realpath('$(ZEPHYR_BASE)')))")/
+override SOURCE_DIR := $(abspath $(SOURCE_DIR))
 override SOURCE_DIR := $(subst \,/,$(SOURCE_DIR))
-export SOURCE_DIR
+override SOURCE_DIR_PARENT := $(patsubst %, %/.., $(SOURCE_DIR))
+override SOURCE_DIR_PARENT := $(abspath $(SOURCE_DIR_PARENT))
+override SOURCE_DIR_PARENT := $(subst \,/,$(SOURCE_DIR_PARENT))
+export SOURCE_DIR SOURCE_DIR_PARENT
 
 ifeq ("$(origin V)", "command line")
   KBUILD_VERBOSE = $(V)
@@ -52,8 +62,12 @@ else
   S = -s
 endif
 
-zephyrmake	= @+$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) CFLAGS=$(CFLAGS) \
-			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(SOURCE_DIR) $(2)
+export CFLAGS
+
+zephyrmake	= +$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) \
+			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(DQUOTE)$(SOURCE_DIR)$(DQUOTE) $(2)
+
+BOARDCONFIG = $(O)/.board_$(BOARD)
 
 DOTCONFIG = $(O)/.config
 
@@ -63,9 +77,12 @@ all: $(DOTCONFIG)
 ifeq ($(findstring qemu_,$(BOARD)),)
 qemu:
 	@echo "Emulation not available for this platform"
+qemugdb: qemu
 else
 qemu: $(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
+qemugdb: $(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
 endif
 
 debug:	$(DOTCONFIG)
@@ -86,6 +103,17 @@ debugserver: FORCE
 
 initconfig: $(DOTCONFIG)
 
+$(BOARDCONFIG):
+	@rm -f $(O)/.board_*
+	@touch $@
+
+
+ram_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+rom_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
 menuconfig: initconfig
 	$(Q)$(call zephyrmake,$(O),$@)
 
@@ -98,7 +126,7 @@ help:
 
 KERNEL_CONFIG = $(ZEPHYR_BASE)/kernel/configs/$(KERNEL_TYPE).config
 
-$(DOTCONFIG): $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
+$(DOTCONFIG): $(BOARDCONFIG) $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
 	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/kconfig/merge_config.sh \
 		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(KERNEL_CONFIG) $(CONF_FILE)
 	$(Q)$(MAKE) $(S) -C $(ZEPHYR_BASE) O=$(O) PROJECT=$(PROJECT_BASE) oldnoconfig

arch/Kconfig

@@ -27,10 +27,16 @@ config ARC
 
 config ARM
 	bool "ARM architecture"
+	select ATOMIC_OPERATIONS_BUILTIN
 
 config X86
 	bool "x86 architecture"
 	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
+	select ATOMIC_OPERATIONS_BUILTIN
+
+config NIOS2
+	bool "Nios II Gen 2 architecture"
+	select ATOMIC_OPERATIONS_C
 
 endchoice
 
@@ -40,19 +46,19 @@ endchoice
 #
 config SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	# Hidden
-        bool
-        default n
-        help
-        This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
-        configuration option.
+	bool
+	default n
+	help
+	This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
+	configuration option.
 
 config SYS_POWER_DEEP_SLEEP_SUPPORTED
 	# Hidden
-        bool
-        default n
-        help
-        This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
-        configuration option.
+	bool
+	default n
+	help
+	This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
+	configuration option.
 #
 # End hidden PM feature configs
 #
@@ -63,16 +69,35 @@ config ARCH
 	System architecture string.
 
 config SOC
-        string
-        help
-        This option holds the directory name used by the build system to locate
-        the correct linker file.
+	string
+	help
+	SoC name which can be found under arch/<arch>/soc/<soc name>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files for the SoC. This option will go away
+	once all SoCs are using family/series structure.
+
+config SOC_SERIES
+	string
+	help
+	SoC series name which can be found under arch/<arch>/soc/<family>/<series>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
+
+config SOC_FAMILY
+	string
+	help
+	SoC family name which can be found under arch/<arch>/soc/<family>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
 
 config BOARD
 	string
 	help
 	This option holds the name of the board and is used to located the files
-	related to the board in the source tree.
+	related to the board in the source tree (under boards/).
+	The Board is the first location where we search for a linker.ld file,
+	if not found we look for the linker file in
+	arch/<arch>/soc/<family>/<series>
 
 source "arch/*/Kconfig"
 

arch/Makefile

@@ -1,9 +1 @@
-ifeq (${ARCH},arm)
-obj-y += arm/
-endif
-ifeq (${ARCH},x86)
-obj-y += x86/
-endif
-ifeq (${ARCH},arc)
-obj-y += arc/
-endif
+obj-y += $(ARCH)/

arch/arc/Kbuild

@@ -2,5 +2,5 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y += $(subdir-ccflags-y)
 
-obj-y += soc/$(SOC_NAME)/
+obj-y += soc/$(SOC_PATH)/
 obj-y += core/

arch/arc/Kconfig

@@ -40,6 +40,7 @@ config	CPU_ARCEM4
 	bool
 	default y
 	select CPU_ARCV2
+	select ATOMIC_OPERATIONS_C
 	help
 	This option signifies the use of an ARC EM4 CPU
 
@@ -54,14 +55,6 @@ config	CPU_ARCV2
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config RAM_START
-	prompt "RAM start address"
-	hex
-
-config RAM_SIZE
-	prompt "RAM size (in kB)"
-	int
-
 config NSIM
 	prompt "Running on the MetaWare nSIM simulator"
 	bool
@@ -72,8 +65,6 @@ config NSIM
 	  a) Uses non-XIP to run in RAM.
 	  b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
 	     a pc_size of 16 (default).
-	  c) Sets the entry point to __reset, since it seems nSIM ignores the
-	     reset vector when starting (??).
 
 config	DATA_ENDIANNESS_LITTLE
 	bool
@@ -144,13 +135,15 @@ config	FAULT_DUMP
 	default 2
 	range 0 2
 	help
-	  Different levels for display information when a fault occurs.
+	Different levels for display information when a fault occurs.
 
-	  2: The default. Display specific and verbose information. Consumes
-	     the most memory (long strings).
-	  1: Display general and short information. Consumes less memory
-	     (short strings).
-	  0: Off.
+	2: The default. Display specific and verbose information. Consumes
+		the most memory (long strings).
+
+	1: Display general and short information. Consumes less memory
+		(short strings).
+
+	0: Off.
 
 config IRQ_OFFLOAD
 	bool "Enable IRQ offload"
@@ -164,20 +157,71 @@ config	XIP
 	default n if NSIM
 	default y
 
-config NSIM
-	prompt "Running on the MetaWare nSIM simulator"
+config HARVARD
+	prompt "Harvard Architecture"
 	bool
 	default n
 	help
-	For running on nSIM simulator.
+	  The ARC CPU can be configured to have two busses;
+	  one for instruction fetching and another that serves as a data bus.
 
-	a) Uses non-XIP to run in RAM.
-	b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
-	   a pc_size of 16 (default).
-	c) Sets the entry point to __reset, since it seems nSIM ignores the
-	   reset vector when starting.
+config ICCM_SIZE
+	int "ICCM Size in kB"
+	help
+	This option specifies the size of the ICCM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
 
-config  SW_ISR_TABLE
+config ICCM_BASE_ADDRESS
+	hex "ICCM Base Address"
+	help
+	This option specifies the base address of the ICCM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config DCCM_SIZE
+	int "DCCM Size in kB"
+	help
+	This option specifies the size of the DCCM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config DCCM_BASE_ADDRESS
+	hex "DCCM Base Address"
+	help
+	This option specifies the base address of the DCCM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config SRAM_SIZE
+	int "SRAM Size in kB"
+	help
+	This option specifies the size of the SRAM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config SRAM_BASE_ADDRESS
+	hex "SRAM Base Address"
+	help
+	This option specifies the base address of the SRAM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config FLASH_SIZE
+	int "Flash Size in kB"
+	help
+	This option specifies the size of the flash in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config FLASH_BASE_ADDRESS
+	hex "Flash Base Address"
+	help
+	This option specifies the base address of the flash on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config SW_ISR_TABLE
 	bool
 	prompt "Enable software interrupt handler table"
 	default y
@@ -190,7 +234,7 @@ config  SW_ISR_TABLE
 	  This has to be enabled for dynamically connecting interrupt handlers
 	  at runtime (SW_ISR_TABLE_DYNAMIC).
 
-config  SW_ISR_TABLE_DYNAMIC
+config SW_ISR_TABLE_DYNAMIC
 	bool
 	prompt "Allow installing interrupt handlers at runtime"
 	depends on SW_ISR_TABLE
@@ -200,7 +244,7 @@ config  SW_ISR_TABLE_DYNAMIC
 	  SRAM so that it is writable. This has the side-effect of removing
 	  write-protection on the ISR table.
 
-config  IRQ_VECTOR_TABLE_CUSTOM
+config IRQ_VECTOR_TABLE_CUSTOM
 	bool
 	prompt "Projects provide a custom static IRQ part of vector table"
 	depends on !SW_ISR_TABLE
@@ -230,29 +274,16 @@ config	IRQ_VECTOR_TABLE_BSP
 	help
 	  Not user-selectable, helps build system logic.
 
-config  ARCH_HAS_TASK_ABORT
+config ARCH_HAS_TASK_ABORT
 	bool
 	# omit prompt to signify a "hidden" option
 	default n
 
-config  ARCH_HAS_NANO_FIBER_ABORT
+config ARCH_HAS_NANO_FIBER_ABORT
 	bool
 	# omit prompt to signify a "hidden" option
 	default n
 
-config  ARC_ATOMIC_ASM
-	bool
-	default n
-	depends on !CPU_ARCEM4
-	help
-	  Say y if the processor supports atomic assembly instructions:
-	  LLOCK and SCOND.
-
-	  Say n if not sure.
-
-	  Note that these instructions are not supported on ARC EM family
-	  processors.
-
 endmenu
 
 

arch/arc/Makefile

@@ -2,8 +2,14 @@ cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-secti
 cflags-$(CONFIG_ARC_STACK_CHECKING) = $(call cc-option,-fomit-frame-pointer)
 cflags-$(CONFIG_LTO) = $(call cc-option,-flto,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)
 
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)
+

arch/arc/core/Makefile

@@ -13,13 +13,9 @@ obj-y += prep_c.o \
          vector_table.o
 
 obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
-obj-$(CONFIG_ERRNO) += errno.o
-
-ifeq ($(CONFIG_ARC_ATOMIC_ASM),y)
-obj-y += atomic.o
-else
-obj-y += atomic_native.o
-endif
 
+# Some ARC cores like the EM4 lack the atomic LLOCK/SCOND and
+# can't use these.
+obj-$(CONFIG_ATOMIC_OPERATIONS_CUSTOM) += atomic.o
 obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
 obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arc/core/cpu_idle.S

@@ -61,12 +61,17 @@ SECTION_VAR(BSS, nano_cpu_sleep_mode)
 
 SECTION_FUNC(TEXT, nano_cpu_idle)
 
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+	push_s blink
+	jl    _sys_k_event_logger_enter_sleep
+	pop_s blink
+#endif
 	enter_tickless_idle
 
 	ld r1, [nano_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
-	j_s.nd [blink]
+	j_s [blink]
 	nop
 
 /*
@@ -78,6 +83,12 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
  */
 SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
 
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+	push_s blink
+	jl    _sys_k_event_logger_enter_sleep
+	pop_s blink
+#endif
+
 	enter_tickless_idle
 
 	ld r1, [nano_cpu_sleep_mode]

arch/arc/core/fast_irq.S

@@ -45,14 +45,16 @@ SECTION_VAR(NOINIT, _firq_stack)
  *
  * The processor switches to a second register bank so registers from the
  * current bank do not have to be preserved yet. The only issue is the LP_START/
- * LP_COUNT/LP_END registers, which are not banked.
+ * LP_COUNT/LP_END registers, which are not banked. These can be saved
+ * in available callee saved registers.
  *
  * If all FIRQ ISRs are programmed such that there are no use of the LP
  * registers (ie. no LPcc instruction), and CONFIG_ARC_STACK_CHECKING is
- * not set, then the kernel can be configured to remove the use of _firq_enter().
+ * not set, then the kernel can be configured to not save and restore them.
  *
  * When entering a FIRQ, interrupts might as well be locked: the processor is
- * running at its highest priority, and cannot be preempted by anything.
+ * running at its highest priority, and cannot be interrupted by any other
+ * interrupt. An exception, however, can be taken.
  *
  * Assumption by _isr_demux: r3 is untouched by _firq_enter.
  *
@@ -61,6 +63,11 @@ SECTION_VAR(NOINIT, _firq_stack)
 
 SECTION_FUNC(TEXT, _firq_enter)
 
+	/*
+	 * ATTENTION:
+	 * firq uses a 2nd register bank so GPRs do not need to be saved.
+	 */
+
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
@@ -70,20 +77,13 @@ SECTION_FUNC(TEXT, _firq_enter)
 
 #ifndef CONFIG_FIRQ_NO_LPCC
 	/*
-	 * Unlike the rest of context switching code, r2 is loaded with something
-	 * else than 'current' in this routine: this is to preserve r3 so that it
-	 * does not have to be fetched again in _isr_demux.
+	 * Save LP_START/LP_COUNT/LP_END because called handler might use.
+	 * Save these in callee saved registers to avoid using memory.
+	 * These will be saved by the compiler if it needs to spill them.
 	 */
-
-	/* save LP_START/LP_COUNT/LP_END variables */
-	mov_s r1, _nanokernel
-
-	st lp_count, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
-
-	lr r2, [_ARC_V2_LP_START]
-	st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
-	lr r2, [_ARC_V2_LP_END]
-	st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
+	mov r23,lp_count
+	lr r24, [_ARC_V2_LP_START]
+	lr r25, [_ARC_V2_LP_END]
 #endif
 
 	j @_isr_demux
@@ -97,30 +97,19 @@ SECTION_FUNC(TEXT, _firq_enter)
 
 SECTION_FUNC(TEXT, _firq_exit)
 
+#ifndef CONFIG_FIRQ_NO_LPCC
+	/* restore lp_count, lp_start, lp_end from r23-r25 */
+	mov lp_count,r23
+	sr r24, [_ARC_V2_LP_START]
+	sr r25, [_ARC_V2_LP_END]
+#endif
+
 	mov_s r1, _nanokernel
 	ld_s r2, [r1, __tNANO_current_OFFSET]
 
-#ifndef CONFIG_FIRQ_NO_LPCC
-
-	/* assumption: r1 contains _nanokernel, r2 contains the current thread */
-
-	/* restore LP_START/LP_COUNT/LP_END variables */
-
-	/* cannot load lp_count from memory */
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
-	mov lp_count, r3
-
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
-	sr r3, [_ARC_V2_LP_START]
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
-	sr r3, [_ARC_V2_LP_END]
-
-	/* exiting here: r1/r2 unchanged, r0/r3 destroyed */
-#endif
-
 #if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
-	/* check if we're a nested interrupt: if so, let the interrupted interrupt
-	 * handle the reschedule */
+	/* check if we're a nested interrupt: if so, let the interrupted
+	 * interrupt handle the reschedule */
 
 	lr r3, [_ARC_V2_AUX_IRQ_ACT]
 
@@ -129,7 +118,7 @@ SECTION_FUNC(TEXT, _firq_exit)
 	 * means that another bit is set so an interrupt was interrupted.
 	 */
 
-	breq.nd r3, 1, _check_if_current_is_the_task
+	breq r3, 1, _check_if_current_is_the_task
 
 	rtie
 
@@ -138,15 +127,15 @@ SECTION_FUNC(TEXT, _firq_exit)
 .balign 4
 _check_if_current_is_the_task:
 
-	ld r0, [r2, __tTCS_flags_OFFSET]
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
 	and.f r0, r0, PREEMPTIBLE
-	bnz.nd _check_if_a_fiber_is_ready
+	bnz _check_if_a_fiber_is_ready
 	rtie
 
 .balign 4
 _check_if_a_fiber_is_ready:
-	ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
-	brne.nd r0, 0, _firq_reschedule
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	brne r0, 0, _firq_reschedule
 	rtie
 
 .balign 4
@@ -177,23 +166,23 @@ _firq_reschedule:
 	st ilink, [sp, __tISF_pc_OFFSET] /* ilink into pc */
 
 	mov_s r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 	_save_callee_saved_regs
 
 	st _CAUSE_FIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	ld r2, [r1, __tNANO_fiber_OFFSET]
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
 
-	st r2, [r1, __tNANO_current_OFFSET]
-	ld r3, [r2, __tTCS_link_OFFSET]
-	st r3, [r1, __tNANO_fiber_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
 	add r3, r2, __tTCS_NOFLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/*
@@ -202,11 +191,11 @@ _firq_reschedule:
 	 */
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _firq_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _firq_return_from_firq
+	breq r3, _CAUSE_FIRQ, _firq_return_from_firq
 	nop
 
 	/* fall through */
@@ -214,7 +203,7 @@ _firq_reschedule:
 .balign 4
 _firq_return_from_coop:
 
-	ld r3, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r3, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
 
 	/* pc into ilink */
@@ -225,15 +214,15 @@ _firq_return_from_coop:
 	/*
 	 * There are only two interrupt lock states: locked and unlocked. When
 	 * entering _Swap(), they are always locked, so the IE bit is unset in
-	 * status32. If the incoming thread had them locked recursively, it means
-	 * that the IE bit should stay unset. The only time the bit has to change
-	 * is if they were not locked recursively.
+	 * status32. If the incoming thread had them locked recursively, it
+	 * means that the IE bit should stay unset. The only time the bit
+	 * has to change is if they were not locked recursively.
 	 */
 	and.f r3, r3, (1 << 4)
 	or.nz r0, r0, _ARC_V2_STATUS32_IE
 	sr r0, [_ARC_V2_STATUS32_P0]
 
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 	rtie
 
 .balign 4
@@ -279,4 +268,4 @@ SECTION_FUNC(TEXT, _firq_stack_setup)
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	kflag r0
 
-	j_s.nd [blink]
+	j_s [blink]

arch/arc/core/fault_s.S

@@ -49,6 +49,15 @@ GDATA(_firq_stack)
 SECTION_VAR(BSS, saved_stack_pointer)
 	.word 0
 
+#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
+#error "NUM_IRQ_PRIO_LEVELS==1 is not supported."
+/* The code below sets bit 1 in AUX_IRQ_ACT and thus requires
+ * priority 0 and 1 at a minimum. Supporting only 1 priority
+ * requires a change to this file but also changes to make
+ * FIRQ optional.
+ */
+#endif
+
 /*
  * @brief Fault handler installed in the fault and reserved vectors
  */
@@ -78,6 +87,15 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	 * a diagnostic message and halt.
 	 */
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
+
 	st sp, [saved_stack_pointer]
 	mov_s sp, _firq_stack
 	add sp, sp, CONFIG_FIRQ_STACK_SIZE
@@ -85,6 +103,11 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, __tISF_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
+
 	jl _Fault
 
 	/* if _Fault returns, restore the registers */
@@ -102,24 +125,102 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	 * Before invoking exception handler, the kernel switches to an exception
 	 * stack, which is really the FIRQ stack, to save the faulting thread's
 	 * registers. It can use the FIRQ stack because it knows it is unused
-	 * since it is save to assume that if an exception has happened in FIRQ
+	 * since it is safe to assume that if an exception has happened in FIRQ
 	 * handler, the problem is fatal and all the kernel can do is just print
 	 * a diagnostic message and halt.
 	 */
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
+
+#ifndef CONFIG_MICROKERNEL
 	st sp, [saved_stack_pointer]
 	mov_s sp, _firq_stack
 	add sp, sp, CONFIG_FIRQ_STACK_SIZE
+#endif
 
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, __tISF_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, __tISF_pc_OFFSET] /* eret into pc */
+
 	jl _irq_do_offload
 
+#ifdef CONFIG_MICROKERNEL
+	mov_s r1, _nanokernel
+	ld_s r2, [r1, __tNANO_current_OFFSET]
+#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
+	/* check if we're a nested interrupt: if so, let the
+	 * interrupted interrupt handle the reschedule
+	 */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
+	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is 0, it
+	 * means trap was taken from outside an interrupt handler.
+	 * But if it was inside, let that handler do the swap.
+	 */
+	breq r3, 0, _trap_check_for_swap
+_trap_return:
+	_pop_irq_stack_frame
+	rtie
+#endif
+
+.balign 4
+_trap_check_for_swap:
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
+	and.f r0, r0, PREEMPTIBLE
+	bnz _e_check_if_a_fiber_is_ready
+	b _trap_return
+
+.balign 4
+_e_check_if_a_fiber_is_ready:
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	brne r0, 0, _trap_reschedule
+	b _trap_return
+
+.balign 4
+_trap_reschedule:
+
+	_save_callee_saved_regs
+
+	st _CAUSE_RIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
+	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
+
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
+
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
+
+	/* clear AE bit to forget this was an exception */
+	lr r3, [_ARC_V2_STATUS32]
+	and r3,r3,(~_ARC_V2_STATUS32_AE)
+	kflag r3
+ 	/* pretend priority 1 int happened to use common handler */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	or r3,r3,2
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+	/* Assumption: r2 has current thread */
+	b _rirq_common_interrupt_swap
+#else
+	/* Nanokernel-only just returns from exception */
+
 	/* if _Fault returns, restore the registers */
 	_pop_irq_stack_frame
 
 	/* now restore the stack */
 	ld sp,[saved_stack_pointer]
 	rtie
+#endif
+
 #endif /* CONFIG_IRQ_OFFLOAD */

arch/arc/core/irq_manage.c

@@ -78,24 +78,23 @@ void _arch_irq_disable(unsigned int irq)
  *
  * @brief Set an interrupt's priority
  *
- * Valid values are from 0 to 15. Interrupts of priority 1 are not masked when
- * interrupts are locked system-wide, so care must be taken when using them. ISR
- * installed with priority 0 interrupts cannot make kernel calls.
- *
- * The priority is verified if ASSERT_ON is enabled.
+ * Lower values take priority over higher values. Special case priorities are
+ * expressed via mutually exclusive flags.
+
+ * The priority is verified if ASSERT_ON is enabled; max priority level
+ * depends on CONFIG_NUM_IRQ_PRIO_LEVELS.
  *
  * @return N/A
  */
 
-void _irq_priority_set(
-	unsigned int irq,
-	unsigned int prio
-)
+void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
+	ARG_UNUSED(flags);
+
 	int key = irq_lock();
 
-	__ASSERT(prio >= 0 && prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
-			 "invalid priority!");
+	__ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
+		 "invalid priority %d for irq %d", prio, irq);
 	_arc_v2_irq_unit_prio_set(irq, prio);
 	irq_unlock(key);
 }

arch/arc/core/isr_wrapper.S

@@ -209,7 +209,38 @@ SECTION_FUNC(TEXT, _isr_enter)
 	mov.nz r3, _rirq_exit
 	mov.nz r2, _rirq_enter
 
-	j_s.nd [r2]
+	j_s [r2]
+
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+GTEXT(_sys_k_event_logger_exit_sleep)
+
+.macro log_sleep_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_exit_sleep
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_sleep_k_event
+#endif
+#if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
+GTEXT(_sys_k_event_logger_interrupt)
+
+.macro log_interrupt_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_interrupt
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_interrupt_k_event
+#endif
 
 #if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
 .macro exit_tickless_idle
@@ -232,6 +263,8 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
+	log_interrupt_k_event
+	log_sleep_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	sub r0, r0, 16
@@ -239,11 +272,11 @@ SECTION_FUNC(TEXT, _isr_demux)
 	mov r1, _sw_isr_table
 	add3 r0, r1, r0   /* table entries are 8-bytes wide */
 
-	ld r1, [r0, 4] /* ISR into r1 */
+	ld_s r1, [r0, 4] /* ISR into r1 */
 	jl_s.d [r1]
 	ld_s r0, [r0] /* delay slot: ISR parameter into r0  */
 
 	/* back from ISR, jump to exit stub */
 	pop_s r3
-	j_s.nd [r3]
+	j_s [r3]
 	nop

arch/arc/core/offsets/offsets.c

@@ -39,7 +39,6 @@
 
 /* ARCv2-specific tNANO structure member offsets */
 GEN_OFFSET_SYM(tNANO, rirq_sp);
-GEN_OFFSET_SYM(tNANO, firq_regs);
 #ifdef CONFIG_SYS_POWER_MANAGEMENT
 GEN_OFFSET_SYM(tNANO, idle);
 #endif
@@ -102,12 +101,6 @@ GEN_OFFSET_SYM(tCalleeSaved, fp);
 GEN_OFFSET_SYM(tCalleeSaved, r30);
 GEN_ABSOLUTE_SYM(__tCalleeSaved_SIZEOF, sizeof(tCalleeSaved));
 
-/* ARCv2-specific registers-saved-in-FIRQ structure member offsets */
-GEN_OFFSET_SYM(tFirqRegs, lp_count);
-GEN_OFFSET_SYM(tFirqRegs, lp_start);
-GEN_OFFSET_SYM(tFirqRegs, lp_end);
-GEN_ABSOLUTE_SYM(__tFirqRegs_SIZEOF, sizeof(tFirqRegs));
-
 /* size of the struct tcs structure sans save area for floating point regs */
 GEN_ABSOLUTE_SYM(__tTCS_NOFLOAT_SIZEOF, sizeof(tTCS));
 

arch/arc/core/prep_c.c

@@ -29,51 +29,84 @@
 #include <stdint.h>
 #include <toolchain.h>
 #include <linker-defs.h>
+#include <arch/arc/v2/aux_regs.h>
+#include <nano_internal.h>
+
 
 /**
  *
- * @brief Clear BSS
+ * @brief Disable the i-cache if present
  *
- * This routine clears the BSS region, so all bytes are 0.
+ * For those ARC CPUs that have a i-cache present,
+ * invalidate the i-cache and then disable it.
  *
  * @return N/A
  */
 
-static void bssZero(void)
+static void disable_icache(void)
 {
-	volatile uint32_t *pBSS = (uint32_t *)&__bss_start;
-	unsigned int n;
+	unsigned int val;
 
-	for (n = 0; n < (unsigned int)&__bss_num_words; n++) {
-		pBSS[n] = 0;
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val &= 0xff; /* version field */
+	if (val == 0) {
+		return; /* skip if i-cache is not present */
 	}
+	_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
+	__asm__ __volatile__ ("nop");
+	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
 }
 
 /**
  *
- * @brief Copy the data section from ROM to RAM
+ * @brief Invalidate the data cache if present
  *
- * This routine copies the data section from ROM to RAM.
+ * For those ARC CPUs that have a data cache present,
+ * invalidate the data cache.
  *
  * @return N/A
  */
 
-#ifdef CONFIG_XIP
-static void dataCopy(void)
+static void invalidate_dcache(void)
 {
-	volatile uint32_t *pROM = (uint32_t *)&__data_rom_start;
-	volatile uint32_t *pRAM = (uint32_t *)&__data_ram_start;
-	unsigned int n;
+	unsigned int val;
 
-	for (n = 0; n < (unsigned int)&__data_num_words; n++) {
-		pRAM[n] = pROM[n];
+	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	val &= 0xff; /* version field */
+	if (val == 0) {
+		return; /* skip if d-cache is not present */
+	}
+	_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
+}
+
+
+/**
+ *
+ * @brief Adjust the vector table base
+ *
+ * Set the vector table base if the value found in the
+ * _ARC_V2_IRQ_VECT_BASE auxiliary register is different from the
+ * _VectorTable known by software. It is important to do this very early
+ * so that exception vectors can be handled.
+ *
+ * @return N/A
+ */
+
+static void adjust_vector_table_base(void)
+{
+	extern struct vector_table _VectorTable;
+	unsigned int vbr;
+	/* if the compiled-in vector table is different
+	 * from the base address known by the ARC CPU,
+	 * set the vector base to the compiled-in address.
+	 */
+	vbr = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
+	vbr &= 0xfffffc00;
+	if (vbr != (unsigned int)&_VectorTable) {
+		_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
+					(unsigned int)&_VectorTable);
 	}
 }
-#else
-static void dataCopy(void)
-{
-}
-#endif
 
 extern FUNC_NORETURN void _Cstart(void);
 /**
@@ -87,8 +120,11 @@ extern FUNC_NORETURN void _Cstart(void);
 
 void _PrepC(void)
 {
-	bssZero();
-	dataCopy();
+	disable_icache();
+	invalidate_dcache();
+	adjust_vector_table_base();
+	_bss_zero();
+	_data_copy();
 	_Cstart();
 	CODE_UNREACHABLE;
 }

arch/arc/core/regular_irq.S

@@ -34,6 +34,16 @@
 
 GTEXT(_rirq_enter)
 GTEXT(_rirq_exit)
+GTEXT(_rirq_common_interrupt_swap)
+
+#if CONFIG_NUM_IRQ_PRIO_LEVELS > 2
+#error "NUM_IRQ_PRIO_LEVELS>2 is not supported."
+/*
+ * Nesting of Regularing interrupts is not yet supported.
+ * If your SOC supports more than 2, set this value to 2.
+ */
+#endif
+
 
 /**
  *
@@ -57,7 +67,7 @@ SECTION_FUNC(TEXT, _rirq_enter)
 	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
 	kflag r2
 #endif
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 #if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS == 1
 	st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 	ld sp, [r1, __tNANO_rirq_sp_OFFSET]
@@ -77,7 +87,7 @@ SECTION_FUNC(TEXT, _rirq_enter)
 SECTION_FUNC(TEXT, _rirq_exit)
 
 	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 #if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS > 1
 	/* check if we're a nested interrupt: if so, let the interrupted interrupt
@@ -95,7 +105,7 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 */
 
 	cmp r0, r3
-	brgt.nd _rirq_return_from_rirq
+	brgt _rirq_return_from_rirq
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 #endif
 
@@ -108,12 +118,12 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 * b) needs to load it to restore the interrupted context.
 	 */
 
-	ld r0, [r2, __tTCS_flags_OFFSET]
+	ld_s r0, [r2, __tTCS_flags_OFFSET]
 	and.f r0, r0, PREEMPTIBLE
 	bz.d _rirq_no_reschedule
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 
-	ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
+	ld_s r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
 	cmp r0, 0
 	bz.d _rirq_no_reschedule
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
@@ -128,15 +138,18 @@ _rirq_reschedule:
 
 	/* incoming fiber is in r0: it becomes the new 'current' */
 	mov r2, r0
-	st r2, [r1, __tNANO_current_OFFSET]
-	ld r3, [r2, __tTCS_link_OFFSET]
-	st r3, [r1, __tNANO_fiber_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
+	st_s r3, [r1, __tNANO_fiber_OFFSET]
+
+_rirq_common_interrupt_swap:
+	/* r2 contains pointer to new thread */
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
 	add r3, r2, __tTCS_NOFLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/*
@@ -145,11 +158,11 @@ _rirq_reschedule:
 	 */
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _rirq_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _rirq_return_from_firq
+	breq r3, _CAUSE_FIRQ, _rirq_return_from_firq
 	nop
 
 	/* fall through */
@@ -160,12 +173,12 @@ _rirq_return_from_coop:
 	/* status32 and pc (blink) are already on the stack in the right order */
 
 	/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
-	ld r0, [sp, 4]
-	ld r3, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r0, [sp, 4]
+	ld_s r3, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
 	cmp r3, 0
 	or.ne r0, r0, _ARC_V2_STATUS32_IE
-	st r0, [sp, 4]
+	st_s r0, [sp, 4]
 
 	/* carve fake stack */
 
@@ -173,7 +186,7 @@ _rirq_return_from_coop:
 	                                  * b) a real value will be pushed in r0 */
 
 	/* push return value on stack */
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 	push_s r0
 
 	/*
@@ -182,7 +195,7 @@ _rirq_return_from_coop:
 	 * IRQ prologue. r13 thus has to be set to its correct value in the IRQ
 	 * stack frame.
 	 */
-	st r13, [sp, __tISF_r13_OFFSET]
+	st_s r13, [sp, __tISF_r13_OFFSET]
 
 	/* stack now has the IRQ stack frame layout, pointing to r0 */
 

arch/arc/core/reset.S

@@ -28,9 +28,15 @@
 #include <sections.h>
 #include <arch/cpu.h>
 
-#define _RAM_END (CONFIG_RAM_START + CONFIG_RAM_SIZE * 1024)
+#ifdef CONFIG_HARVARD
+#define _TOP_OF_MEMORY (CONFIG_DCCM_BASE_ADDRESS + CONFIG_DCCM_SIZE * 1024)
+/* harvard places the initial stack in the dccm memory */
+#else
+#define _TOP_OF_MEMORY (CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_SIZE * 1024)
+#endif
 
 GTEXT(__reset)
+GTEXT(__start)
 
 /**
  *
@@ -47,11 +53,12 @@ GTEXT(__reset)
  */
 
 SECTION_FUNC(TEXT,__reset)
+SECTION_FUNC(TEXT,__start)
 
 	/* lock interrupts: will get unlocked when switch to main task */
 	clri
 
-	/* setup a stack at the end of the RAM */
-	mov sp, _RAM_END
+	/* setup a stack at the end of MEMORY */
+	mov sp, _TOP_OF_MEMORY
 
 	j @_PrepC

arch/arc/core/swap.S

@@ -74,10 +74,10 @@ SECTION_FUNC(TEXT, _Swap)
 	/* interrupts are locked, interrupt key is in r0 */
 
 	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	ld_s r2, [r1, __tNANO_current_OFFSET]
 
 	/* save intlock key */
-	st r0, [r2, __tTCS_intlock_key_OFFSET]
+	st_s r0, [r2, __tTCS_intlock_key_OFFSET]
 	st _CAUSE_COOP, [r2, __tTCS_relinquish_cause_OFFSET]
 
 	/*
@@ -95,20 +95,20 @@ SECTION_FUNC(TEXT, _Swap)
 
 	_save_callee_saved_regs
 
-	ld r2, [r1, __tNANO_fiber_OFFSET]
-	breq.nd r2, 0, _swap_to_the_task
+	ld_s r2, [r1, __tNANO_fiber_OFFSET]
+	breq r2, 0, _swap_to_the_task
 
 .balign 4
 _swap_to_a_fiber:
 
-	ld r3, [r2, __tTCS_link_OFFSET]
+	ld_s r3, [r2, __tTCS_link_OFFSET]
 	b.d _finish_swapping_to_thread    /* always execute delay slot */
-	st r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
+	st_s r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
 
 .balign 4
 _swap_to_the_task:
 
-	ld r2, [r1, __tNANO_task_OFFSET]
+	ld_s r2, [r1, __tNANO_task_OFFSET]
 
 	/* fall through */
 
@@ -120,26 +120,26 @@ _finish_swapping_to_thread:
 #if 0
 /* don't save flags in tNANO: slower, error-prone, and might not even give
  * a speed boost where it's supposed to */
-	ld r3, [r2, __tTCS_flags_OFFSET]
-	st r3, [r1, __tNANO_flags_OFFSET]
+	ld_s r3, [r2, __tTCS_flags_OFFSET]
+	st_s r3, [r1, __tNANO_flags_OFFSET]
 #endif
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
 	add r3, r2, __tTCS_NOFLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, __tTCS_stack_top_OFFSET]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
-	st r2, [r1, __tNANO_current_OFFSET]
+	st_s r2, [r1, __tNANO_current_OFFSET]
 
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, __tTCS_relinquish_cause_OFFSET]
 
-	breq.nd r3, _CAUSE_RIRQ, _swap_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _swap_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _swap_return_from_firq
+	breq r3, _CAUSE_FIRQ, _swap_return_from_firq
 	nop
 
 	/* fall through to _swap_return_from_coop */
@@ -147,19 +147,12 @@ _finish_swapping_to_thread:
 .balign 4
 _swap_return_from_coop:
 
-	ld r1, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r1, [r2, __tTCS_intlock_key_OFFSET]
 	st  0, [r2, __tTCS_intlock_key_OFFSET]
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, __tTCS_return_value_OFFSET]
 
-	/*
-	 * Adjust the stack here in case we go to _return_from_exc: this allows
-	 * keeping handling both coop and irq cases in _return_from_exc without
-	 * adding extra logic.
-	 */
-	add_s sp, sp, 8
 	lr ilink, [_ARC_V2_STATUS32]
 	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
-	sub_s sp, sp, 8
 
 	pop_s blink /* pc into blink */
 	pop_s r3    /* status32 into r3 */
@@ -173,39 +166,32 @@ _swap_return_from_coop:
 _swap_return_from_rirq:
 _swap_return_from_firq:
 
-	_pop_irq_stack_frame
-
-	lr ilink, [_ARC_V2_STATUS32]
-	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
-
-	ld ilink, [sp, -4] /* status32 into ilink */
-#ifdef CONFIG_ARC_STACK_CHECKING
-	and ilink, ilink, 0x7fffbffe // keep SC off till we stop using under SP
-#else
-	and ilink, ilink, 0x7ffffffe // keep interrupts disabled until seti
-#endif
-	kflag ilink
-
-	ld ilink, [sp, -8] /* pc into ilink */
-
-#ifdef CONFIG_ARC_STACK_CHECKING
-	/* Enable stack checking now it is safe */
-	push_s r3
 	lr r3, [_ARC_V2_STATUS32]
-	bset r3, r3, _ARC_V2_STATUS32_SC_BIT
-	flag r3
-	pop_s r3
-#endif
-	j.d [ilink]
-	seti (_ARC_V2_DEF_IRQ_LEVEL | (1 << 4))
+	bbit1 r3, _ARC_V2_STATUS32_AE_BIT, _return_from_exc_irq
+
+	/* pretend interrupt happened to use rtie instruction */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	brne r3,0,_swap_already_in_irq
+
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+_swap_already_in_irq:
+	rtie
 
 .balign 4
+_return_from_exc_irq:
+	_pop_irq_stack_frame
+	sub_s sp, sp, 8
+
 _return_from_exc:
+
 	/* put the return address to eret */
-	ld ilink, [sp, -8] /* pc into ilink */
+	ld ilink, [sp] /* pc into ilink */
 	sr ilink, [_ARC_V2_ERET]
 
 	/* put status32 into estatus */
-	ld ilink, [sp, -4] /* status32 into ilink */
+	ld ilink, [sp, 4] /* status32 into ilink */
 	sr ilink, [_ARC_V2_ERSTATUS]
+	add_s sp, sp, 8
 	rtie

arch/arc/core/swap_macros.h

@@ -36,9 +36,9 @@ extern "C" {
 	sub_s sp, sp, __tCalleeSaved_SIZEOF
 
 	/* save regs on stack */
-	st r13, [sp, __tCalleeSaved_r13_OFFSET]
-	st r14, [sp, __tCalleeSaved_r14_OFFSET]
-	st r15, [sp, __tCalleeSaved_r15_OFFSET]
+	st_s r13, [sp, __tCalleeSaved_r13_OFFSET]
+	st_s r14, [sp, __tCalleeSaved_r14_OFFSET]
+	st_s r15, [sp, __tCalleeSaved_r15_OFFSET]
 	st r16, [sp, __tCalleeSaved_r16_OFFSET]
 	st r17, [sp, __tCalleeSaved_r17_OFFSET]
 	st r18, [sp, __tCalleeSaved_r18_OFFSET]
@@ -62,9 +62,9 @@ extern "C" {
 	/* restore stack pointer from struct tcs */
 	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
 
-	ld r13, [sp, __tCalleeSaved_r13_OFFSET]
-	ld r14, [sp, __tCalleeSaved_r14_OFFSET]
-	ld r15, [sp, __tCalleeSaved_r15_OFFSET]
+	ld_s r13, [sp, __tCalleeSaved_r13_OFFSET]
+	ld_s r14, [sp, __tCalleeSaved_r14_OFFSET]
+	ld_s r15, [sp, __tCalleeSaved_r15_OFFSET]
 	ld r16, [sp, __tCalleeSaved_r16_OFFSET]
 	ld r17, [sp, __tCalleeSaved_r17_OFFSET]
 	ld r18, [sp, __tCalleeSaved_r18_OFFSET]
@@ -112,9 +112,9 @@ extern "C" {
 
 	mov r0, lp_count
 	st_s r0, [sp, __tISF_lp_count_OFFSET]
-	lr r0, [_ARC_V2_LP_START]
-	st_s r0, [sp, __tISF_lp_start_OFFSET]
+	lr r1, [_ARC_V2_LP_START]
 	lr r0, [_ARC_V2_LP_END]
+	st_s r1, [sp, __tISF_lp_start_OFFSET]
 	st_s r0, [sp, __tISF_lp_end_OFFSET]
 
 .endm
@@ -129,9 +129,9 @@ extern "C" {
 
 	ld_s r0, [sp, __tISF_lp_count_OFFSET]
 	mov lp_count, r0
-	ld_s r0, [sp, __tISF_lp_start_OFFSET]
-	sr r0, [_ARC_V2_LP_START]
+	ld_s r1, [sp, __tISF_lp_start_OFFSET]
 	ld_s r0, [sp, __tISF_lp_end_OFFSET]
+	sr r1, [_ARC_V2_LP_START]
 	sr r0, [_ARC_V2_LP_END]
 
 	ld_s r13, [sp, __tISF_r13_OFFSET]

arch/arc/core/sys_fatal_error_handler.c

@@ -73,7 +73,7 @@ void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF * pEsf)
 	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
-	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential(NULL)) {
+	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential()) {
 		PRINTK("Fatal fault in %s ! Spinning...\n",
 		       NANO_CTX_ISR == curCtx
 			       ? "ISR"

arch/arc/core/thread.c

@@ -101,7 +101,8 @@ static ALWAYS_INLINE void thread_monitor_init(struct tcs *tcs)
  *
  * @return N/A
  */
-void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
+void _new_thread(char *pStackMem, unsigned stackSize,
+		 void *uk_task_ptr, _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned options)
 {
@@ -154,6 +155,13 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	 */
 	tcs->entry = (struct __thread_entry *)(pInitCtx);
 #endif
+
+#ifdef CONFIG_MICROKERNEL
+	tcs->uk_task_ptr = uk_task_ptr;
+#else
+	ARG_UNUSED(uk_task_ptr);
+#endif
+
 	/*
 	 * intlock_key is constructed based on ARCv2 ISA Programmer's
 	 * Reference Manual CLRI instruction description:

arch/arc/core/vector_table.c

@@ -75,4 +75,3 @@ struct vector_table _VectorTable _GENERIC_SECTION(.exc_vector_table) = {
 	0
 };
 
-extern struct vector_table __start _ALIAS_OF(_VectorTable);

arch/arc/defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARC=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
-CONFIG_SOC_GENERIC_ARC=y
 CONFIG_CPU_ARCEM4=y
 CONFIG_CPU_ARCV2=y
 CONFIG_ARCV2_INTERRUPT_UNIT=y

arch/arc/include/kernel_event_logger_arch.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief Kernel event logger support for ARM
+ */
+
+#ifndef __KERNEL_EVENT_LOGGER_ARCH_H__
+#define __KERNEL_EVENT_LOGGER_ARCH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the identification of the current interrupt.
+ *
+ * This routine obtain the key of the interrupt that is currently processed
+ * if it is called from a ISR context.
+ *
+ * @return The key of the interrupt that is currently being processed.
+ */
+int _sys_current_irq_key_get(void)
+{
+	return _INTERRUPT_CAUSE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __KERNEL_EVENT_LOGGER_ARCH_H__ */

arch/arc/include/nano_private.h

@@ -130,14 +130,6 @@ struct callee_saved {
 };
 typedef struct callee_saved tCalleeSaved;
 
-/* registers saved by software when taking a FIRQ */
-struct firq_regs {
-	uint32_t lp_count;
-	uint32_t lp_start;
-	uint32_t lp_end;
-};
-typedef struct firq_regs tFirqRegs;
-
 #endif /* _ASMLANGUAGE */
 
 /* Bitmask definitions for the struct tcs->flags bit field */
@@ -145,8 +137,8 @@ typedef struct firq_regs tFirqRegs;
 #define FIBER          0x000
 #define TASK           0x001 /* 1 = task, 0 = fiber   */
 
-#define INT_ACTIVE     0x002 /* 1 = execution context is interrupt handler */
-#define EXC_ACTIVE     0x004 /* 1 = executino context is exception handler */
+#define INT_ACTIVE     0x002 /* 1 = executing context is interrupt handler */
+#define EXC_ACTIVE     0x004 /* 1 = executing context is exception handler */
 #define USE_FP         0x010 /* 1 = thread uses floating point unit */
 #define PREEMPTIBLE    0x020 /* 1 = preemptible thread */
 #define ESSENTIAL      0x200 /* 1 = system thread that must not abort */
@@ -197,6 +189,9 @@ struct tcs {
 #ifdef CONFIG_ARC_STACK_CHECKING
 	uint32_t stack_top;
 #endif
+#ifdef CONFIG_MICROKERNEL
+	void *uk_task_ptr;
+#endif
 };
 
 struct s_NANO {
@@ -223,7 +218,6 @@ struct s_NANO {
 	 * there is no need to track it in _nanokernel.
 	 */
 
-	struct firq_regs firq_regs;
 #if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
 	sys_dlist_t timeout_q;
 	int32_t task_timeout;
@@ -278,6 +272,21 @@ static ALWAYS_INLINE int _IS_IN_ISR(void)
 	return ((act & 0xffff) != 0);
 }
 
+/**
+ *
+ * @bried Indicates the interrupt number of the highest priority
+ * active interrupt
+ *
+ * @return IRQ number
+ */
+static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
+{
+	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
+
+	return irq_num;
+}
+
+
 extern void nanoCpuAtomicIdle(unsigned int);
 extern void _thread_entry_wrapper(void);
 

arch/arc/include/start_task_arch.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief ARC nanokernel declarations to start a task
+ *
+ * ARC-specific parts of start_task().
+ *
+ * Currently empty, only here for abstraction.
+ */
+
+#ifndef _START_TASK_ARCH__H_
+#define _START_TASK_ARCH__H_
+
+#include <toolchain.h>
+#include <sections.h>
+
+#include <micro_private.h>
+#include <nano_private.h>
+#include <microkernel/task.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _START_TASK_ARCH(task, opt_ptr) \
+	do {/* nothing */              \
+	} while ((0))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _START_TASK_ARCH__H_ */

arch/arc/include/v2/cache.h

@@ -49,7 +49,14 @@ static ALWAYS_INLINE void _icache_setup(void)
 		CACHE_DIRECT | /* direct mapping (one-way assoc.) */
 		CACHE_ENABLE   /* i-cache enabled */
 	);
-	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+	uint32_t val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val &= 0xff;
+	if (val != 0) {
+		/* configure i-cache if present */
+		_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+	}
 }
 
 #endif /* _ASMLANGUAGE */

arch/arc/soc/em11d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em11d/Kconfig.defconfig

@@ -0,0 +1,260 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_EM11D
+
+config SOC
+	default em11d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_REGULAR_IRQ_PRIO_LEVELS
+	# This processor supports 3 Regular Interrupt priority level (1-3).
+	# TODO: But regular irq nesting is not implemented -- so use 1.
+	default 1
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em11d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x10000000 if NSIM
+	default 0x10000000
+
+config SRAM_SIZE
+	default 131072 if NSIM
+	default 131072
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 64
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 64
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM11D

arch/arc/soc/em11d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM11D
+	bool "Synopsys ARC EM11D"

arch/arc/soc/em11d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mARCv2EM) \
+                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)

arch/arc/soc/em11d/linker.ld

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM11D platform.
+ */
+
+/*
+ * DRAM base address and size
+ *
+ * DRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
+/* TODO: Using SRAM config for now, even though this is really DRAM. */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/em11d/soc.c

@@ -0,0 +1,46 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ */
+
+#include <nanokernel.h>
+#include "soc.h"
+#include <init.h>
+
+
+/**
+ *
+ * @brief perform basic hardware initialization
+ *
+ * Hardware initialized:
+ * - interrupt unit
+ *
+ * RETURNS: N/A
+ */
+static int em11d_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_v2_irq_unit_init();
+	return 0;
+}
+
+SYS_INIT(em11d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em11d/soc.h

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+/* ARCv2 timer 0 configuration settings for the system clock */
+#ifdef CONFIG_NANOKERNEL
+#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
+#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
+#endif /* CONFIG_NANOKERNEL */
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+#define SPI_DW_IRQ_FLAGS     0
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS					0 /* Default */
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em11d/soc_config.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em9d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em9d/Kconfig.defconfig

@@ -0,0 +1,261 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_EM9D
+
+config SOC
+	default em9d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_REGULAR_IRQ_PRIO_LEVELS
+	# This processor supports 3 Regular Interrupt priority level (1-3).
+	# TODO: But regular irq nesting is not implemented -- so use 1.
+	default 1
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool y
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em9d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x00000000 if NSIM
+	default 0x00000000
+
+config SRAM_SIZE
+	default 0 if NSIM
+	default 0
+	# em9d has no SRAM so size is 0.
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 256
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 128
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM9D

arch/arc/soc/em9d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM9D
+	bool "Synopsys ARC EM9D"

arch/arc/soc/em9d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mARCv2EM) \
+                   $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)

arch/arc/soc/em9d/linker.ld

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM9D platform.
+ */
+
+/*
+ * ICCM base address and size
+ *
+ * ICCM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker_harvard.ld>
+

arch/arc/soc/em9d/soc.c

@@ -0,0 +1,46 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ */
+
+#include <nanokernel.h>
+#include "soc.h"
+#include <init.h>
+
+
+/**
+ *
+ * @brief perform basic hardware initialization
+ *
+ * Hardware initialized:
+ * - interrupt unit
+ *
+ * RETURNS: N/A
+ */
+static int em9d_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_arc_v2_irq_unit_init();
+	return 0;
+}
+
+SYS_INIT(em9d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/em9d/soc.h

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+/* ARCv2 timer 0 configuration settings for the system clock */
+#ifdef CONFIG_NANOKERNEL
+#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
+#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
+#endif /* CONFIG_NANOKERNEL */
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+#define SPI_DW_IRQ_FLAGS     0
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS					0 /* Default */
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em9d/soc_config.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_ss/Kconfig

@@ -0,0 +1,28 @@
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if ARC && SOC_QUARK_SE_SS
+
+if IPM
+config QUARK_SE_SS_IPM_IRQ_PRI
+	int "IPM interrupt priority"
+	default 1
+	help
+	Priority level for interrupts coming in from the inter-processor
+	mailboxes.
+
+endif # IPM
+endif # SOC_QUARK_SE_SS

arch/arc/soc/quark_se_ss/Kconfig.defconfig

@@ -29,193 +29,160 @@ config NUM_REGULAR_IRQ_PRIO_LEVELS
 	# This processor supports only 1 Regular Interrupt priority level (1).
 	default 1
 
-config  NUM_IRQS
+config NUM_IRQS
 	# must be > the highest interrupt number used
 	default 68
 
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 32000000
 
-config RAM_START
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x40000000
+
+config FLASH_SIZE
+	default 152
+
+config SRAM_BASE_ADDRESS
 	default 0x4000 if NSIM
 	default 0xa8000400
 
-config RAM_SIZE
+config SRAM_SIZE
 	default 16 if NSIM
 	default 24
 
+config ICCM_BASE_ADDRESS
+	default 0xFFFFFFFF
+
+config ICCM_SIZE
+	default 0
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 8
+
+config QMSI
+	def_bool y
+
+config QMSI_BUILTIN
+	def_bool y
+
 if GPIO
 
-config GPIO_DW
+config GPIO_QMSI_SS
 	def_bool y
 
-if GPIO_DW
+if GPIO_QMSI_SS
 
-config GPIO_DW_BOTHEDGES_SUPPORT
-	default n
-
-config GPIO_DW_0
+config GPIO_QMSI_SS_0
 	def_bool y
 
-if GPIO_DW_0
+if GPIO_QMSI_SS_0
 
-config GPIO_DW_0_BASE_ADDR
-	default 0x80017800
-config GPIO_DW_0_IRQ
-	default 20
-config GPIO_DW_0_PRI
-	default 2
-config GPIO_DW_0_BITS
-	default 8
+config GPIO_QMSI_SS_0_PRI
+	default 1
 
-endif # GPIO_DW_0
+endif # GPIO_QMSI_SS_0
 
-config GPIO_DW_1
+config GPIO_QMSI_SS_1
 	def_bool y
 
-if GPIO_DW_1
+if GPIO_QMSI_SS_1
 
-config GPIO_DW_1_BASE_ADDR
-	default 0x80017900
-config GPIO_DW_1_IRQ
-	default 21
-config GPIO_DW_1_PRI
-	default 2
-config GPIO_DW_1_BITS
-	default 8
+config GPIO_QMSI_SS_1_PRI
+	default 1
 
-endif # GPIO_DW_1
+endif # GPIO_QMSI_SS_1
 
-endif # GPIO_DW
+endif # GPIO_QMSI_SS
 
 endif # GPIO
 
+
 if I2C
 
-config I2C_QUARK_SE_SS
+config I2C_QMSI_SS
 	def_bool y
 
-if I2C_QUARK_SE_SS
-
-config I2C_QUARK_SE_SS_0
+config I2C_0
 	def_bool y
 
-if I2C_QUARK_SE_SS_0
+config I2C_0_NAME
+	default "I2C_0"
 
-config I2C_QUARK_SE_SS_0_NAME
-	default "I2C0"
-
-config I2C_QUARK_SE_SS_0_DEFAULT_CFG
+config I2C_0_DEFAULT_CFG
 	default 0x12
 
-endif # I2C_QUARK_SE_SS_0
+config I2C_0_IRQ_PRI
+	default 2
 
-if I2C_QUARK_SE_SS_1
+if I2C_1
 
-config I2C_QUARK_SE_SS_1_NAME
-	default "I2C1"
+config I2C_1_NAME
+	default "I2C_1"
 
-config I2C_QUARK_SE_SS_1_DEFAULT_CFG
+config I2C_1_DEFAULT_CFG
 	default 0x12
 
-endif # I2C_QUARK_SE_SS_1
+config I2C_1_IRQ_PRI
+	default 2
+
+endif # I2C_1
 
-endif # I2C_QUARK_SE_SS
 
 endif # I2C
 
-if UART_NS16550
 
-config UART_NS16550_PORT_0
-        def_bool y
+if UART_QMSI
+config UART_QMSI_0
+	def_bool y
 
-if UART_NS16550_PORT_0
+if UART_QMSI_0
 
-config UART_NS16550_PORT_0_NAME
-        default "UART_0"
-config UART_NS16550_PORT_0_IRQ_PRI
-        default 1
-config UART_NS16550_PORT_0_BAUD_RATE
-        default 115200
-config UART_NS16550_PORT_0_OPTIONS
-        default 0
+config UART_QMSI_0_IRQ_PRI
+	default 3
 
-endif # UART_NS16550_PORT_0
+endif # UART_QMSI_0
 
-config UART_NS16550_PORT_1
-        def_bool y
+config UART_QMSI_1
+	def_bool y
 
-if UART_NS16550_PORT_1
+if UART_QMSI_1
 
-config UART_NS16550_PORT_1_NAME
-        default "UART_1"
-config UART_NS16550_PORT_1_IRQ_PRI
-        default 1
-config UART_NS16550_PORT_1_BAUD_RATE
-        default 115200
-config UART_NS16550_PORT_1_OPTIONS
-        default 0
+config UART_QMSI_1_IRQ_PRI
+	default 3
 
-endif # UART_NS16550_PORT_1
+endif # UART_QMSI_1
 
-endif # UART_NS16550
+endif # UART_QMSI
 
 if UART_CONSOLE
 
 config UART_CONSOLE_ON_DEV_NAME
-        default "UART_1"
+	default "UART_1"
 
 endif
 
 if SPI
 
-config SPI_DW
+config SPI_QMSI_SS
 	def_bool y
 
-if SPI_DW
-
-config SPI_DW_CLOCK_GATE
-	def_bool n
-
-config SPI_DW_PORT_0
+config SPI_0
 	def_bool y
 
-if SPI_DW_PORT_0
-
-config SPI_DW_PORT_0_PRI
+config SPI_0_IRQ_PRI
 	default 1
-config SPI_DW_PORT_0_REGS
-	default 0x80010000
-config SPI_DW_PORT_0_ERROR_IRQ
-	default 30
-config SPI_DW_PORT_0_RX_IRQ
-	default 31
-config SPI_DW_PORT_0_TX_IRQ
-	default 32
-
-endif # SPI_DW_PORT_0
-
-config SPI_DW_PORT_1
+config SPI_1
 	def_bool y
 
-if SPI_DW_PORT_1
-
-config SPI_DW_PORT_1_PRI
+config SPI_1_IRQ_PRI
 	default 1
-config SPI_DW_PORT_1_REGS
-	default 0x80010100
-config SPI_DW_PORT_1_ERROR_IRQ
-	default 33
-config SPI_DW_PORT_1_RX_IRQ
-	default 34
-config SPI_DW_PORT_1_TX_IRQ
-	default 35
-
-endif # SPI_DW_PORT_1
-
-endif # SPI_DW
-
 endif # SPI
 
+
 endif #SOC_QUARK_SE_ARC

arch/arc/soc/quark_se_ss/Kconfig.soc

@@ -1,4 +1,5 @@
 
 config SOC_QUARK_SE_SS
-        bool "Intel Quark SE - Sensor Sub System"
+	bool "Intel Quark SE - Sensor Sub System"
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_QMSI

arch/arc/soc/quark_se_ss/Makefile

@@ -1,7 +1,5 @@
-
-arch-cflags = $(call cc-option,-mARCv2EM) \
+soc-cflags = $(call cc-option,-mARCv2EM) \
                    $(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
-
-KBUILD_AFLAGS += $(arch-cflags)
-KBUILD_CFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
+soc-aflags = $(soc-cflags)
+soc-cxxflags = $(soc-cflags)
+soc-cflags += -DQM_SENSOR=1

arch/arc/soc/quark_se_ss/linker.ld

@@ -20,8 +20,8 @@
  */
 
 /* Flash base address and size */
-#define FLASH_START     0x40000000  /* Flash bank 1 */
-#define FLASH_SIZE      152K
+#define FLASH_START     CONFIG_FLASH_BASE_ADDRESS  /* Flash bank 1 */
+#define FLASH_SIZE      CONFIG_FLASH_SIZE
 
 /*
  * SRAM base address and size
@@ -29,11 +29,11 @@
  * Internal SRAM includes the exception vector table at reset, which is at
  * the beginning of the region.
  */
-#define SRAM_START		CONFIG_RAM_START
-#define SRAM_SIZE		CONFIG_RAM_SIZE
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
 
 /* Data Closely Coupled Memory (DCCM) base address and size */
-#define DCCM_START		0x80000000
-#define DCCM_SIZE		8K
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
 
-#include <arch/arc/v2/linker.cmd>
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/quark_se_ss/soc.c

@@ -26,10 +26,6 @@
 #include <init.h>
 #include <quark_se/shared_mem.h>
 
-/* Cannot use microkernel, since only nanokernel is supported */
-#if defined(CONFIG_MICROKERNEL)
-#error "Microkernel support is not available"
-#endif
 
 /**
  *

arch/arc/soc/quark_se_ss/soc.h

@@ -58,16 +58,18 @@
 #define IRQ_I2C1_TX_REQ 23
 #define IRQ_I2C1_STOP_DET 24
 #define IRQ_I2C1_ERR 25
-#define IRQ_SPI0_ERR_INT 26
-#define IRQ_SPI0_RX_AVAIL 27
-#define IRQ_SPI0_TX_REQ 28
-#define IRQ_SPI1_ERR_INT 29
-#define IRQ_SPI1_RX_AVAIL 30
-#define IRQ_SPI1_TX_REQ 31
-#define IRQ_ADC_IRQ 32
-#define IRQ_ADC_ERR 33
-#define IRQ_GPIO0_INTR 34
-#define IRQ_GPIO1_INTR 35
+#define IRQ_SPI0_ERR_INT 30
+#define IRQ_SPI0_RX_AVAIL 31
+#define IRQ_SPI0_TX_REQ 32
+
+#define IRQ_SPI1_ERR_INT 33
+#define IRQ_SPI1_RX_AVAIL 34
+#define IRQ_SPI1_TX_REQ 35
+
+#define IRQ_ADC_ERR 18
+#define IRQ_ADC_IRQ 19
+#define IRQ_GPIO0_INTR 20
+#define IRQ_GPIO1_INTR 21
 #define IRQ_I2C_MST0_INTR 36
 #define IRQ_I2C_MST1_INTR 37
 #define IRQ_SPI_MST0_INTR 38
@@ -113,12 +115,6 @@
 #define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
 #endif /* CONFIG_NANOKERNEL */
 
-#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
-#define CONFIG_ARCV2_TIMER0_INT_PRI 0
-
-#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI 1
-
 #define INT_ENABLE_ARC					~(0x00000001 << 8)
 #define INT_ENABLE_ARC_BIT_POS				(8)
 
@@ -148,8 +144,22 @@
 /*
  * GPIO
  */
-#define GPIO_DW_PORT_0_INT_MASK				(SCSS_REGISTER_BASE + 0x408)
-#define GPIO_DW_PORT_1_INT_MASK				(SCSS_REGISTER_BASE + 0x40C)
+#define GPIO_DW_IO_ACCESS
+
+#define GPIO_DW_0_BASE_ADDR			0x80017800
+#define GPIO_DW_0_IRQ				20
+#define GPIO_DW_0_BITS				8
+#define GPIO_DW_PORT_0_INT_MASK			(SCSS_REGISTER_BASE + 0x408)
+
+#define GPIO_DW_1_BASE_ADDR			0x80017900
+#define GPIO_DW_1_IRQ				21
+#define GPIO_DW_1_BITS				8
+#define GPIO_DW_PORT_1_INT_MASK			(SCSS_REGISTER_BASE + 0x40C)
+
+#if defined(CONFIG_IOAPIC)
+#define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#define GPIO_DW_1_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#endif
 
 /*
  * UART
@@ -167,6 +177,10 @@
 /*
  * SPI
  */
+
+#define SPI_DW_PORT_0_REGS				0x80010000
+#define SPI_DW_PORT_1_REGS				0x80010100
+
 #define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
 #define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
 #define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
@@ -175,6 +189,8 @@
 #define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
 #define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
 
+#define SPI_DW_IRQ_FLAGS				0
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _BOARD__H_ */

arch/arc/soc/quark_se_ss/soc_config.c

@@ -24,7 +24,7 @@
 
 static int arc_quark_se_ipm_init(void)
 {
-	IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, QUARK_SE_IPM_INTERRUPT_PRI,
+	IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, CONFIG_QUARK_SE_SS_IPM_IRQ_PRI,
 		    quark_se_ipm_isr, NULL, 0);
 	irq_enable(QUARK_SE_IPM_INTERRUPT);
 	return 0;
@@ -33,9 +33,10 @@ static int arc_quark_se_ipm_init(void)
 static struct quark_se_ipm_controller_config_info ipm_controller_config = {
 	.controller_init = arc_quark_se_ipm_init
 };
-DEVICE_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
+DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
 				NULL, &ipm_controller_config,
-				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+				SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+				&ipm_quark_se_api_funcs);
 
 #if CONFIG_IPM_CONSOLE_SENDER
 #include <console/ipm_console.h>

arch/arm/Kbuild

@@ -2,5 +2,10 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y := ${subdir-ccflags-y}
 
-obj-y += soc/$(SOC_NAME)/
+ifneq ($(SOC_FAMILY),)
+obj-y += soc/$(SOC_FAMILY)/
+else
+obj-y += soc/$(SOC_PATH)/
+endif
+
 obj-y += core/

arch/arm/Kconfig

@@ -18,7 +18,7 @@
 
 choice
 	prompt "ARM SoC Selection"
-	default SOC_FSL_FRDM_K64F
+	default SOC_SERIES_KINETIS_K6X
 	depends on ARM
 
 	source "arch/arm/soc/*/Kconfig.soc"
@@ -37,7 +37,7 @@ config ARCH_DEFCONFIG
 
 source "arch/arm/core/Kconfig"
 
-menu "Platform Configuration"
+menu "Board Configuration"
 
 source "arch/arm/soc/*/Kconfig"
 

arch/arm/Makefile

@@ -1,15 +1,54 @@
 KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 cflags-$(CONFIG_LTO) += $(call cc-option,-flto,)
 
+cflags-cortex-m0 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m0) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m0+ = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m0plus) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m1 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m1) \
+			$(call cc-option,-mthumb -march=armv6-m)
+cflags-cortex-m3 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m3) \
+			$(call cc-option,-mthumb -march=armv7-m)
+cflags-cortex-m4 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m4) \
+			$(call cc-option,-mthumb -march=armv7e-m)
+
+ifeq ($(CONFIG_FLOAT), y)
+ifeq ($(CONFIG_FP_SOFTABI), y)
+cflags-cortex-m4 += $(call cc-option,-mfloat-abi=softfp -mfpu=fpv4-sp-d16)
+endif
+ifeq ($(CONFIG_FP_HARDABI), y)
+cflags-cortex-m4 += $(call cc-option,-mfloat-abi=hard -mfpu=fpv4-sp-d16)
+endif
+endif
+
+cflags-cortex-m7 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m7) \
+			$(call cc-option,-mthumb -march=armv7e-m)
+
+aflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+cflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+cxxflags-$(CONFIG_CPU_CORTEX_M3) += $(cflags-cortex-m3)
+
+aflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+cflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+cxxflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
+
+
+KBUILD_AFLAGS += $(aflags-y)
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)
 
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)
+
 QEMU_CPU_TYPE_arm = cortex-m3
 QEMU_FLAGS_arm = -cpu  $(QEMU_CPU_TYPE_arm) \
-		-machine lm3s6965evb -nographic
+		-machine lm3s6965evb -nographic -vga none
 QEMU_arm = qemu-system-arm
 
 export QEMU_FLAGS_arm QEMU_arm

arch/arm/core/Kconfig

@@ -31,6 +31,61 @@ config CPU_CORTEX_M
 	help
 	This option signifies the use of a CPU of the Cortex-M family.
 
+config CPU_HAS_FPU
+	# Hidden config selected by CPU family
+	bool
+	default n
+	help
+	This option is enabled when the CPU has a hardware floating point
+	unit.
+
+menu "Floating Point Options"
+depends on CPU_HAS_FPU
+
+config	FLOAT
+	bool
+	prompt "Floating point registers"
+	default n
+	help
+	This option allows tasks and fibers to use the floating point registers.
+	By default, only a single task or fiber may use the registers.
+
+	Disabling this option means that any task or fiber that uses a
+	floating point register will get a fatal exception.
+
+config	FP_SHARING
+	bool
+	prompt "Floating point register sharing"
+	depends on FLOAT
+	default n
+	help
+	This option allows multiple tasks and fibers to use the floating point
+	registers.
+
+choice
+	prompt "Floating point ABI"
+	default FP_HARDABI
+	depends on FLOAT
+
+config FP_HARDABI
+	bool "Floating point Hard ABI"
+	depends on FLOAT
+	help
+	This option selects the Floating point ABI in which hardware floating
+	point instructions are generated and uses FPU-specific calling
+	conventions
+
+config FP_SOFTABI
+	bool "Floating point Soft ABI"
+	depends on FLOAT
+	help
+	This option selects the Floating point ABI in which hardware floating
+	point instructions are generated but soft-float calling conventions.
+
+endchoice
+
+endmenu
+
 if CPU_CORTEX_M
 source "arch/arm/core/cortex_m/Kconfig"
 endif

arch/arm/core/Makefile

@@ -3,7 +3,7 @@ ccflags-y += -I$(srctree)/kernel/microkernel/include
 
 asflags-y := ${ccflags-y}
 
-obj-y = atomic.o exc_exit.o irq_init.o \
+obj-y = exc_exit.o irq_init.o \
 	fiber_abort.o swap.o \
 	fault.o gdb_stub_irq_vector_table.o \
 	irq_manage.o thread.o cpu_idle.o \

arch/arm/core/atomic.S

@@ -1,415 +0,0 @@
-/*
- * Copyright (c) 2013-2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief ARM atomic operations library
- *
- * This library provides routines to perform a number of atomic operations
- * on a memory location: add, subtract, increment, decrement, bitwise OR,
- * bitwise NOR, bitwise AND, bitwise NAND, set, clear and compare-and-swap.
- */
-
-#define _ASMLANGUAGE
-
-#include <toolchain.h>
-#include <sections.h>
-
-_ASM_FILE_PROLOGUE
-
-/* exports */
-
-GTEXT(atomic_set)
-GTEXT(atomic_get)
-GTEXT(atomic_add)
-GTEXT(atomic_nand)
-GTEXT(atomic_and)
-GTEXT(atomic_or)
-GTEXT(atomic_xor)
-GTEXT(atomic_clear)
-GTEXT(atomic_dec)
-GTEXT(atomic_inc)
-GTEXT(atomic_sub)
-GTEXT(atomic_cas)
-
-/**
- *
- * @brief Atomically clear a memory location
- *
- * This routine atomically clears the contents of <target> and returns the old
- * value that was in <target>.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_clear
- *    (
- *    atomic_t *target	/@ memory location to clear @/
- *    )
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_clear_set, atomic_clear)
-	MOV	r1, #0
-	/* fall through into atomic_set */
-
-/**
- *
- * @brief Atomically set a memory location
- *
- * This routine atomically sets the contents of <target> to <value> and returns
- * the old value that was in <target>.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_set
- *    (
- *    atomic_t *target,	/@ memory location to set @/
- *    atomic_val_t value	/@ set with this value @/
- *    )
- *
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_clear_set, atomic_set)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	STREX	r12, r1, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-
-	BNE	atomic_set	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Get the value of a shared memory atomically
- *
- * This routine atomically retrieves the value in *target
- *
- * long atomic_get
- *     (
- *     atomic_t * target    /@ address of atom to be retrieved @/
- *     )
- *
- * RETURN: value read from address target.
- *
- */
-
-SECTION_FUNC(TEXT, atomic_get)
-	LDR	r0, [r0]
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically increment a memory location
- *
- * This routine atomically increments the value in <target>.  The operation is
- * done using unsigned integer arithmetic.  Various CPU architectures may impose
- * restrictions with regards to the alignment and cache attributes of the
- * atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_inc
- *    (
- *    atomic_t *target,	/@ memory location to increment @/
- *    )
- *
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_inc)
-	MOV	r1, #1
-	/* fall through into atomic_add */
-
-/**
- *
- * @brief Atomically add a value to a memory location
- *
- * This routine atomically adds the contents of <target> and <value>, placing
- * the result in <target>. The operation is done using signed integer arithmetic.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_add
- *    (
- *    atomic_t *target,	/@ memory location to add to @/
- *    atomic_val_t value	/@ value to add @/
- *    )
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_inc_add, atomic_add)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	ADD	r3, r2, r1	/* add word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-
-	BNE	atomic_add	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically decrement a memory location
- *
- * This routine atomically decrements the value in <target>.  The operation is
- * done using unsigned integer arithmetic.  Various CPU architectures may impose
- * restrictions with regards to the alignment and cache attributes of the
- * atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_dec
- *    (
- *    atomic_t *target,	/@ memory location to decrement @/
- *    )
- *
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_decSub, atomic_dec)
-	MOV   r1, #1
-	/* fall through into atomic_sub */
-
-/**
- *
- * @brief Atomically subtract a value from a memory location
- *
- * This routine atomically subtracts <value> from the contents of <target>,
- * placing the result in <target>.  The operation is done using signed integer
- * arithmetic. Various CPU architectures may impose restrictions with regards to
- * the alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_sub
- *    (
- *    atomic_t *target,	/@ memory location to subtract from @/
- *    atomic_val_t value	/@ value to subtract @/
- *    )
- *
- */
-
-SECTION_SUBSEC_FUNC(TEXT, atomic_decSub, atomic_sub)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	SUB	r3, r2, r1	/* subtract word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_sub	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically perform a bitwise NAND on a memory location
- *
- * This routine atomically performs a bitwise NAND operation of the contents of
- * <target> and <value>, placing the result in <target>.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_nand
- *    (
- *    atomic_t *target,	/@ memory location to NAND @/
- *    atomic_val_t value	/@ NAND with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_nand)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	AND	r3, r2, r1	/* AND word */
-	MVN	r3, r3		/* invert */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_nand	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically perform a bitwise AND on a memory location
- *
- * This routine atomically performs a bitwise AND operation of the contents of
- * <target> and <value>, placing the result in <target>.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_and
- *    (
- *    atomic_t *target,	/@ memory location to AND @/
- *    atomic_val_t value	/@ AND with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_and)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	AND	r3, r2, r1	/* AND word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_and	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically perform a bitwise OR on memory location
- *
- * This routine atomically performs a bitwise OR operation of the contents of
- * <target> and <value>, placing the result in <target>.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_or
- *    (
- *    atomic_t *target,	/@ memory location to OR @/
- *    atomic_val_t value	/@ OR with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_or)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	ORR	r3, r2, r1	/* OR word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_or	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically perform a bitwise XOR on a memory location
- *
- * This routine atomically performs a bitwise XOR operation of the contents of
- * <target> and <value>, placing the result in <target>.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return Contents of <target> before the atomic operation
- *
- * ERRNO: N/A
- *
- * atomic_val_t atomic_xor
- *    (
- *    atomic_t *target,	/@ memory location to XOR @/
- *    atomic_val_t value	/@ XOR with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_xor)
-
-	LDREX	r2, [r0]	/* load old value and mark exclusive access */
-	EOR	r3, r2, r1	/* XOR word */
-	STREX	r12, r3, [r0]	/* try to store new value */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_xor	/* if not, retry */
-
-	MOV	r0, r2		/* return old value */
-	MOV	pc, lr
-
-/**
- *
- * @brief Atomically compare-and-swap the contents of a memory location
- *
- * This routine performs an atomic compare-and-swap. testing that the contents of
- * <target> contains <oldValue>, and if it does, setting the value of <target>
- * to <newValue>. Various CPU architectures may impose restrictions with regards
- * to the alignment and cache attributes of the atomic_t type.
- *
- * This routine can be used from both task and interrupt level.
- *
- * @return 1 if the swap is actually executed, 0 otherwise.
- *
- * ERRNO: N/A
- *
- * int atomic_cas
- *    (
- *    atomic_t *target,	        /@ memory location to compare-and-swap @/
- *    atomic_val_t oldValue,	/@ compare to this value @/
- *    atomic_val_t newValue,	/@ swap with this value @/
- *    )
- *
- */
-
-SECTION_FUNC(TEXT, atomic_cas)
-
-	LDREX	r3, [r0]	/* load the value and mark exclusive access */
-	CMP	r3, r1		/* if (*target != oldValue) */
-	ITT NE
-	    MOVNE	r0, #0		/*     return FALSE */
-	    MOVNE	pc, lr
-	STREX	r12, r2, [r0]	/* try to store if equal */
-	TEQ	r12, #0		/* store successful? */
-	BNE	atomic_cas	/* if not, retry */
-
-	MOV	r0, #1		/* return TRUE if swap occurred */
-	MOV	pc, lr

arch/arm/core/cortex_m/Kconfig

@@ -79,7 +79,7 @@ config DATA_ENDIANNESS_LITTLE
 	default y
 	help
 	This is driven by the processor implementation, since it is fixed in
-	hardware. The platform should set this value to 'n' if the data is
+	hardware. The board should set this value to 'n' if the data is
 	implemented as big endian.
 
 config STACK_ALIGN_DOUBLE_WORD
@@ -92,12 +92,12 @@ config STACK_ALIGN_DOUBLE_WORD
 
 config NUM_IRQ_PRIO_BITS
 	int
-	#hidden option, implemented by platform
+	#hidden option, implemented by board
 	help
 	Cortex-M chips can implement up to 8 bits of interrupt priorities,
 	for a maximum of 256 priorities. Most chips implement fewer than 8.
 
-	The platform must define the correct value.
+	The board must define the correct value.
 
 config RUNTIME_NMI
 	bool
@@ -119,8 +119,10 @@ config FAULT_DUMP
 
 	2: The default. Display specific and verbose information. Consumes
 		the most memory (long strings).
+
 	1: Display general and short information. Consumes less memory
 		(short strings).
+
 	0: Off.
 
 config XIP
@@ -130,28 +132,28 @@ config SRAM_SIZE
 	int "SRAM Size in kB"
 	help
 	This option specifies the size of the SRAM in kB.  It is normally set by
-	the platform's defconfig file and the user should generally avoid modifying
+	the board's defconfig file and the user should generally avoid modifying
 	it via the menu configuration.
 
 config SRAM_BASE_ADDRESS
 	hex "SRAM Base Address"
 	help
-	This option specifies the base address of the SRAM on the platform.  It is
-	normally set by the platform's defconfig file and the user should generally
+	This option specifies the base address of the SRAM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 
 config FLASH_SIZE
 	int "Flash Size in kB"
 	help
 	This option specifies the size of the flash in kB.  It is normally set by
-	the platform's defconfig file and the user should generally avoid modifying
+	the board's defconfig file and the user should generally avoid modifying
 	it via the menu configuration.
 
 config FLASH_BASE_ADDRESS
 	hex "Flash Base Address"
 	help
-	This option specifies the base address of the flash on the platform.  It is
-	normally set by the platform's defconfig file and the user should generally
+	This option specifies the base address of the flash on the board.  It is
+	normally set by the board's defconfig file and the user should generally
 	avoid modifying it via the menu configuration.
 endmenu
 
@@ -195,7 +197,7 @@ config IRQ_VECTOR_TABLE_CUSTOM
 	depends on !SW_ISR_TABLE
 	default n
 	help
-	Projects, not the platform, provide the IRQ part of the vector table.
+	Projects, not the board, provide the IRQ part of the vector table.
 
 	This is the table of interrupt handlers with the best potential
 	performance, but is the less flexible.

arch/arm/core/cortex_m/Makefile

@@ -1,5 +1,6 @@
 ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/arch/$(ARCH)/platforms/$(SOC_NAME)
+ccflags-y +=-I$(srctree)/arch/arm/soc/$(SOC_PATH)
+ccflags-y +=-I$(srctree)/kernel/nanokernel/include
 
 asflags-y = $(ccflags-y)
 
@@ -7,6 +8,5 @@ obj-y = vector_table.o reset.o \
 	nmi_on_reset.o prep_c.o scs.o scb.o nmi.o \
 	exc_manage.o exc_wrapper.o
 
-obj-$(CONFIG_ERRNO) += errno.o
 obj-$(CONFIG_IRQ_VECTOR_TABLE_SOC) += irq_vector_table.o
 obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o

arch/arm/core/cortex_m/exc_manage.c

@@ -78,6 +78,14 @@ void sys_exc_esf_dump(NANO_ESF *esf)
 	printk("r14/lr: %x\n", esf->lr);
 	printk("r15/pc: %x  ", esf->pc);
 	printk("xpsr:   %x\n", esf->xpsr);
+#ifdef CONFIG_FLOAT
+	for (int i = 0; i < 16; i += 4) {
+		printk("s[%d]:  %x  s[%d]:  %x  s[%d]:  %x  s[%d]:  %x\n",
+			i, esf->s[i], i + 1, esf->s[i + 1],
+			i + 2, esf->s[i + 2], i + 3, esf->s[i + 3]);
+	}
+	printk("fpscr:  %x\n", esf->fpscr);
+#endif
 }
 
 #endif /* CONFIG_XIP */

arch/arm/core/cortex_m/prep_c.c

@@ -30,53 +30,11 @@
 #include <stdint.h>
 #include <toolchain.h>
 #include <linker-defs.h>
-
-/**
- *
- * @brief Clear BSS
- *
- * This routine clears the BSS region, so all bytes are 0.
- *
- * @return N/A
- */
-
-static void bssZero(void)
-{
-	volatile uint32_t *pBSS = (uint32_t *)&__bss_start;
-	unsigned int n;
-
-	for (n = 0; n < (unsigned int)&__bss_num_words; n++) {
-		pBSS[n] = 0;
-	}
-}
-
-/**
- *
- * @brief Copy the data section from ROM to RAM
- *
- * This routine copies the data section from ROM to RAM.
- *
- * @return N/A
- */
+#include <nano_internal.h>
 
 #ifdef CONFIG_XIP
-static void dataCopy(void)
-{
-	volatile uint32_t *pROM = (uint32_t *)&__data_rom_start;
-	volatile uint32_t *pRAM = (uint32_t *)&__data_ram_start;
-	unsigned int n;
-
-	for (n = 0; n < (unsigned int)&__data_num_words; n++) {
-		pRAM[n] = pROM[n];
-	}
-}
-
 static inline void relocate_vector_table(void) { /* do nothing */ }
 #else
-static void dataCopy(void)
-{
-}
-
 static inline void relocate_vector_table(void)
 {
 	/* vector table is already in SRAM, just point to it */
@@ -84,6 +42,44 @@ static inline void relocate_vector_table(void)
 }
 #endif
 
+#ifdef CONFIG_FLOAT
+static inline void enable_floating_point(void)
+{
+	/*
+	 * Upon reset, the Co-Processor Access Control Register is 0x00000000.
+	 * Enable CP10 and CP11 coprocessors to enable floating point.
+	 */
+	__scs.cpacr.val = (_SCS_CPACR_CP10_FULL_ACCESS |
+				_SCS_CPACR_CP11_FULL_ACCESS);
+
+	/*
+	 * Upon reset, the FPU Context Control Register is 0xC0000000
+	 * (both Automatic and Lazy state preservation is enabled).
+	 * Disable lazy state preservation so the volatile FP registers are
+	 * always saved on exception.
+	 */
+	__scs.fpu.ccr.val = (_SCS_FPU_CCR_ASPEN_ENABLE |
+				_SCS_FPU_CCR_LSPEN_DISABLE);
+
+	/*
+	 * Although automatic state preservation is enabled, the processor
+	 * does not automatically save the volatile FP registers until they
+	 * have first been touched. Perform a dummy move operation so that
+	 * the stack frames are created as expected before any task or fiber
+	 * context switching can occur.
+	 */
+	__asm__ volatile(
+		"vmov s0, s0;\n\t"
+		"dsb;\n\t"
+		"isb;\n\t"
+		);
+}
+#else
+static inline void enable_floating_point(void)
+{
+}
+#endif
+
 extern FUNC_NORETURN void _Cstart(void);
 /**
  *
@@ -97,8 +93,9 @@ extern FUNC_NORETURN void _Cstart(void);
 void _PrepC(void)
 {
 	relocate_vector_table();
-	bssZero();
-	dataCopy();
+	enable_floating_point();
+	_bss_zero();
+	_data_copy();
 	_Cstart();
 	CODE_UNREACHABLE;
 }

arch/arm/core/fatal.c

@@ -47,6 +47,14 @@ const NANO_ESF _default_esf = {
 	{0xdeaddead}, /* r14/lr */
 	{0xdeaddead}, /* r15/pc */
 	 0xdeaddead,  /* xpsr */
+#ifdef CONFIG_FLOAT
+	{0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead,   /* s0 .. s3 */
+	 0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead,    /* s4 .. s7 */
+	 0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead,    /* s8 .. s11 */
+	 0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead},   /* s12 .. s15 */
+	0xdeaddead,  /* fpscr */
+	0xdeaddead,  /* undefined */
+#endif
 };
 
 /**

arch/arm/core/offsets/offsets.c

@@ -51,6 +51,10 @@ GEN_OFFSET_SYM(tTCS, basepri);
 GEN_OFFSET_SYM(tTCS, custom_data);
 #endif
 
+#ifdef CONFIG_FLOAT
+GEN_OFFSET_SYM(tTCS, preemp_float_regs);
+#endif
+
 /* ARM-specific ESF structure member offsets */
 
 GEN_OFFSET_SYM(tESF, a1);
@@ -62,6 +66,11 @@ GEN_OFFSET_SYM(tESF, lr);
 GEN_OFFSET_SYM(tESF, pc);
 GEN_OFFSET_SYM(tESF, xpsr);
 
+#ifdef CONFIG_FLOAT
+GEN_OFFSET_SYM(tESF, s);
+GEN_OFFSET_SYM(tESF, fpscr);
+#endif
+
 /* size of the entire tESF structure */
 
 GEN_ABSOLUTE_SYM(__tESF_SIZEOF, sizeof(tESF));

arch/arm/core/swap.S

@@ -76,6 +76,11 @@ SECTION_FUNC(TEXT, __pendsv)
     mrs ip, PSP
     stmia r0, {v1-v8, ip}
 
+#ifdef CONFIG_FP_SHARING
+    add r0, r2, #__tTCS_preemp_float_regs_OFFSET
+    vstmia r0, {s16-s31}
+#endif
+
     /*
      * Prepare to clear PendSV with interrupts unlocked, but
      * don't clear it yet. PendSV must not be cleared until
@@ -128,6 +133,11 @@ SECTION_FUNC(TEXT, __pendsv)
     str ip, [r2, #__tTCS_basepri_OFFSET]
     msr BASEPRI, r0
 
+#ifdef CONFIG_FP_SHARING
+    add r0, r2, #__tTCS_preemp_float_regs_OFFSET
+    vldmia r0, {s16-s31}
+#endif
+
     /* load callee-saved + psp from TCS */
     add r0, r2, #__tTCS_preempReg_OFFSET
     ldmia r0, {v1-v8, ip}

arch/arm/core/sys_fatal_error_handler.c

@@ -74,7 +74,7 @@ void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF * pEsf)
 	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
-	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential(NULL)) {
+	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential()) {
 		PRINTK("Fatal fault in %s ! Spinning...\n",
 		       NANO_CTX_ISR == curCtx
 			       ? "ISR"

arch/arm/core/thread.c

@@ -100,7 +100,8 @@ static ALWAYS_INLINE void _thread_monitor_init(struct tcs *tcs /* thread */
  * @return N/A
  */
 
-void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
+void _new_thread(char *pStackMem, unsigned stackSize,
+		 void *uk_task_ptr, _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned options)
 {
@@ -143,6 +144,12 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	tcs->entry = (struct __thread_entry *)(pInitCtx);
 #endif
 
+#ifdef CONFIG_MICROKERNEL
+	tcs->uk_task_ptr = uk_task_ptr;
+#else
+	ARG_UNUSED(uk_task_ptr);
+#endif
+
 	tcs->preempReg.psp = (uint32_t)pInitCtx;
 	tcs->basepri = 0;
 

arch/arm/include/cortex_m/stack.h

@@ -43,9 +43,6 @@ extern "C" {
 
 #else
 
-#define __GET_MSP() \
-	STACK_ROUND_DOWN(&_interrupt_stack[CONFIG_ISR_STACK_SIZE - 1])
-
 extern char _interrupt_stack[CONFIG_ISR_STACK_SIZE];
 
 /**
@@ -59,7 +56,7 @@ extern char _interrupt_stack[CONFIG_ISR_STACK_SIZE];
  */
 static ALWAYS_INLINE void _InterruptStackSetup(void)
 {
-	uint32_t msp = __GET_MSP();
+	uint32_t msp = (uint32_t)(_interrupt_stack + CONFIG_ISR_STACK_SIZE);
 
 	_MspSet(msp);
 }

arch/arm/include/nano_private.h

@@ -57,9 +57,8 @@ struct __thread_entry {
 
 struct coop {
 	/*
-	 * Unused for Cortex-M, which automatically saves the neccesary
-	 *registers
-	 * in its exception stack frame.
+	 * Unused for Cortex-M, which automatically saves the necessary
+	 * registers in its exception stack frame.
 	 *
 	 * For Cortex-A, this may be:
 	 *
@@ -96,8 +95,8 @@ typedef struct preempt tPreempt;
 
 #define FIBER 0x000
 #define TASK 0x001	   /* 1 = task, 0 = fiber   */
-#define INT_ACTIVE 0x002     /* 1 = executino context is interrupt handler */
-#define EXC_ACTIVE 0x004     /* 1 = executino context is exception handler */
+#define INT_ACTIVE 0x002     /* 1 = executing context is interrupt handler */
+#define EXC_ACTIVE 0x004     /* 1 = executing context is exception handler */
 #define USE_FP 0x010	 /* 1 = thread uses floating point unit */
 #define PREEMPTIBLE                                            \
 	0x020 /* 1 = preemptible thread                       \
@@ -119,6 +118,28 @@ typedef struct preempt tPreempt;
 #endif
 
 #ifndef _ASMLANGUAGE
+
+#ifdef CONFIG_FLOAT
+struct preemp_float {
+	float  s16;
+	float  s17;
+	float  s18;
+	float  s19;
+	float  s20;
+	float  s21;
+	float  s22;
+	float  s23;
+	float  s24;
+	float  s25;
+	float  s26;
+	float  s27;
+	float  s28;
+	float  s29;
+	float  s30;
+	float  s31;
+};
+#endif
+
 struct tcs {
 	struct tcs *link; /* singly-linked list in _nanokernel.fibers */
 	uint32_t flags;
@@ -139,6 +160,17 @@ struct tcs {
 #ifdef CONFIG_ERRNO
 	int errno_var;
 #endif
+#ifdef CONFIG_MICROKERNEL
+	void *uk_task_ptr;
+#endif
+#ifdef CONFIG_FLOAT
+	/*
+	 * No cooperative floating point register set structure exists for
+	 * the Cortex-M as it automatically saves the necessary registers
+	 * in its exception stack frame.
+	 */
+	struct preemp_float  preemp_float_regs;
+#endif
 };
 
 struct s_NANO {

arch/arm/soc/atmel_sam3/Kbuild

@@ -1 +0,0 @@
-obj-y += soc.o

arch/arm/soc/atmel_sam3/Kconfig

@@ -80,4 +80,13 @@ config SOC_ATMEL_SAM3_PLLA_DIVA
 	With default of MULA == 6, and DIVA == 1,
 	PLL is running at 7 times of main clock.
 
+config SOC_ATMEL_SAM3_WAIT_MODE
+	bool "Atmel SAM3 goes to Wait mode instead of Sleep mode"
+	depends on SOC_ATMEL_SAM3_EXT_MAINCK
+	default y if DEBUG
+	help
+	For JTAG debugging CPU clock (HCLK) should not stop. In order
+	to achieve this, make CPU go to Wait mode instead of Sleep
+	mode while using external crystal oscillator for main clock.
+
 endif # SOC_ATMEL_SAM3

arch/arm/soc/atmel_sam3/Kconfig.defconfig

@@ -75,7 +75,10 @@ config UART_ATMEL_SAM3_CLK_FREQ
 
 endif # UART_ATMEL_SAM3
 
-if GPIO_ATMEL_SAM3
+if GPIO
+
+config GPIO_ATMEL_SAM3
+	def_bool y
 
 config GPIO_ATMEL_SAM3_PORTA
 	default y
@@ -89,16 +92,24 @@ config GPIO_ATMEL_SAM3_PORTC
 config GPIO_ATMEL_SAM3_PORTD
 	default y
 
-endif # GPIO_ATMEL_SAM3
+endif # GPIO
 
-if I2C_ATMEL_SAM3
+if I2C
 
-config I2C_ATMEL_SAM3_0
+config I2C_ATMEL_SAM3
+	def_bool y
+
+config I2C_0
+	default y
+config I2C_0_IRQ_PRI
+	default 0
+
+config I2C_1
 	default y
 
-config I2C_ATMEL_SAM3_1
-	default y
+config I2C_1_IRQ_PRI
+	default 0
 
-endif # I2C_ATMEL_SAM3
+endif # I2C
 
 endif # SOC_ATMEL_SAM3

arch/arm/soc/atmel_sam3/Makefile

@@ -1,7 +1 @@
-
-arch-cflags += $(call cc-option,-mthumb -mcpu=cortex-m3) \
-		$(call cc-option,-mthumb -march=armv7-m)
-
-KBUILD_AFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
-KBUILD_CFLAGS += $(arch-cflags)
+obj-y += soc.o

arch/arm/soc/atmel_sam3/linker.ld

@@ -1,4 +1,4 @@
-/* linker.cmd - Linker command/script file */
+/* linker.ld - Linker command/script file */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -16,4 +16,4 @@
  * limitations under the License.
  */
 
-#include <arch/arm/cortex_m/scripts/linker.cmd>
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/atmel_sam3/soc.c

@@ -38,7 +38,7 @@
  * Assumption:
  * SLCK = 32.768kHz
  */
-static void clock_init(void)
+static ALWAYS_INLINE void clock_init(void)
 {
 	uint32_t tmp;
 
@@ -81,6 +81,14 @@ static void clock_init(void)
 	/* Wait for main oscillator to be selected */
 	while (!(__PMC->sr & PMC_INT_MOSCSELS))
 		;
+#ifdef CONFIG_SOC_ATMEL_SAM3_WAIT_MODE
+	/*
+	 * Instruct CPU enter Wait mode instead of Sleep mode to
+	 * keep Processor Clock (HCLK) and thus be able to debug
+	 * CPU using JTAG
+	 */
+	__PMC->fsmr |= PMC_FSMR_LPM;
+#endif
 #else
 	/* Set main fast RC oscillator to 12 MHz */
 	__PMC->ckgr_mor = PMC_CKGR_MOR_KEY | PMC_CKGR_MOR_MOSCRCF_12MHZ

arch/arm/soc/atmel_sam3/soc.h

@@ -162,6 +162,8 @@
 #define PMC_MCKR_PLLADIV2		(1 << 12)
 #define PMC_MCKR_UPLLDIV2		(1 << 13)
 
+#define PMC_FSMR_LPM			(1 << 20)
+
 #define PMC_INT_MOSCXTS			(1 << 0)
 #define PMC_INT_LOCKA			(1 << 1)
 #define PMC_INT_MCKRDY			(1 << 3)

arch/arm/soc/fsl_frdm_k64f/Kconfig.soc

@@ -1,6 +0,0 @@
-
-config  SOC_FSL_FRDM_K64F
-	bool "Freescale FRDM-K64F"
-	select CPU_CORTEX_M
-	select CPU_CORTEX_M4
-	select SYS_POWER_LOW_POWER_STATE_SUPPORTED

arch/arm/soc/fsl_frdm_k64f/Makefile

@@ -1,8 +0,0 @@
-
-
-arch-cflags = $(call cc-option,-mthumb -mcpu=cortex-m4) \
-			$(call cc-option,-mthumb -march=armv7e-m)
-
-KBUILD_CFLAGS += $(arch-cflags)
-KBUILD_CXXFLAGS += $(arch-cflags)
-KBUILD_AFLAGS += $(arch-cflags)

arch/arm/soc/nordic_nrf5/Kbuild

@@ -0,0 +1,2 @@
+
+obj-y += $(SOC_SERIES)/

arch/arm/soc/nordic_nrf5/Kconfig

@@ -0,0 +1,29 @@
+# Kconfig - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config SOC_FAMILY_NRF5
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+if SOC_FAMILY_NRF5
+config SOC_FAMILY
+	string
+	default nordic_nrf5
+endif
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.soc"

arch/arm/soc/nordic_nrf5/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# Kconfig.defconfig - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.defconfig.series"

arch/arm/soc/nordic_nrf5/Kconfig.soc

@@ -0,0 +1,19 @@
+# Kconfig.soc - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+source "arch/arm/soc/nordic_nrf5/*/Kconfig.series"
+

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832

@@ -0,0 +1,40 @@
+# Kconfig.defconfig.nrf52832 - Nordic Semiconductor nRF52832 MCU
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+
+if SOC_NRF52832
+
+config SOC
+	string
+	default nRF52832
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 64000000
+
+config SRAM_SIZE
+	default 64
+
+config FLASH_SIZE
+	default 512
+
+config NUM_IRQS
+	int
+	default 38
+
+endif # SOC_NRF52832
+

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series

@@ -0,0 +1,35 @@
+# Kconfig.defconfig.series - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if SOC_SERIES_NRF52X
+
+source "arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52*"
+
+config SOC_SERIES
+	default nrf52
+
+config SRAM_BASE_ADDRESS
+	default 0x20000000
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config NUM_IRQ_PRIO_BITS
+	int
+	default 3
+
+endif # SOC_SERIES_NRF52X

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series

@@ -0,0 +1,28 @@
+# Kconfig.series - Nordic Semiconductor nRF5 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config  SOC_SERIES_NRF52X
+	bool "Nordic Semiconductor nRF52 series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_NRF5
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select XIP
+	select HAS_CMSIS
+	select HAS_NORDIC_MDK
+	help
+	 Enable support for NRF52 MCU series

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc

@@ -0,0 +1,25 @@
+# Kconfig.soc - Nordic Semiconductor nRF52 MCU line
+#
+# Copyright (c) 2016 Nordic Semiconductor ASA
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+choice
+prompt "nRF52x MCU Selection"
+depends on SOC_SERIES_NRF52X
+
+config SOC_NRF52832
+	bool "NRF52832"
+
+endchoice

arch/arm/soc/nordic_nrf5/nrf52/Makefile

@@ -0,0 +1,19 @@
+ifdef CONFIG_SOC_SERIES_NRF52X
+soc-cflags += -DNRF52
+endif
+
+obj-y += soc.o
+
+KERNEL_HEX_NAME = $(KERNEL_NAME).hex
+
+quiet_cmd_gen_hex = HEX     $@
+      cmd_gen_hex =                                                         \
+(                                                                           \
+   $(OBJCOPY) -S -O ihex -R .note -R .comment -R COMMON -R .eh_frame $< $@; \
+)
+
+$(KERNEL_HEX_NAME): $(KERNEL_ELF_NAME)
+	$(call cmd,gen_hex)
+
+zephyr: $(KERNEL_HEX_NAME)
+all: $(KERNEL_HEX_NAME)

arch/arm/soc/nordic_nrf5/nrf52/linker.ld

@@ -1,4 +1,4 @@
-/* linker.cmd - Linker command/script file */
+/* linker.ld - Linker command/script file */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -16,4 +16,4 @@
  * limitations under the License.
  */
 
-#include <arch/arm/cortex_m/scripts/linker.cmd>
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nordic_nrf5/nrf52/soc.c

@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Nordic Semiconductor nRF52 family processor
+ *
+ * This module provides routines to initialize and support board-level hardware
+ * for the Nordic Semiconductor nRF52 family processor.
+ */
+
+#include <nanokernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+
+#ifdef CONFIG_RUNTIME_NMI
+extern void _NmiInit(void);
+#define NMI_INIT() _NmiInit()
+#else
+#define NMI_INIT()
+#endif
+
+#include "nrf.h"
+
+#define __SYSTEM_CLOCK_64M (64000000UL)
+
+static bool ftpan_32(void);
+static bool ftpan_37(void);
+static bool ftpan_36(void);
+
+uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M;
+
+static void clock_init(void)
+{
+	SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+static int nordicsemi_nrf52_init(struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	/* Note:
+	* Magic numbers below are obtained by reading the registers
+	* when the SoC was running the SAM-BA bootloader
+	* (with reserved bits set to 0).
+	*/
+
+	key = irq_lock();
+
+	/* Setup the vector table offset register (VTOR),
+	* which is located at the beginning of flash area.
+	*/
+	_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
+
+	/* Workaround for FTPAN-32 "DIF: Debug session automatically
+	* enables TracePort pins" found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_32()) {
+		CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
+	}
+
+	/* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio,
+	* ECB, AAR and CCM." found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_37()) {
+		*(volatile uint32_t *)0x400005A0 = 0x3;
+	}
+
+	/* Workaround for FTPAN-36 "CLOCK: Some registers are not
+	* reset when expected." found at Product Anomaly document
+	* for your device located at https://www.nordicsemi.com/
+	*/
+	if (ftpan_36()) {
+		NRF_CLOCK->EVENTS_DONE = 0;
+		NRF_CLOCK->EVENTS_CTTO = 0;
+	}
+
+	/* Enable the FPU if the compiler used floating point unit
+	* instructions. __FPU_USED is a MACRO defined by the
+	* compiler. Since the FPU consumes energy, remember to
+	* disable FPU use in the compiler if floating point unit
+	* operations are not used in your code.
+	*/
+	#if (__FPU_USED == 1)
+
+	SCB->CPACR |= (3UL << 20) | (3UL << 22);
+	__DSB();
+	__ISB();
+
+	#endif
+
+	/* Configure NFCT pins as GPIOs if NFCT is not to be used in
+	* your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+	* two GPIOs (see Product Specification to see which ones)
+	* will be reserved for NFC and will not be available as
+	* normal GPIOs.
+	*/
+	#if defined(CONFIG_NFCT_PINS_AS_GPIOS)
+
+	if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) ==
+	    (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) {
+
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NVIC_SystemReset();
+	}
+
+	#endif
+
+	/* Configure GPIO pads as pPin Reset pin if Pin Reset
+	* capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+	* defined, pin reset will not be available. One GPIO (see
+	* Product Specification to see which one) will then be
+	* reserved for PinReset and not available as normal GPIO.
+	*/
+	#if defined(CONFIG_GPIO_AS_PINRESET)
+	if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+	    ((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
+	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) {
+
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->PSELRESET[0] = 21;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_UICR->PSELRESET[1] = 21;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+		while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {
+			;
+		}
+		NVIC_SystemReset();
+	}
+	#endif
+
+	/* Enable SWO trace functionality. If ENABLE_SWO is not
+	* defined, SWO pin will be used as GPIO (see Product
+	* Specification to see which one).
+	*/
+	#if defined(ENABLE_SWO)
+
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial <<
+				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
+	#endif
+
+	/* Enable Trace functionality. If ENABLE_TRACE is not
+	* defined, TRACE pins will be used as GPIOs (see Product
+	* Specification to see which ones).
+	*/
+	#if defined(ENABLE_TRACE)
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel <<
+				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
+	#endif
+
+	/* Clear all faults */
+	_ScbMemFaultAllFaultsReset();
+	_ScbBusFaultAllFaultsReset();
+	_ScbUsageFaultAllFaultsReset();
+
+	_ScbHardFaultAllFaultsReset();
+
+	/* Setup master clock */
+	clock_init();
+
+	/* Install default handler that simply resets the CPU
+	* if configured in the kernel, NOP otherwise
+	*/
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+static bool ftpan_32(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool ftpan_37(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool ftpan_36(void)
+{
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+SYS_INIT(nordicsemi_nrf52_init, PRIMARY, 0);