Zephyr 1.7.0

Change-Id: I0841f3b768ffdf98c8c4acf2a8f5f85ba0370bb3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

.checkpatch.conf

@@ -3,14 +3,19 @@
 --emacs
 --summary-file
 --show-types
---max-line-length=100
+--max-line-length=80
+--min-conf-desc-length=1
 
 --ignore BRACES
 --ignore PRINTK_WITHOUT_KERN_LEVEL
 --ignore SPLIT_STRING
---ignore FILE_PATH_CHANGES
 --ignore VOLATILE
 --ignore CONFIG_EXPERIMENTAL
 --ignore PREFER_KERNEL_TYPES
 --ignore AVOID_EXTERNS
 --ignore NETWORKING_BLOCK_COMMENT_STYLE
+--ignore DATE_TIME
+--ignore MINMAX
+--ignore CONST_STRUCT
+--ignore FILE_PATH_CHANGES
+--exclude ext

.gitignore

@@ -2,14 +2,15 @@
 *.a
 *.d
 *.cmd
+*.log
 *.pyc
 *.swp
 *.swo
-!arch/*/*/**/*.cmd
 *~
 cscope.*
 .dir
 outdir
+outdir-*
 scripts/basic/fixdep
 scripts/gen_idt/gen_idt
 scripts/gen_offset_header/gen_offset_header
@@ -19,11 +20,17 @@ scripts/kconfig/zconf.hash.c
 scripts/kconfig/zconf.lex.c
 scripts/kconfig/zconf.tab.c
 doc/_build
-xml
-html/
-doc/latex/
+doc/doxygen
+doc/xml
+doc/html
+doc/boards
+doc/samples
+doc/latex
 sanity-out/
 scripts/grub
 doc/reference/kconfig/CONFIG_*
 doc/reference/kconfig/index.rst
 tags
+.project
+.cproject
+.xxproject

.known-issues/README

@@ -0,0 +1,55 @@
+This directory contains configuration files to ignore errors found in
+the build and test process which are known to the developers and for
+now can be safely ignored.
+
+To use:
+
+ $ cd zephyr
+ $ make SOMETHING >& result
+ $ scripts/filter-known-issues.py result
+
+It is included in the source tree so if anyone has to submit anything
+that triggers some kind of error that is a false positive, it can
+include the "ignore me" file, properly documented.
+
+Each file can contain one or more multiline Python regular expressions
+(https://docs.python.org/2/library/re.html#regular-expression-syntax)
+that match an error message. Multiple regular expressions are
+separated by comment blocks (that start with #). Note that an empty
+line still is considered part of the multiline regular expression.
+
+For example
+
+---beginning---
+#
+# This testcase always fails, pending fix ZEP-1234
+#
+.*/tests/kernel/grumpy .* FAIL
+#
+# Documentation issue, masks:
+#
+# /home/e/inaky/z/kernel.git/doc/api/io_interfaces.rst:28: WARNING: Invalid definition: Expected identifier in nested name. [error at 19]
+#  struct dev_config::@65  dev_config::bits
+#  -------------------^
+#
+^(?P<filename>.+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^\s+struct dev_config::@[0-9]+  dev_config::bits.*
+^\s+-+\^
+---end---
+
+Note you want to:
+
+- use relateive paths; instead of
+  /home/me/mydir/zephyr/something/somewhere.c you will want
+  ^.*/something/somewhere.c (as they will depend on where it is being
+  built)
+
+- Replace line numbers with [0-9]+, as they will change
+
+- (?P<filename>[-._/\w]+/something/somewhere.c) saves the match on
+  that file path in a "variable" called 'filename' that later you can
+  match with (?P=filename) if you want to match multiple lines of the
+  same error message.
+
+Can get really twisted and interesting in terms of regexps; they are
+powerful, so start small :)

.known-issues/doc/bluetooth.conf

@@ -0,0 +1,38 @@
+#
+# Bluetooth unnamed struct definition
+#
+# FIXME: all these should match the relative filename
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]$
+^.*bt_conn_info.__unnamed__.*$
+^[- \t]*\^$
+#
+# bt_gatt_discover_params unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_gatt_discover_params.__unnamed__.*
+^[- \t]*\^
+#
+# Bluetooth GATT unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/bluetooth.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*bt_gatt_read_params.__unnamed__.*
+^[- \t]*\^

.known-issues/doc/header_footer.conf

@@ -0,0 +1,18 @@
+#
+# KERNELVERSION not being defined in local builds, kill that warning,
+# can ignore it
+#
+^.*/Kconfig.zephyr:[0-9]+: warning: The symbol KERNELVERSION references the non-existent environment variable KERNELVERSION.*
+#
+# Documentation generation, early message
+#
+^cd .* && doxygen doc/doxygen.config
+^srctree=.* SRCARCH=\w+ python scripts/genrest/genrest.py .*$
+# This cuts the sphinx build line; has to be separate because in the
+# middle, we have removed the KERNELVERSION one and a full regex won't match
+^sphinx-build -t \w+ -b html .*
+#
+# Documentation generation, footer message
+#
+^[ \t]*
+^Build finished. The HTML pages are in [-._/\w]+

.known-issues/doc/kernel.conf

@@ -0,0 +1,14 @@
+#
+# Kernel unnamed struct definition
+#
+# FIXME: all these should match the relative filename
+#
+^(?P<filename>[-._/\w]+/doc/api/kernel_api.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]$
+^[ \t]*$
+^[ \t]*\^$
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]$
+^.*k_msg.extra.*$
+^[- \t]*\^$

.known-issues/doc/networking.conf

@@ -0,0 +1,49 @@
+#
+# Networking
+#
+#
+# include/net/net_ip.h warnings
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*in[_6]+addr.in[46]_u
+^[- \t]*\^
+#
+# include/net/net_if.h warnings
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Error when parsing function declaration.
+^\If the function has no return type:
+^[ \t]*Error in declarator or parameters and qualifiers
+^[ \t]*Invalid definition: Expected identifier in nested name, got keyword: struct \[error at [0-9]+]
+^.*struct net_if __aligned\(32\)
+^[- \t]*\^
+^\If the function has a return type:
+^[ \t]*Error in declarator or parameters and qualifiers
+^[ \t]*If pointer to member declarator:
+^[ \t]*Invalid definition: Expected \'::\' in pointer to member \(function\). \[error at [0-9]+]
+^.*struct net_if __aligned\(32\)
+^[- \t]*\^
+^[ \t]*If declarator-id:
+^[ \t]*Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^.*struct net_if __aligned\(32\)
+^[- \t]*\^
+#
+# include/net/dns_client.h
+#
+^(?P<filename>[-._/\w]+/doc/api/networking.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*dns_context.address
+^[- \t]*\^

.known-issues/doc/sensor.conf

@@ -0,0 +1,12 @@
+#
+# Sensor value unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*sensor_value.__unnamed__.*
+^[- \t]*\^

.known-issues/doc/uart.conf

@@ -0,0 +1,15 @@
+#
+# UART unnamed struct definition
+#
+^(?P<filename>[-._/\w]+/doc/api/io_interfaces.rst):(?P<lineno>[0-9]+): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected identifier in nested name. \[error at [0-9]+]
+^[ \t]*
+^[ \t]*\^
+^(?P=filename):(?P=lineno): WARNING: Invalid definition: Expected end of definition. \[error at [0-9]+]
+^.*uart_device_config.__unnamed__.*
+^[- \t]*\^

.known-issues/make.conf

@@ -0,0 +1,6 @@
+#
+# When filtering output of the build process, ignore lines that don't
+# provide any information that helps the invoker tell if there was an
+# error.
+#
+^make: (Entering|Leaving) directory .*

.known-issues/testcases/block.conf

@@ -0,0 +1,11 @@
+#
+# When executing test cases, ignore the following messages as they are
+# not to be considered hard errors.
+#
+# Block line when test case cannot run in the HW due to server or connection issues
+#
+^BLCK0/[-a-z0-9:]+	(.+)#test @[^/]+/[^:]+:[^:]+: evaluation blocked(.*)$
+#
+# Block line when there is an issue with the YKUSH serial connection
+#
+^BLCK0/[-a-z0-9:]+	(.+)#test @[^/]+/(?P<board>[^:]+):[^:]+: exception: 400: (?P=board): Cannot find YKUSH serial '[A-Z0-9]+'$

.known-issues/testcases/makefile.conf

@@ -0,0 +1,18 @@
+#
+# When executing test cases under TCF, ignore the following messages
+# as they are not to be considered hard errors.
+#
+# TCF is run under make for taking advantage of the jobserver; when
+# the testcase execution fail, make will complain, which we can
+# ignore ('sommersault' was the old name of the target).
+#
+^/tmp/tcf-[a-zA-Z0-9]+.mk:[0-9]+: recipe for target ('tcf-jobserver-run'|'sommersault') failed$
+#
+# More of the same
+#
+^make: \*\*\* \[(tcf-jobserver-run|sommersault)\] Error 1$
+#
+# TCF's summary line. We don't need to consider it to determine if the
+# run failed or passed.
+#
+^[A-Z]+0/\S+:\s+\S+\s+@\S+: [0-9]+ tests \([0-9]+ passed, [0-9]+ failed, [0-9]+ blocked, [0-9]+ skipped\).*$

.known-issues/testcases/skip.conf

@@ -0,0 +1,4 @@
+#
+# Skip line when test case is eliminated due to filters
+#
+^SKIP0/\S+\s+\S+: No targets can be used \(all [0-9]+ selected from [0-9]+ available eliminated by testcase filtering\)$

.mailmap

@@ -5,3 +5,17 @@ Leona Cook <leonax.cook@intel.com> <lsc@hackeress.com>
 Leona Cook <leonax.cook@intel.com> <leonax.cook@intel.com>
 Thomas Heeley <thomas.heeley@intel.com> <thomas.heeley@intel.com>
 Shuang He <shuang.he@intel.com> <shuang.he@intel.com>
+Chuck Jordan <cjordan@synopsys.com> <cjordan@synopsys.com>
+Jeremie Garcia <jeremie.garcia@intel.com> <jeremie.garcia@intel.com>
+Bit Pathe <bitpathe@gmail.com> <bitpathe@gmail.com>
+Carles Cufi <carles.cufi@nordicsemi.no> <carles.cufi@nordicsemi.no>
+Kuo-Lang Tseng <kuo-lang.tseng@intel.com> <kuo-lang.tseng@intel.com>
+Gerardo Aceves <gerardo.aceves@intel.com> <gerardo.aceves@intel.com>
+Evan Couzens <evanx.couzens@intel.com> <evanx.couzens@intel.com>
+Lei Liu <lei.a.liu@intel.com> <lei.a.liu@intel.com>
+Douglas Su <d0u9.su@outlook.com> <d0u9.su@outlook.com>
+Keren Siman-Tov <keren.siman-tov@intel.com> <keren.siman-tov@intel.com>
+Naga Raja Rao Tulasi <tulasi.r@tcs.com> <tulasi.r@tcs.com>
+Felipe Neves <ryukokki.felipe@gmail.com> <ryukokki.felipe@gmail.com>
+Amir Kaplan <amir.kaplan@intel.com> <amir.kaplan@intel.com>
+Anas Nashif <anas.nashif@intel.com> <anas.nashif@intel.com>

Kbuild

@@ -1,11 +1,5 @@
 # vim: filetype=make
 
-ifneq ($(strip $(CONFIG_MAX_NUM_TASK_IRQS)),)
-ifneq (${CONFIG_MAX_NUM_TASK_IRQS},0)
-TASK_IRQS=y
-endif
-endif
-
 ifneq ("$(wildcard $(MDEF_FILE))","")
 MDEF_FILE_PATH=$(strip $(MDEF_FILE))
 else
@@ -14,6 +8,20 @@ MDEF_FILE_PATH=$(strip $(PROJECT_BASE)/$(MDEF_FILE))
 endif
 endif
 
+ifeq (${CONFIG_NUM_COMMAND_PACKETS},)
+CONFIG_NUM_COMMAND_PACKETS=0
+endif
+ifeq (${CONFIG_NUM_TIMER_PACKETS},)
+CONFIG_NUM_TIMER_PACKETS=0
+endif
+ifeq (${CONFIG_NUM_TASK_PRIORITIES},)
+CONFIG_NUM_TASK_PRIORITIES=$(CONFIG_NUM_PREEMPT_PRIORITIES)
+endif
+
+ifeq ($(ARCH),x86)
+TASKGROUP_SSE="  TASKGROUP SSE"
+endif
+
 define filechk_prj.mdef
 	(echo "% WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!"; \
 	echo; \
@@ -25,19 +33,9 @@ define filechk_prj.mdef
 	echo "% ==============";\
 	echo "  TASKGROUP EXE";\
 	echo "  TASKGROUP SYS";\
-	echo "  TASKGROUP FPU";\
-	echo "  TASKGROUP SSE";\
+	echo "  TASKGROUP FPU_LEGACY";\
+	echo $(TASKGROUP_SSE);\
 	echo; \
-	if test "$(TASK_IRQS)" = "y"; then \
-		echo "% Task IRQ objects";\
-		echo "% EVENT    NAME              HANDLER"; \
-		echo "% ======================================="; \
-		i=0; \
-		while [ $$i -lt $(CONFIG_MAX_NUM_TASK_IRQS) ]; do \
-			echo "  EVENT    _TaskIrqEvt$$i     NULL"; \
-		i=$$(($$i+1));\
-		done; \
-	fi; \
 	if test -e "$(MDEF_FILE_PATH)"; then \
 		cat $(MDEF_FILE_PATH); \
 	fi;)
@@ -47,8 +45,15 @@ misc/generated/sysgen/prj.mdef:	$(MDEF_FILE_PATH) \
 				include/config/auto.conf FORCE
 	$(call filechk,prj.mdef)
 
-misc/generated/sysgen/kernel_main.c: misc/generated/sysgen/prj.mdef
-	$(Q)$(srctree)/scripts/sysgen $(CURDIR)/misc/generated/sysgen/prj.mdef $(CURDIR)/misc/generated/sysgen/
+sysgen_cmd=$(strip \
+	$(PYTHON) $(srctree)/scripts/sysgen \
+	-i $(CURDIR)/misc/generated/sysgen/prj.mdef \
+	-o $(CURDIR)/misc/generated/sysgen/ \
+)
+
+misc/generated/sysgen/kernel_main.c: misc/generated/sysgen/prj.mdef \
+				     $(srctree)/scripts/sysgen
+	$(Q)$(sysgen_cmd)
 
 define filechk_configs.c
 	(echo "/* file is auto-generated, do not modify ! */"; \
@@ -68,13 +73,15 @@ misc/generated/configs.c: include/config/auto.conf FORCE
 	$(call filechk,configs.c)
 
 targets := misc/generated/configs.c
+targets += include/generated/generated_dts_board.h
 targets += include/generated/offsets.h
 
 
 always := misc/generated/configs.c
+always += include/generated/generated_dts_board.h
 always += include/generated/offsets.h
 
-ifeq ($(CONFIG_MICROKERNEL),y)
+ifeq ($(CONFIG_MDEF),y)
 targets += misc/generated/sysgen/kernel_main.c
 always += misc/generated/sysgen/kernel_main.c
 endif
@@ -83,18 +90,10 @@ define rule_cc_o_c_1
 	$(call echo-cmd,cc_o_c_1) $(cmd_cc_o_c_1);
 endef
 
-OFFSETS_INCLUDE = $(strip \
-		-include $(CURDIR)/include/generated/autoconf.h \
-		-I $(srctree)/include \
-		-I $(CURDIR)/include/generated \
-		-I $(srctree)/kernel/microkernel/include \
-		-I $(srctree)/kernel/nanokernel/include \
-		-I $(srctree)/lib/libc/minimal/include \
-		-I $(srctree)/arch/${ARCH}/include )
+cmd_cc_o_c_1 = $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(ZEPHYRINCLUDE) -c -o $@ $<
 
-cmd_cc_o_c_1 = $(CC) $(KBUILD_CFLAGS) $(OFFSETS_INCLUDE) -c -o $@ $<
-
-arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c
+arch/$(ARCH)/core/offsets/offsets.o: arch/$(ARCH)/core/offsets/offsets.c $(KCONFIG_CONFIG) \
+				include/generated/generated_dts_board.h
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed,cc_o_c_1)
 
@@ -113,6 +112,31 @@ define offsetchk
 endef
 
 include/generated/offsets.h: arch/$(ARCH)/core/offsets/offsets.o \
-					include/config/auto.conf FORCE
+			     include/config/auto.conf FORCE
 	$(call offsetchk,arch/$(ARCH)/core/offsets/offsets.o)
 
+ifeq ($(CONFIG_HAS_DTS),y)
+define filechk_generated_dts_board.h
+	(echo "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */"; \
+		extract_dts_includes.py dts/$(ARCH)/$(BOARD_NAME).dts_compiled $(ZEPHYR_BASE)/dts/$(ARCH)/yaml; \
+		if test -e $(ZEPHYR_BASE)/dts/$(ARCH)/$(BOARD_NAME).fixup; then \
+			echo; echo; \
+			echo "/* Following definitions fixup the generated include */"; \
+			echo; \
+			cat $(ZEPHYR_BASE)/dts/$(ARCH)/$(BOARD_NAME).fixup; \
+		fi; \
+		)
+endef
+else
+define filechk_generated_dts_board.h
+	(echo "/* WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY! */";)
+endef
+endif
+
+
+include/generated/generated_dts_board.h: include/config/auto.conf FORCE
+ifeq ($(CONFIG_HAS_DTS),y)
+	$(Q)$(MAKE) $(build)=dts/$(ARCH)
+endif
+	$(call filechk,generated_dts_board.h)
+

Kconfig

@@ -3,17 +3,7 @@
 #
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 mainmenu "Zephyr Kernel Configuration"
 

Kconfig.zephyr

@@ -4,21 +4,11 @@
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2016 Intel Corporation
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 config KERNELVERSION
-        string
-        option env="KERNELVERSION"
+	string
+	option env="KERNELVERSION"
 
 source "arch/Kconfig"
 
@@ -30,12 +20,20 @@ source "net/Kconfig"
 
 source "misc/Kconfig"
 
+source "lib/Kconfig"
+
+source "subsys/Kconfig"
+
+source "ext/Kconfig"
+
+source "tests/Kconfig"
+
 #
 # The following are for Kconfig files for default values only.
 # These should be parsed at the end.
 #
-# Board defaults should be parsed before SoC defaults
-# because board usually overrides them.
+# Board defaults should be parsed after SoC defaults
+# because board usually overrides SoC values.
 #
-source "boards/*/Kconfig.defconfig"
 source "arch/*/soc/*/Kconfig.defconfig"
+source "boards/*/*/Kconfig.defconfig"

MAINTAINERS

@@ -0,0 +1,510 @@
+Originally from the Linux Kernel.
+# Licensed under the terms of the GNU GPL License version 2
+
+Descriptions of section entries:
+
+	P: Person (obsolete)
+	M: Mail patches to: FullName <address@domain>
+	R: Designated reviewer: FullName <address@domain>
+	   These reviewers should be CCed on patches.
+	L: Mailing list that is relevant to this area
+	W: Web-page with status/info
+	Q: Patchwork web based patch tracking system site
+	T: SCM tree type and location.
+	   Type is one of: git, hg, quilt, stgit, topgit
+	S: Status, one of the following:
+	   Supported:	Someone is actually paid to look after this.
+	   Maintained:	Someone actually looks after it.
+	   Odd Fixes:	It has a maintainer but they don't have time to do
+			much other than throw the odd patch in. See below..
+	   Orphan:	No current maintainer [but maybe you could take the
+			role as you write your new code].
+	   Obsolete:	Old code. Something tagged obsolete generally means
+			it has been replaced by a better system and you
+			should be using that.
+	F: Files and directories with wildcard patterns.
+	   A trailing slash includes all files and subdirectory files.
+	   F:	drivers/net/	all files in and below drivers/net
+	   F:	drivers/net/*	all files in drivers/net, but not below
+	   F:	*/net/*		all files in "any top level directory"/net
+	   One pattern per line.  Multiple F: lines acceptable.
+	N: Files and directories with regex patterns.
+	   N:	[^a-z]tegra	all files whose path contains the word tegra
+	   One pattern per line.  Multiple N: lines acceptable.
+	   scripts/get_maintainer.pl has different behavior for files that
+	   match F: pattern and matches of N: patterns.  By default,
+	   get_maintainer will not look at git log history when an F: pattern
+	   match occurs.  When an N: match occurs, git log history is used
+	   to also notify the people that have git commit signatures.
+	X: Files and directories that are NOT maintained, same rules as F:
+	   Files exclusions are tested before file matches.
+	   Can be useful for excluding a specific subdirectory, for instance:
+	   F:	net/
+	   X:	net/ipv6/
+	   matches all files in and below net excluding net/ipv6/
+	K: Keyword perl extended regex pattern to match content in a
+	   patch or file.  For instance:
+	   K: of_get_profile
+	      matches patches or files that contain "of_get_profile"
+	   K: \b(printk|pr_(info|err))\b
+	      matches patches or files that contain one or more of the words
+	      printk, pr_info or pr_err
+	   One regex pattern per line.  Multiple K: lines acceptable.
+
+Note: For the hard of thinking, this list is meant to remain in alphabetical
+order. If you could add yourselves to it in alphabetical order that would be
+so much easier [Ed]
+
+Maintainers List (try to look for most precise areas first)
+
+		-----------------------------------
+
+ARC ARCHITECTURE
+M:	Ruud Derwig <Ruud.Derwig@synopsys.com>
+M:	Chuck Jordan <cjordan@synopsys.com>
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+S:	Supported
+F:	arch/arc/
+F:	include/arch/arc/
+F:	boards/arc/
+
+ARM ARCHITECTURE
+M:	Maureen Helm <maureen.helm@nxp.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
+S:	Supported
+F:	arch/arm/
+F:	include/arch/arm/
+F:	boards/arm/
+
+ARM CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS)
+M:	Maureen Helm <maureen.helm@nxp.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
+S:	Supported
+F:	ext/hal/cmsis/
+
+BOARDS/ARC - ARDUINO 101 SSS
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/arc/arduino_101_sss/
+
+BOARDS/ARC - EM Starterkit
+M:	Chuck Jordan <cjordan@synopsys.com>
+S:	Supported
+F:	boards/arc/em_starterkit/
+
+BOARDS/ARC - QUARK SE C1000 SS Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/arc/quark_se_c1000_ss_devboard/
+
+BOARDS/ARM - 96Boards CARBON
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/96b_carbon/
+
+BOARDS/ARM - 96Boards NITROGEN
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+S:	Supported
+F:	boards/arm/96b_nitrogen/
+
+BOARDS/ARM - ARDUINO 101 BLE
+M:	Johan Hedberg <johan.hedberg@intel.com>
+S:	Supported
+F:	boards/arm/arduino_101_ble/
+
+BOARDS/ARM - CC3200 LAUNCHXL
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      boards/arm/cc3200_launchxl/
+
+BOARDS/ARM - NXP FRDM-K64F
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	boards/arm/frdm_k64f/
+
+BOARDS/ARM - NXP FRDM-KW41Z
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	boards/arm/frdm_kw41z/
+
+BOARDS/ARM - NXP Hexiwear
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	boards/arm/hexiwear_k64/
+
+BOARDS/ARM - NORDIC NRF51 REDBEAR BLENANO
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/nrf51_blenano/
+
+BOARDS/ARM - NORDIC NRF52 PCA10040
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	boards/arm/nrf52_pca10040/
+
+BOARDS/ARM - NUCLEO-64 F401RE Devboard
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/nucleo_f401re/
+
+BOARDS/ARM - ARM LTD V2M Beetle
+M:	Vincenzo Frascino <vincenzo.frascino@linaro.org>
+S:	Supported
+F:	boards/arm/v2m_beetle/
+
+BOARDS/NIOS2 - ALTERA MAX10
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	boards/nios2/altera_max10/
+
+BOARDS/X86 - ARDUINO 101
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/arduino_101/
+
+BOARDS/X86 - Galileo
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/galileo/
+
+BOARDS/X86 - QUARK D2000 Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/quark_d2000/
+
+BOARDS/X86 - QUARK SE C1000 Devboard
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	boards/x86/quark_se_c1000/
+
+BLUETOOTH
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Luiz Augusto von Dentz <luiz.dentz@gmail.com>
+M:	Szymon Janc <szymon.janc@gmail.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/bluetooth/bluetooth.html
+F:	subsys/bluetooth/
+F:	include/bluetooth/
+F:	include/drivers/bluetooth/
+F:	drivers/bluetooth/
+F:	samples/bluetooth/
+F:	tests/bluetooth/
+F:	doc/subsystems/bluetooth/
+
+BLUETOOTH CONTROLLER
+M:	Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	subsys/bluetooth/controller/
+
+CC3200 SDK
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      ext/hal/cc3200sdk/
+
+CC32XX SOC - TI SIMPLELINK
+M:      Gil Pitney <gil.pitney@linaro.org>
+S:      Supported
+F:      arch/arm/soc/ti_simplelink/
+
+DOCUMENTATION
+M:	Kinder, David <david.b.kinder@intel.com>
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	doc/
+F:	*.rst
+F:	*/*.rst
+F:	*/*/*.rst
+F:	*/*/*/*.rst
+F:	*/*/*/*/*.rst
+F:	*/*/*/*/*/*.rst
+F:	*/*/*/*/*/*/*.rst
+F:	*/*/*/*/*/*/*/*.rst
+F:	*/*/*/*/*/*/*/*/*.rst
+
+FILE SYSTEM
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	ext/fs/
+F:	subsys/fs/
+F:	include/fs/
+F:	include/fs.h
+F:	samples/fs/
+
+FLASH DRIVER
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/flash/
+
+INTERRUPTS
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	drivers/interrupt_controller/
+F:	arch/arc/core/
+F:	arch/arm/core/
+F:	arch/nios2/core/
+F:	arch/x86/core/
+F:	include/irq.h
+F:	include/arch/x86/arch.h
+F:	include/arch/arm/cortex_m/irq.h
+F:	include/arch/nios2/arch.h
+F:	include/arch/arc/arch.h
+F:	include/arch/arc/v2/irq.h
+F:	include/drivers/loapic.h
+F:	include/drivers/ioapic.h
+F:	include/drivers/mvic.h
+
+KERNEL CORE
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Andrew Boie <andrew.p.boie@intel.com>
+M:	Andy Ross <andrew.j.ross@intel.com>
+S:	Supported
+F:	kernel/
+F:	include/nanokernel.h
+F:	include/microkernel.h
+F:	include/misc/
+F:	include/toolchain/
+F:	include/atomic.h
+F:	include/cache.h
+F:	include/init.h
+F:	include/irq.h
+F:	include/irq_offload.h
+F:	include/kernel_version.h
+F:	include/linker-defs.h
+F:	include/linker-tool-gcc.h
+F:	include/linker-tool.h
+F:	include/section_tags.h
+F:	include/sections.h
+F:	include/shared_irq.h
+F:	include/sw_isr_table.h
+F:	include/sys_clock.h
+F:	include/sys_io.h
+F:	include/toolchain.h
+F:	include/zephyr.h
+F:	include/kernel.h
+F:	include/legacy.h
+F:	tests/kernel/
+
+KNOWN ISSUES
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+M:	Genaro Saucedo <genaro.saucedo.tejada@intel.com>
+F:	.known-issues/
+
+
+MAINTAINERS
+M:	Genaro Saucedo <genaro.saucedo.tejada@intel.com>
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Perez-Gonzalez, Inaky <inaky.perez-gonzalez@intel.com>
+S:	Supported
+F:	MAINTAINERS
+
+MBEDTLS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Jithu Joseph <jithu.joseph@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	ext/lib/crypto/mbedtls/
+F:	samples/net/mbedtls_sslclient/
+F:	tests/crypto/test_mbedtls/
+
+MCUXPRESSO SOFTWARE DEVELOPMENT KIT (MCUX)
+M:	Maureen Helm <maureen.helm@nxp.com>
+S:	Supported
+F:	ext/hal/nxp/mcux/
+
+MPS2 - ARM LTD CORTEX-M PROTOTYPING SYSTEM
+M:	Vincenzo Frascino <vincenzo.frascino@linaro.org>
+S:	Supported
+F:	arch/arm/soc/arm/mps2/
+F:	boards/arm/mps2/
+
+NETWORKING
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/networking/networking.html
+F:	subsys/net/ip/
+F:	subsys/net/lib/
+F:	include/net/
+F:	samples/net/
+F:	tests/net/
+F:	tests/net/lib/
+F:	drivers/ethernet/
+F:	drivers/ieee802154/
+F:	drivers/slip/
+
+NETWORK APPLICATIONS
+M:	Flavio Santes <flavio.santes@intel.com>
+S:	Supported
+F:	subsys/net/lib/dns/
+F:	subsys/net/lib/http/
+F:	subsys/net/lib/mqtt/
+F:	samples/net/dns_client/
+F:	samples/net/http_server/
+F:	samples/net/mqtt_publisher/
+F:	tests/net/lib/http_header_fields/
+F:	tests/net/lib/mqtt_packet/
+
+NETWORK BUFFERS
+M:	Johan Hedberg <johan.hedberg@intel.com>
+M:	Jukka Rissanen <jukka.rissanen@linux.intel.com>
+M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/networking/buffers.html
+F:	subsys/net/buf.c
+F:	include/net/buf.h
+F:	tests/net/buf/
+
+NIOS II
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	arch/nios2/
+F:	include/arch/nios2/
+F:	drivers/serial/uart_altera_jtag.c
+F:	drivers/timer/altera_avalon_timer.c
+F:	tests/kernel/test_intmath/
+F:	boards/nios2/
+
+NORDIC MDK
+M:	Carles Cufi <carles.cufi@nordicsemi.no>
+S:	Supported
+F:	ext/hal/nordic/mdk/
+
+POWER MANAGEMENT
+M:	Ramesh Thomas <ramesh.thomas@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	arch/x86/core/crt0.S
+F:	include/device.h
+F:	include/init.h
+F:	include/power.h
+F:	kernel/k_idle.c
+F:	kernel/device.c
+F:	samples/power/
+
+QMSI
+M:	Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	ext/hal/qmsi/
+
+QMSI DRIVERS
+M:	Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
+M:	Baohong Liu <baohong.liu@intel.com>
+M:	Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+S:	Supported
+F:	drivers/*/*qmsi*
+F:	drivers/*/*/*qmsi*
+
+QUARK D2000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_d2000/
+
+QUARK SE C1000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_se_c1000/
+
+QUARK X1000 SOC
+M:      Anas Nashif <anas.nashif@intel.com>
+S:	Supported
+F:	arch/x86/soc/intel_quark/quark_x1000/
+
+SANITYCHECK
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	scripts/sanitycheck
+F:	scripts/expr_parser.py
+F:	scripts/sanity_chk/
+
+SENSOR DRIVERS
+M:	Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
+M:	Murtaza Alexandru <murtaza.alexandru1995@gmail.com>
+S:	Supported
+W:	https://www.zephyrproject.org/doc/subsystems/sensor.html
+F:	include/sensor.h
+F:	drivers/sensor/
+F:	samples/sensor/
+
+STM32CUBE SDK
+M:	Erwan Gouriou <erwan.gouriou@linaro.org>
+S:	Supported
+F:	ext/hal/st/stm32cube/
+
+STM32F4X SoC FAMILY and DRIVERS
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	arch/arm/soc/st_stm32/stm32f4/
+F:	drivers/pinmux/stm32/
+F:	drivers/gpio/*stm32*
+F:	drivers/clock_control/*stm32f4*
+
+TINYCRYPT
+M:	Constanza Heath <constanza.m.heath@intel.com>
+M:	Flavio Santes <flavio.santes@intel.com>
+S:	Supported
+F:	ext/lib/crypto/tinycrypt/
+F:	tests/crypto/
+
+SPI
+M:	Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
+S:	Supported
+F:	drivers/spi/
+F:	include/spi.h
+F:	tests/drivers/spi_test/
+
+USB
+M:	Jithu Joseph <jithu.joseph@intel.com>
+S:	Supported
+F:	subsys/usb
+F:	drivers/usb
+F:	samples/usb
+
+X86 ARCH
+M:	Benjamin Walsh <benjamin.walsh@windriver.com>
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	arch/x86/
+F:	include/arch/x86/
+F:	boards/x86/
+
+XTENSA ARCH
+M:	Andrew Boie <andrew.p.boie@intel.com>
+S:	Supported
+F:	arch/xtensa
+F:	include/arch/xtensa/
+F:	boards/xtensa/
+
+RISCV32 ARCH
+M:	Jean-Paul Etienne <fractalclone@gmail.com>
+S:	Supported
+F:	arch/riscv32
+F:	include/arch/riscv32
+F:	boards/riscv32
+F:	drivers/serial/uart_riscv_qemu.c
+F:	drivers/timer/pulpino_timer.c
+F:	drivers/timer/riscv_machine_timer.c
+F:	drivers/gpio/gpio_pulpino.c
+
+ZOAP
+M:	Vinicius Costa Gomes <vinicius.gomes@intel.com>
+S:	Supported
+F:	subsys/net/lib/zoap/
+F:	samples/net/zoap_client/
+F:	samples/net/zoap_server/
+F:	tests/net/lib/zoap/
+
+THE REST
+M:	Anas Nashif <anas.nashif@intel.com>
+M:	Kumar Gala <kumar.gala@linaro.org>
+L:	devel@lists.zephyrproject.com
+T:	git https://gerrit.zephyrproject.org/r/a/zephyr
+S:	Buried alive in reporters
+F:	*
+F:	*/

Makefile

@@ -1,5 +1,5 @@
 VERSION_MAJOR 	   = 1
-VERSION_MINOR 	   = 2
+VERSION_MINOR 	   = 7
 PATCHLEVEL 	   = 0
 VERSION_RESERVED   = 0
 EXTRAVERSION       =
@@ -28,6 +28,9 @@ ifeq (MINGW, $(findstring MINGW, $(UNAME)))
 HOST_OS=MINGW
 PWD_OPT=-W
 DISABLE_TRYRUN=y
+CPATH ?= $(MIGW_DIR)/include
+LIBRARY_PATH ?= $(MINGW_DIR)/lib
+export CPATH LIBRARY_PATH
 else ifeq (Linux, $(findstring Linux, $(UNAME)))
 HOST_OS=Linux
 else ifeq (Darwin, $(findstring Darwin, $(UNAME)))
@@ -46,6 +49,7 @@ unexport GREP_OPTIONS
 
 DQUOTE = "
 #This comment line is to fix the highlighting of some editors due the quote effect."
+export DQUOTE
 
 # We are using a recursive build, so we need to do a little thinking
 # to get the ordering right.
@@ -214,7 +218,7 @@ objtree		:= .
 src		:= $(srctree)
 obj		:= $(objtree)
 
-VPATH		:= $(srctree)
+VPATH		:= $(SOURCE_DIR_PARENT) $(srctree)
 
 export srctree objtree VPATH
 
@@ -263,8 +267,8 @@ CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
 	  else if [ -x /bin/bash ]; then echo /bin/bash; \
 	  else echo sh; fi ; fi)
 
-HOSTCC       = gcc
-HOSTCXX      = g++
+HOSTCC       ?= gcc
+HOSTCXX      ?= g++
 HOSTCFLAGS   = -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer -std=gnu89
 HOSTCXXFLAGS = -O2
 
@@ -281,15 +285,6 @@ KBUILD_BUILTIN := 1
 export KBUILD_BUILTIN
 export KBUILD_CHECKSRC KBUILD_SRC
 
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
 # Look for make include files relative to root of kernel src
 MAKEFLAGS += --include-dir=$(srctree)
 
@@ -307,8 +302,8 @@ ifeq ($(USE_CCACHE),1)
 CC		= $(CCACHE) $(CROSS_COMPILE)gcc
 CXX		= $(CCACHE) $(CROSS_COMPILE)g++
 else
-CC		= $(CROSS_COMPILE)gcc
-CXX		= $(CROSS_COMPILE)g++
+CC		?= $(CROSS_COMPILE)gcc
+CXX		?= $(CROSS_COMPILE)g++
 endif
 CPP		= $(CC) -E
 AR		= $(CROSS_COMPILE)ar
@@ -317,9 +312,15 @@ STRIP		= $(CROSS_COMPILE)strip
 OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
 GDB		= $(CROSS_COMPILE)gdb
+READELF		= $(CROSS_COMPILE)readelf
 AWK		= awk
-GENIDT		= scripts/gen_idt/gen_idt
+ifeq ($(PREBUILT_HOST_TOOLS),)
 GENOFFSET_H	= scripts/gen_offset_header/gen_offset_header
+FIXDEP		= scripts/basic/fixdep
+else
+GENOFFSET_H	= $(PREBUILT_HOST_TOOLS)/gen_offset_header
+FIXDEP		= $(PREBUILT_HOST_TOOLS)/fixdep
+endif
 PERL		= perl
 PYTHON		= python
 CHECK		= sparse
@@ -345,19 +346,26 @@ endif
 USERINCLUDE    := -include $(CURDIR)/include/generated/autoconf.h
 
 SOC_NAME = $(subst $(DQUOTE),,$(CONFIG_SOC))
+SOC_SERIES = $(subst $(DQUOTE),,$(CONFIG_SOC_SERIES))
+SOC_FAMILY = $(subst $(DQUOTE),,$(CONFIG_SOC_FAMILY))
+
 override ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 BOARD_NAME = $(subst $(DQUOTE),,$(CONFIG_BOARD))
 KERNEL_NAME = $(subst $(DQUOTE),,$(CONFIG_KERNEL_BIN_NAME))
 KERNEL_ELF_NAME = $(KERNEL_NAME).elf
 KERNEL_BIN_NAME = $(KERNEL_NAME).bin
+KERNEL_HEX_NAME = $(KERNEL_NAME).hex
+KERNEL_STAT_NAME = $(KERNEL_NAME).stat
 
-export SOC_NAME BOARD_NAME ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME
+export SOC_FAMILY SOC_SERIES SOC_PATH SOC_NAME BOARD_NAME
+export ARCH KERNEL_NAME KERNEL_ELF_NAME KERNEL_BIN_NAME KERNEL_HEX_NAME
 # Use ZEPHYRINCLUDE when you must reference the include/ directory.
 # Needed to be compatible with the O= option
 ZEPHYRINCLUDE    = \
+		-I$(srctree)/kernel/include \
 		-I$(srctree)/arch/$(ARCH)/include \
-		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_NAME) \
-		-I$(srctree)/boards/$(BOARD_NAME) \
+		-I$(srctree)/arch/$(ARCH)/soc/$(SOC_PATH) \
+		-I$(srctree)/boards/$(ARCH)/$(BOARD_NAME) \
 		$(if $(KBUILD_SRC), -I$(srctree)/include) \
 		-I$(srctree)/include \
 		-I$(CURDIR)/include/generated \
@@ -365,19 +373,19 @@ ZEPHYRINCLUDE    = \
 		$(USERINCLUDE) \
 		$(STDINCLUDE)
 
-KBUILD_CPPFLAGS := -DKERNEL
+KBUILD_CPPFLAGS := -DKERNEL -D__ZEPHYR__=1
 
 KBUILD_CFLAGS   := -c -g -std=c99 \
-		-fno-asynchronous-unwind-tables \
-		-fno-omit-frame-pointer \
 		-Wall \
+		-Wformat \
+		-Wformat-security \
+		-D_FORTIFY_SOURCE=2 \
 		-Wno-format-zero-length \
 		-Wno-main -ffreestanding
 
 KBUILD_CXXFLAGS   := -c -g -std=c++11 \
 		-fno-reorder-functions \
 		-fno-asynchronous-unwind-tables \
-		-fno-omit-frame-pointer \
 		-fcheck-new \
 		-fno-defer-pop -Wall \
 		-Wno-unused-but-set-variable \
@@ -386,7 +394,7 @@ KBUILD_CXXFLAGS   := -c -g -std=c++11 \
 		-ffunction-sections -fdata-sections \
 		-fno-rtti -fno-exceptions
 
-KBUILD_AFLAGS   := -c -g -xassembler-with-cpp
+KBUILD_AFLAGS   := -c -g -xassembler-with-cpp -D_ASMLANGUAGE
 
 LDFLAGS += $(call ld-option,-nostartfiles)
 LDFLAGS += $(call ld-option,-nodefaultlibs)
@@ -395,17 +403,33 @@ LDFLAGS += $(call ld-option,-static)
 
 KERNELVERSION = $(VERSION_MAJOR)$(if $(VERSION_MINOR),.$(VERSION_MINOR)$(if $(PATCHLEVEL),.$(PATCHLEVEL)))$(EXTRAVERSION)
 
-export VERSION_MAJOR VERSION_MINOR PATCHLEVEL VERSION_RESERVED EXTRAVERSION
-export KERNELRELEASE KERNELVERSION
-export ARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC CXX
-export CPP AR NM STRIP OBJCOPY OBJDUMP GDB
-export MAKE AWK INSTALLKERNEL PERL PYTHON GENIDT GENOFFSET_H
-export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS
+exports += VERSION_MAJOR VERSION_MINOR PATCHLEVEL VERSION_RESERVED EXTRAVERSION
+exports += KERNELRELEASE KERNELVERSION
+exports += ARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC CXX
+exports += CPP AR NM STRIP OBJCOPY OBJDUMP GDB
+exports += MAKE AWK INSTALLKERNEL PERL PYTHON GENOFFSET_H
+exports += HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS
 
-export KBUILD_CPPFLAGS NOSTDINC_FLAGS ZEPHYRINCLUDE OBJCOPYFLAGS LDFLAGS
-export KBUILD_CFLAGS KBUILD_CXXFLAGS CFLAGS_GCOV KBUILD_AFLAGS AFLAGS_KERNEL
-export KBUILD_ARFLAGS
+exports += KBUILD_CPPFLAGS NOSTDINC_FLAGS ZEPHYRINCLUDE OBJCOPYFLAGS LDFLAGS
+exports += KBUILD_CFLAGS KBUILD_CXXFLAGS CFLAGS_GCOV KBUILD_AFLAGS AFLAGS_KERNEL
+exports += KBUILD_ARFLAGS FIXDEP
 
+# Push the exports to sub-processes
+export $(exports)
+
+# Make the exports available to third-party build systems
+PHONY += outputexports
+outputexports: Makefile.export
+Makefile.export: include/config/auto.conf FORCE
+	$(call filechk,Makefile.export)
+
+define filechk_Makefile.export
+	(echo "# file is auto-generated, do not modify !"; \
+	echo "BOARD=$(BOARD)"; \
+	echo; \
+	$(foreach e,$(exports),echo $(e)=$($(e));) echo; \
+	echo "include $(O)/include/config/auto.conf";)
+endef
 
 # Files to ignore in find ... statements
 
@@ -420,10 +444,14 @@ export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
 
 # Basic helpers built in scripts/
 PHONY += scripts_basic
+ifeq ($(PREBUILT_HOST_TOOLS),)
 scripts_basic:
 	$(Q)$(MAKE) $(build)=scripts/basic
 	$(Q)$(MAKE) $(build)=scripts/gen_idt
 	$(Q)$(MAKE) $(build)=scripts/gen_offset_header
+else
+scripts_basic:
+endif
 
 # To avoid any implicit rule to kick in, define an empty command.
 scripts/basic/%: scripts_basic ;
@@ -515,9 +543,8 @@ PHONY += scripts
 scripts: scripts_basic include/config/auto.conf include/config/tristate.conf
 	$(Q)$(MAKE) $(build)=$(@)
 
-
-core-y := lib/ kernel/ misc/ net/ boards/ arch/
-drivers-y := drivers/
+# arch/ must be last here so that .gnu.linkonce magic for interrupts/exceptions
+# works as expected
 
 ifneq ($(strip $(MAKEFILE_APP_DIR)),)
 MAKEFILE_APP := $(realpath $(MAKEFILE_APP_DIR)/Makefile.app)
@@ -559,38 +586,40 @@ else
 include/config/auto.conf: ;
 endif # $(dot-config)
 
-ifdef CONFIG_TINYCRYPT
-# Objects we will link into the kernel / subdirs we need to visit
-KCRYPTO_DIR := lib/crypto/tinycrypt
-libs-y += $(KCRYPTO_DIR)/
- ZEPHYRINCLUDE += -I$(srctree)/lib/crypto/tinycrypt/include
-endif
+# kernel objects are built as a static library
+libs-y := kernel/
+core-y := lib/ misc/ boards/ ext/ subsys/ tests/ arch/
+drivers-y := drivers/
 
 ARCH = $(subst $(DQUOTE),,$(CONFIG_ARCH))
 export ARCH
+
+ifeq ($(CONFIG_DEBUG),y)
+KBUILD_CFLAGS += -Og
+else
+KBUILD_CFLAGS += -Os
+endif
+
 ifdef ZEPHYR_GCC_VARIANT
 include $(srctree)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
 else
+ifneq ($(MAKECMDGOALS),htmldocs)
 $(if $(CROSS_COMPILE),, \
      $(error ZEPHYR_GCC_VARIANT is not set. ))
 endif
-
-ifdef CONFIG_QMSI_DRIVERS
-LIB_INCLUDE_DIR += -L$(CONFIG_QMSI_INSTALL_PATH:"%"=%)/lib
-ALL_LIBS += qmsi
 endif
 
-ifdef CONFIG_MINIMAL_LIBC
-ZEPHYRINCLUDE += -I$(srctree)/lib/libc/minimal/include
-endif
+-include $(srctree)/ext/Makefile
+-include $(srctree)/lib/Makefile
 
-ifdef CONFIG_NEWLIB_LIBC
-ZEPHYRINCLUDE += $(TOOLCHAIN_CFLAGS)
-ALL_LIBS += c m
+ifneq ($(CC),)
+ifeq ($(shell $(CC) -v 2>&1 | grep -Ec "clang version|icx version"), 1)
+COMPILER := clang
+else
+COMPILER := gcc
+endif
+export COMPILER
 endif
-
-QEMU_BIN_PATH	?= /usr/bin
-QEMU		= $(QEMU_BIN_PATH)/$(QEMU_$(ARCH))
 
 # The all: target is the default when no target is given on the
 # command line.
@@ -608,11 +637,8 @@ KBUILD_CFLAGS += $(call cc-option,-fno-reorder-blocks,) \
                  $(call cc-option,-fno-partial-inlining)
 endif
 
-ifeq ($(CONFIG_DEBUG),y)
-KBUILD_CFLAGS  += -O0
-else
-KBUILD_CFLAGS  += -Os
-endif
+# Some GCC variants don't support these
+KBUILD_CFLAGS += $(call cc-option,-fno-asynchronous-unwind-tables,)
 
 ifeq ($(CONFIG_STACK_CANARIES),y)
 KBUILD_CFLAGS += $(call cc-option,-fstack-protector-all,)
@@ -620,10 +646,25 @@ else
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector,)
 endif
 
+ifeq ($(CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT),y)
+ifeq ($(CONFIG_OMIT_FRAME_POINTER),y)
+fp_arg := $(call cc-option,-fomit-frame-pointer,)
+else
+fp_arg := $(call cc-option,-fno-omit-frame-pointer,)
+endif
+endif
+KBUILD_CFLAGS += $(fp_arg)
+KBUILD_CXXFLAGS += $(fp_arg)
+
 KBUILD_CFLAGS += $(subst $(DQUOTE),,$(CONFIG_COMPILER_OPT))
 
 export LDFLAG_LINKERCMD
 
+ifeq ($(SOC_SERIES),)
+SOC_PATH = $(SOC_NAME)
+else
+SOC_PATH = $(SOC_FAMILY)/$(SOC_SERIES)
+endif
 include arch/$(ARCH)/Makefile
 
 KBUILD_CFLAGS += $(CFLAGS)
@@ -632,7 +673,6 @@ KBUILD_AFLAGS += $(CFLAGS)
 
 
 ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
 KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
 KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
 KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
@@ -645,8 +685,10 @@ else
 # Use make W=1 to enable this warning (see scripts/Makefile.build)
 KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)
 KBUILD_CFLAGS += $(call cc-option,-fno-reorder-functions)
+ifneq (${ZEPHYR_GCC_VARIANT},xcc)
 KBUILD_CFLAGS += $(call cc-option,-fno-defer-pop)
 endif
+endif
 
 # We trigger additional mismatches with less inlining
 ifdef CONFIG_DEBUG_SECTION_MISMATCH
@@ -655,6 +697,7 @@ endif
 
 # arch Makefile may override CC so keep this after arch Makefile is included
 NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+NOSTDINC_FLAGS += -isystem $(shell $(CC) -print-file-name=include-fixed)
 CHECKFLAGS     += $(NOSTDINC_FLAGS)
 
 # disable pointer signed / unsigned warnings in gcc 4.0
@@ -688,33 +731,45 @@ KBUILD_CFLAGS += $(KCFLAGS)
 
 # Use --build-id when available.
 
+LINKFLAGPREFIX ?= -Wl,
 LDFLAGS_zephyr += $(LDFLAGS)
-LDFLAGS_zephyr += $(call ld-option,-X)
-LDFLAGS_zephyr += $(call ld-option,-N)
-LDFLAGS_zephyr += $(call ld-option,--gc-sections)
-LDFLAGS_zephyr += $(call ld-option,--build-id=none)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-X)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)-N)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--gc-sections)
+LDFLAGS_zephyr += $(call cc-ldoption,$(LINKFLAGPREFIX)--build-id=none)
 
 LD_TOOLCHAIN ?= -D__GCC_LINKER_CMD__
 
 ifdef CONFIG_HAVE_CUSTOM_LINKER_SCRIPT
-KBUILD_LDS         := $(subst $(DQUOTE),,$(CONFIG_CUSTOM_LINKER_SCRIPT))
+KBUILD_LDS := $(subst $(DQUOTE),,$(PROJECT_BASE)/$(CONFIG_CUSTOM_LINKER_SCRIPT))
+ifeq ($(wildcard $(KBUILD_LDS)),)
+KBUILD_LDS := $(subst $(DQUOTE),,$(CONFIG_CUSTOM_LINKER_SCRIPT))
+endif
 else
 # Try a board specific linker file
-KBUILD_LDS := $(srctree)/boards/$(BOARD_NAME)/linker.cmd
+KBUILD_LDS := $(srctree)/boards/$(ARCH)/$(BOARD_NAME)/linker.ld
 
 # If not available, try an SoC specific linker file
 ifeq ($(wildcard $(KBUILD_LDS)),)
-KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/linker.cmd
+KBUILD_LDS         := $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/linker.ld
 endif
 endif
 
 export LD_TOOLCHAIN KBUILD_LDS
 
+ifdef MAKEFILE_TOOLCHAIN_DO_PASS2
+# KBUILD_CFLAGS known at this point.
+# We can now determine which multilib libraries to use
+include $(srctree)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
+endif
+
+QEMU		= $(addsuffix /,$(QEMU_BIN_PATH))$(QEMU_$(ARCH))
+
 # The all: target is the default when no target is given on the
 # command line.
 # This allow a user to issue only 'make' to build a kernel including modules
 # Defaults to zephyr, but the arch makefile usually adds further targets
-all: $(KERNEL_BIN_NAME)
+all: $(KERNEL_BIN_NAME) $(KERNEL_STAT_NAME)
 
 # Default kernel image to build when no specific target is given.
 # KBUILD_IMAGE may be overruled on the command line or
@@ -724,102 +779,107 @@ all: $(KERNEL_BIN_NAME)
 export KBUILD_IMAGE ?= zephyr
 
 zephyr-dirs	:= $(patsubst %/,%,$(filter %/, $(core-y) $(drivers-y) \
-		     $(libs-y) $(app-y)))
+		     $(libs-y)))
 
-zephyr-alldirs	:= $(sort $(zephyr-dirs) $(patsubst %/,%,$(filter %/, \
+# Workaround for some make notdir implementations that require
+# the paramenter not to end in "/".
+zephyr-app-dir-root-name := $(patsubst %/,%, $(SOURCE_DIR))
+
+zephyr-app-dir-root := $(abspath $(patsubst %, %/.., $(SOURCE_DIR)))
+
+zephyr-alldirs	:= $(sort $(zephyr-dirs) $(SOURCE_DIR) $(patsubst %/,%,$(filter %/, \
 		     $(core-) $(drivers-) $(libs-) $(app-))))
 
 core-y		:= $(patsubst %/, %/built-in.o, $(core-y))
-app-y		:= $(patsubst %/, %/built-in.o, $(app-y))
+app-y		:= $(patsubst %, %/built-in.o, $(notdir $(zephyr-app-dir-root-name)))
 drivers-y	:= $(patsubst %/, %/built-in.o, $(drivers-y))
 libs-y1		:= $(patsubst %/, %/lib.a, $(libs-y))
 libs-y2		:= $(patsubst %/, %/built-in.o, $(libs-y))
 libs-y		:= $(libs-y1) $(libs-y2)
 
-export KBUILD_ZEPHYR_MAIN := $(drivers-y) $(libs-y) $(app-y) $(core-y)
+# core-y must be last here. several arches use .gnu.linkonce magic
+# to register interrupt or exception handlers, and defaults under
+# arch/ (part of core-y) must be linked after drivers or libs.
+export KBUILD_ZEPHYR_MAIN := $(drivers-y) $(libs-y) $(core-y)
 export LDFLAGS_zephyr
 
-zephyr-deps := $(KBUILD_LDS) $(KBUILD_ZEPHYR_MAIN)
+zephyr-deps := $(KBUILD_LDS) $(KBUILD_ZEPHYR_MAIN) $(app-y)
 
 ALL_LIBS += $(TOOLCHAIN_LIBS)
 export ALL_LIBS
 
 LINK_LIBS := $(foreach l,$(ALL_LIBS), -l$(l))
 
-OUTPUT_FORMAT ?= elf32-i386
-OUTPUT_ARCH ?= i386
+quiet_cmd_ar_target = AR      $@
+# Do not put lib.a into libzephyr.a. lib.a files are to be linked separately to
+# the final image
+cmd_ar_target = rm -f $@; $(AR) rcT$(KBUILD_ARFLAGS) $@ \
+	$(filter-out %/lib.a, $(KBUILD_ZEPHYR_MAIN))
+libzephyr.a: $(zephyr-deps)
+	$(call cmd,ar_target)
 
 quiet_cmd_create-lnk = LINK    $@
       cmd_create-lnk =								\
 (										\
 	echo $(LDFLAGS_zephyr); 						\
-	echo "-Map ./$(KERNEL_NAME).map"; 					\
+	echo "$(LINKFLAGPREFIX)-Map=$(KERNEL_NAME).map"; 			\
 	echo "-L $(objtree)/include/generated";					\
 	echo "-u _OffsetAbsSyms -u _ConfigAbsSyms"; 				\
 	echo "-e __start"; 						 	\
-	echo "--start-group";							\
-	echo "--whole-archive $(KBUILD_ZEPHYR_APP) --no-whole-archive";         \
-	echo "$(KBUILD_ZEPHYR_MAIN)";						\
+	echo "$(LINKFLAGPREFIX)--start-group";					\
+	echo "$(LINKFLAGPREFIX)--whole-archive";				\
+	echo "$(KBUILD_ZEPHYR_APP)";						\
+	echo "$(app-y)";							\
+	echo "libzephyr.a";							\
+	echo "$(LINKFLAGPREFIX)--no-whole-archive";         			\
+	echo "$(filter %/lib.a, $(KBUILD_ZEPHYR_MAIN))";			\
 	echo "$(objtree)/arch/$(ARCH)/core/offsets/offsets.o"; 			\
-	echo "--end-group"; 							\
+	echo "$(LINKFLAGPREFIX)--end-group"; 					\
 	echo "$(LIB_INCLUDE_DIR) $(LINK_LIBS)";					\
 ) > $@
 
-$(KERNEL_NAME).lnk:
+$(KERNEL_NAME).lnk: $(zephyr-deps)
 	$(call cmd,create-lnk)
 
 linker.cmd: $(zephyr-deps)
 	$(Q)$(CC) -x assembler-with-cpp -nostdinc -undef -E -P \
 	$(LDFLAG_LINKERCMD) $(LD_TOOLCHAIN) -I$(srctree)/include \
+	-I$(SOURCE_DIR) \
 	-I$(objtree)/include/generated $(EXTRA_LINKER_CMD_OPT) $(KBUILD_LDS) -o $@
 
-final-linker.cmd: $(zephyr-deps)
-	$(Q)$(CC) -x assembler-with-cpp -nostdinc -undef -E -P \
-	$(LDFLAG_LINKERCMD) $(LD_TOOLCHAIN) -DFINAL_LINK -I$(srctree)/include \
-	-I$(objtree)/include/generated $(EXTRA_LINKER_CMD_OPT) $(KBUILD_LDS) -o $@
+PREBUILT_KERNEL = $(KERNEL_NAME)_prebuilt.elf
 
-TMP_ELF = .tmp_$(KERNEL_NAME).prebuilt
+$(PREBUILT_KERNEL): $(zephyr-deps) libzephyr.a $(KBUILD_ZEPHYR_APP) $(app-y) linker.cmd $(KERNEL_NAME).lnk
+	$(Q)$(CC) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
 
-$(TMP_ELF): $(zephyr-deps) $(KBUILD_ZEPHYR_APP) linker.cmd $(KERNEL_NAME).lnk
-	$(Q)$(LD) -T linker.cmd @$(KERNEL_NAME).lnk -o $@
+ASSERT_WARNING_STR := \
+    "\n      ------------------------------------------------------------" \
+    "\n      --- WARNING:  __ASSERT() statements are globally ENABLED ---" \
+    "\n      --- The kernel will run more slowly and uses more memory ---" \
+    "\n      ------------------------------------------------------------\n\n" \
 
-quiet_cmd_gen_idt = SIDT    $@
-      cmd_gen_idt =								\
-(										\
-	$(OBJCOPY) -I $(OUTPUT_FORMAT)  -O binary -j intList $< isrList.bin &&	\
-	$(GENIDT) -i isrList.bin -n $(CONFIG_IDT_NUM_VECTORS) -o staticIdt.bin 	\
-		-b int_vector_alloc.bin -m irq_int_vector_map.bin		\
-		-l $(CONFIG_MAX_IRQ_LINES) &&					\
-	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
-		--rename-section .data=staticIdt staticIdt.bin staticIdt.o &&	\
-	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
-		--rename-section .data=int_vector_alloc int_vector_alloc.bin	\
-		int_vector_alloc.o &&						\
-	$(OBJCOPY) -I binary -B $(OUTPUT_ARCH) -O $(OUTPUT_FORMAT) 		\
-	--rename-section .data=irq_int_vector_map irq_int_vector_map.bin 	\
-		irq_int_vector_map.o &&						\
-	rm staticIdt.bin irq_int_vector_map.bin int_vector_alloc.bin isrList.bin\
-)
+WARN_ABOUT_ASSERT := $(if $(CONFIG_ASSERT),echo -e -n $(ASSERT_WARNING_STR),true)
 
-staticIdt.o: $(TMP_ELF)
-	$(call cmd,gen_idt)
 
-quiet_cmd_lnk_elf = LINK    $@
-      cmd_lnk_elf =									\
-(											\
-	$(LD) -T final-linker.cmd @$(KERNEL_NAME).lnk staticIdt.o int_vector_alloc.o 	\
-	irq_int_vector_map.o -o $@;							\
-	${OBJCOPY} --change-section-address intList=${CONFIG_PHYS_LOAD_ADDR} $@ elf.tmp;\
-	$(OBJCOPY) -R intList elf.tmp $@;						\
-	rm elf.tmp									\
-)
+DEPRECATION_WARNING_STR := \
+    "\n      WARNING:  The board '$(BOARD)' is deprecated and will be" \
+    "\n      removed in version $(CONFIG_BOARD_DEPRECATED)\n\n"
+
+WARN_ABOUT_DEPRECATION := $(if $(CONFIG_BOARD_DEPRECATED),echo -e \
+				-n $(DEPRECATION_WARNING_STR),true)
 
 ifeq ($(ARCH),x86)
-$(KERNEL_ELF_NAME): staticIdt.o final-linker.cmd
-	$(call cmd,lnk_elf)
+# X86 with its IDT has very special handling for interrupt tables
+include $(srctree)/arch/x86/Makefile.idt
+else ifeq ($(CONFIG_GEN_ISR_TABLES),y)
+# Logic for interrupt tables created by scripts/gen_isr_tables.py
+include $(srctree)/arch/common/Makefile.gen_isr_tables
 else
-$(KERNEL_ELF_NAME): $(TMP_ELF)
-	@cp $(TMP_ELF) $(KERNEL_ELF_NAME)
+# Otherwise, nothing to do, prebuilt kernel is the real one
+$(KERNEL_ELF_NAME): $(PREBUILT_KERNEL)
+	@cp $(PREBUILT_KERNEL) $(KERNEL_ELF_NAME)
+	@$(WARN_ABOUT_ASSERT)
+	@$(WARN_ABOUT_DEPRECATION)
 endif
 
 
@@ -834,11 +894,28 @@ quiet_cmd_gen_bin = BIN     $@
 $(KERNEL_BIN_NAME): $(KERNEL_ELF_NAME)
 	$(call cmd,gen_bin)
 
+quiet_cmd_gen_hex = HEX     $@
+      cmd_gen_hex =                                                         \
+(                                                                           \
+   $(OBJCOPY) -S -O ihex -R .note -R .comment -R COMMON -R .eh_frame $< $@; \
+)
+
+$(KERNEL_HEX_NAME): $(KERNEL_ELF_NAME)
+	$(call cmd,gen_hex)
+
+$(KERNEL_STAT_NAME): $(KERNEL_BIN_NAME) $(KERNEL_ELF_NAME)
+	@$(READELF) -e $(KERNEL_ELF_NAME) > $@
+
+ram_report: $(KERNEL_STAT_NAME)
+	@$(srctree)/scripts/size_report -r -o $(O)
+rom_report: $(KERNEL_STAT_NAME)
+	@$(srctree)/scripts/size_report -F -o $(O)
+
 zephyr: $(zephyr-deps) $(KERNEL_BIN_NAME)
 
 # The actual objects are generated when descending,
 # make sure no implicit rule kicks in
-$(sort $(zephyr-deps)): $(zephyr-dirs) ;
+$(sort $(zephyr-deps)): $(zephyr-dirs) zephyr-app-dir ;
 
 # Handle descending into subdirectories listed in $(zephyr-dirs)
 # Preset locale variables to speed up the build process. Limit locale
@@ -850,6 +927,11 @@ PHONY += $(zephyr-dirs)
 $(zephyr-dirs): prepare scripts
 	$(Q)$(MAKE) $(build)=$@
 
+PHONY += zephyr-app-dir
+zephyr-app-dir: prepare scripts
+	$(Q)$(MAKE) $(build)=$(notdir $(zephyr-app-dir-root-name)) \
+		srctree=$(zephyr-app-dir-root)
+
 # Things we need to do before we recursively start building the kernel
 # or the modules are listed in "prepare".
 # A multi level approach is used. prepareN is processed before prepareN-1.
@@ -944,13 +1026,17 @@ depend dep:
 
 # Directories & files removed with 'make clean'
 CLEAN_DIRS  += $(MODVERDIR)
+CLEAN_DIRS  += $(MODVERDIR) dts/
 
 CLEAN_FILES += 	misc/generated/sysgen/kernel_main.c \
 		misc/generated/sysgen/sysgen.h \
 		misc/generated/sysgen/prj.mdef \
+		misc/generated/sysgen/micro_private_types.h \
+		misc/generated/sysgen/kernel_main.h \
+		include/generated/generated_dts_board.h \
 		.old_version .tmp_System.map .tmp_version \
 		.tmp_* System.map *.lnk *.map *.elf *.lst \
-		*.bin *.strip staticIdt.o linker.cmd final-linker.cmd
+		*.bin *.hex *.stat *.strip staticIdt.o linker.cmd
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config usr/include include/generated          \
@@ -967,9 +1053,9 @@ clean: rm-dirs  := $(CLEAN_DIRS)
 clean: rm-files := $(CLEAN_FILES)
 clean-dirs      := $(addprefix _clean_, . $(zephyr-alldirs) )
 
-PHONY += $(clean-dirs) clean archclean zephyrclean
-$(clean-dirs):
-	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
+PHONY += clean-dirs-target clean archclean zephyrclean
+clean-dirs-target:
+	$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$(clean-dirs))
 
 clean: archclean
 
@@ -1001,7 +1087,7 @@ distclean: mrproper
 # Brief documentation of the typical targets used
 # ---------------------------------------------------------------------------
 
-boards := $(wildcard $(srctree)/boards/*/*_defconfig)
+boards := $(wildcard $(srctree)/boards/*/*/*_defconfig)
 boards := $(sort $(notdir $(boards)))
 
 kconfig-help:
@@ -1024,9 +1110,14 @@ help:
 	@echo  'Other generic targets:'
 	@echo  '  all		  - Build all targets marked with [*]'
 	@echo  '* zephyr	  - Build a zephyr application'
-	@echo  '  qemu		  - Build a zephyr application and run it in qemu'
+	@echo  '  run		  - Build a zephyr application and run it if board supports emulation'
+	@echo  '  qemu		  - Build a zephyr application and run it in qemu [deprecated]'
+	@echo  '  qemugdb         - Same as 'qemu' but start a GDB server on port 1234 [deprecated]'
 	@echo  '  flash		  - Build and flash an application'
 	@echo  '  debug		  - Build and debug an application using GDB'
+	@echo  '  debugserver	  - Build and start a GDB server (port 1234 for Qemu targets)'
+	@echo  '  ram_report	  - Build and create RAM usage report'
+	@echo  '  rom_report	  - Build and create ROM usage report'
 	@echo  ''
 	@echo  'Supported Boards:'
 	@echo  ''
@@ -1066,7 +1157,7 @@ help-board-dirs := $(addprefix help-,$(board-dirs))
 
 help-boards: $(help-board-dirs)
 
-boards-per-dir = $(sort $(notdir $(wildcard $(srctree)/boards/$*/*_defconfig)))
+boards-per-dir = $(sort $(notdir $(wildcard $(srctree)/boards/*/$*/*_defconfig)))
 
 $(help-board-dirs): help-%:
 	@echo  'Architecture specific targets ($(ARCH) $*):'
@@ -1081,7 +1172,7 @@ $(help-board-dirs): help-%:
 %docs: FORCE
 	$(Q)$(MAKE) -C doc htmldocs
 
-clean: $(clean-dirs)
+clean: clean-dirs-target
 	$(call cmd,rmdirs)
 	$(call cmd,rmfiles)
 	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
@@ -1124,34 +1215,32 @@ tools/%: FORCE
 	$(Q)mkdir -p $(objtree)/tools
 	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS="$(filter --j% -j,$(MAKEFLAGS))" O=$(objtree) subdir=tools -C $(src)/tools/ $*
 
-QEMU_FLAGS = $(QEMU_FLAGS_$(ARCH)) -pidfile qemu.pid
+-include $(srctree)/boards/$(ARCH)/$(BOARD_NAME)/Makefile.board
 
-ifneq ($(QEMU_PIPE),)
-    # Send console output to a pipe, used for running automated sanity tests
-    QEMU_FLAGS += -serial pipe:$(QEMU_PIPE)
+ifneq ($(EMU_PLATFORM),)
+-include $(srctree)/scripts/Makefile.$(EMU_PLATFORM)
 else
-    QEMU_FLAGS += -serial mon:stdio
+run:
+	@echo ===================================================
+	@echo Emulation/Simulation not supported with this board.
+	@echo ===================================================
 endif
 
-qemu: zephyr
-	$(if $(QEMU_PIPE),,@echo "To exit from QEMU enter: 'CTRL+a, x'")
-	@echo '[QEMU] CPU: $(QEMU_CPU_TYPE_$(ARCH))'
-	$(if $(CONFIG_X86_IAMCU),python $(ZEPHYR_BASE)/scripts/qemu-machine-hack.py $(KERNEL_ELF_NAME))
-	$(Q)$(QEMU) $(QEMU_FLAGS) $(QEMU_EXTRA_FLAGS) -kernel $(KERNEL_ELF_NAME)
-
--include $(srctree)/boards/$(BOARD_NAME)/Makefile.board
 ifneq ($(FLASH_SCRIPT),)
 flash: zephyr
 	@echo "Flashing $(BOARD_NAME)"
 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/support/$(FLASH_SCRIPT) flash
-
-debug: zephyr
-	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/support/$(FLASH_SCRIPT) debug
 else
 flash: FORCE
 	@echo Flashing not supported with this board.
 	@echo Please check the documentation for alternate instructions.
+endif
 
+ifneq ($(DEBUG_SCRIPT),)
+debug: zephyr
+	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/support/$(DEBUG_SCRIPT) debug
+
+else
 debug: FORCE
 	@echo Debugging not supported with this board.
 	@echo Please check the documentation for alternate instructions.

Makefile.inc

@@ -1,13 +1,37 @@
 # vim: filetype=make
 #
 
+UNAME := $(shell uname)
+ifeq (MINGW, $(findstring MINGW, $(UNAME)))
+DQUOTE = '
+# '
+PROJECT_BASE ?= $(shell sh -c "pwd -W")
+else
 DQUOTE = "
 # "
-
-ARCH ?= x86
-
 PROJECT_BASE ?= $(CURDIR)
-O ?= $(PROJECT_BASE)/outdir
+endif
+
+ifdef BOARD
+KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/*/$(BOARD)_defconfig)
+ifeq ($(KBUILD_DEFCONFIG_PATH),)
+$(error Board $(BOARD) not found!)
+endif
+else
+$(error BOARD is not defined!)
+endif
+
+# Choose a default output directory if one wasn't supplied.  Note that
+# PRISTINE_O depends on whether this is default or not.  If building
+# in-tree, we want to remove the whole outdir and not just the BOARD
+# specified (thus "pristine").  Out of tree, we can obviously remove
+# only what we were told to build.
+ifndef O
+PRISTINE_O = outdir
+O = $(PROJECT_BASE)/outdir/$(BOARD)
+else
+PRISTINE_O = $(O)
+endif
 
 # Turn O into an absolute path; we call the main Kbuild with $(MAKE) -C
 # which changes the working directory, relative paths don't work right.
@@ -20,22 +44,15 @@ endif
 
 export ARCH MDEF_FILE QEMU_EXTRA_FLAGS PROJECT_BASE
 
-KERNEL_TYPE ?= micro
 override CONF_FILE := $(strip $(subst $(DQUOTE),,$(CONF_FILE)))
 
-ifdef BOARD
-KBUILD_DEFCONFIG_PATH=$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD)_defconfig)
-export KBUILD_DEFCONFIG_PATH
-else
-$(error BOARD is not defined!)
-endif
-
 SOURCE_DIR ?= $(PROJECT_BASE)/src/
-# Kbuild doesn't work correctly if this is an absolute path
-# FIXME Do not depend on python
-override SOURCE_DIR := $(shell python -c "import os.path; print(\"%s\" % os.path.relpath(os.path.realpath('$(SOURCE_DIR)'), os.path.realpath('$(ZEPHYR_BASE)')))")/
+override SOURCE_DIR := $(realpath $(SOURCE_DIR))
 override SOURCE_DIR := $(subst \,/,$(SOURCE_DIR))
-export SOURCE_DIR
+override SOURCE_DIR_PARENT := $(patsubst %, %/.., $(SOURCE_DIR))
+override SOURCE_DIR_PARENT := $(abspath $(SOURCE_DIR_PARENT))
+override SOURCE_DIR_PARENT := $(subst \,/,$(SOURCE_DIR_PARENT))
+export SOURCE_DIR SOURCE_DIR_PARENT
 
 ifeq ("$(origin V)", "command line")
   KBUILD_VERBOSE = $(V)
@@ -52,39 +69,55 @@ else
   S = -s
 endif
 
-zephyrmake	= @+$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) CFLAGS=$(CFLAGS) \
-			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(SOURCE_DIR) $(2)
+export CFLAGS
+
+zephyrmake	= +$(MAKE) -C $(ZEPHYR_BASE)  O=$(1) \
+			PROJECT=$(PROJECT_BASE) SOURCE_DIR=$(DQUOTE)$(SOURCE_DIR)$(DQUOTE) $(2)
+
+BOARDCONFIG = $(O)/.board_$(BOARD)
 
 DOTCONFIG = $(O)/.config
 
 all: $(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
 
-ifeq ($(findstring qemu_,$(BOARD)),)
-qemu:
-	@echo "Emulation not available for this platform"
-else
-qemu: $(DOTCONFIG)
-	$(Q)$(call zephyrmake,$(O),$@)
-endif
-
 debug:	$(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
 
 flash: $(DOTCONFIG)
 	$(Q)$(call zephyrmake,$(O),$@)
 
+qemugdb: debugserver
+
+qemu: $(DOTCONFIG)
+	@echo This target is deprecated, use 'make run' instead
+	$(Q)$(call zephyrmake,$(O),$@)
+
+run: $(DOTCONFIG)
+	$(Q)$(call zephyrmake,$(O),$@)
+
 ifeq ($(MAKECMDGOALS),debugserver)
--include $(ZEPHYR_BASE)/boards/$(BOARD)/Makefile.board
+ARCH = $(notdir $(subst /$(BOARD),,$(wildcard $(ZEPHYR_BASE)/boards/*/$(BOARD))))
+-include $(ZEPHYR_BASE)/boards/$(ARCH)/$(BOARD)/Makefile.board
 -include $(ZEPHYR_BASE)/scripts/Makefile.toolchain.$(ZEPHYR_GCC_VARIANT)
 BOARD_NAME = $(BOARD)
 export BOARD_NAME
 endif
+
 debugserver: FORCE
-	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/support/$(FLASH_SCRIPT) debugserver
+	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/support/$(DEBUG_SCRIPT) debugserver
 
+initconfig outputexports: $(DOTCONFIG)
 
-initconfig: $(DOTCONFIG)
+$(BOARDCONFIG):
+	@rm -f $(O)/.board_*
+	@touch $@
+
+ram_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
+
+rom_report: initconfig
+	$(Q)$(call zephyrmake,$(O),$@)
 
 menuconfig: initconfig
 	$(Q)$(call zephyrmake,$(O),$@)
@@ -96,15 +129,16 @@ help:
 %:
 	$(Q)$(call zephyrmake,$(O),$@)
 
-KERNEL_CONFIG = $(ZEPHYR_BASE)/kernel/configs/$(KERNEL_TYPE).config
+OVERLAY_CONFIG += $(ZEPHYR_BASE)/kernel/configs/kernel.config
 
-$(DOTCONFIG): $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
+$(DOTCONFIG): $(BOARDCONFIG) $(KBUILD_DEFCONFIG_PATH) $(CONF_FILE)
 	$(Q)$(CONFIG_SHELL) $(ZEPHYR_BASE)/scripts/kconfig/merge_config.sh \
-		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(KERNEL_CONFIG) $(CONF_FILE)
+		-q -m -O $(O) $(KBUILD_DEFCONFIG_PATH) $(OVERLAY_CONFIG) $(CONF_FILE) \
+			      $(wildcard $(O)/*.conf)
 	$(Q)$(MAKE) $(S) -C $(ZEPHYR_BASE) O=$(O) PROJECT=$(PROJECT_BASE) oldnoconfig
 
 pristine:
-	$(Q)rm -rf $(O)
+	$(Q)rm -rf $(PRISTINE_O)
 
 PHONY += FORCE initconfig
 FORCE:

Makefile.test

@@ -0,0 +1,4 @@
+
+OVERLAY_CONFIG += $(ZEPHYR_BASE)/tests/include/test.config
+
+include ${ZEPHYR_BASE}/Makefile.inc

arch/Kconfig

@@ -3,18 +3,9 @@
 #
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2015 Intel Corporation
+# Copyright (c) 2016 Cadence Design Systems, Inc.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 
@@ -30,7 +21,17 @@ config ARM
 
 config X86
 	bool "x86 architecture"
-	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
+	select ATOMIC_OPERATIONS_BUILTIN
+
+config NIOS2
+	bool "Nios II Gen 2 architecture"
+	select ATOMIC_OPERATIONS_C
+
+config RISCV32
+	bool "RISCV32 architecture"
+
+config XTENSA
+	bool "Xtensa architecture"
 
 endchoice
 
@@ -40,19 +41,39 @@ endchoice
 #
 config SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	# Hidden
-        bool
-        default n
-        help
-        This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
-        configuration option.
+	bool
+	default n
+	help
+	This option signifies that the target supports the SYS_POWER_LOW_POWER_STATE
+	configuration option.
 
 config SYS_POWER_DEEP_SLEEP_SUPPORTED
 	# Hidden
-        bool
-        default n
-        help
-        This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
-        configuration option.
+	bool
+	default n
+	help
+	This option signifies that the target supports the SYS_POWER_DEEP_SLEEP
+	configuration option.
+
+config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
+	# Hidden
+	bool
+	default n
+	help
+	This option signifies that the target has options of bootloaders
+	that support context restore upon resume from deep sleep
+
+config SIMPLE_FATAL_ERROR_HANDLER
+	prompt "Simple system fatal error handler"
+	bool
+	default n
+	default y if !MULTITHREADING
+	help
+	Provides an implementation of _SysFatalErrorHandler() that hard hangs
+	instead of aborting the faulting thread, and does not print anything,
+	for footprint-concerned systems. Only enable this option if you do not
+	want debug capabilities in case of system fatal error.
+
 #
 # End hidden PM feature configs
 #
@@ -63,16 +84,84 @@ config ARCH
 	System architecture string.
 
 config SOC
-        string
-        help
-        This option holds the directory name used by the build system to locate
-        the correct linker file.
+	string
+	help
+	SoC name which can be found under arch/<arch>/soc/<soc name>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files for the SoC. This option will go away
+	once all SoCs are using family/series structure.
+
+config SOC_SERIES
+	string
+	help
+	SoC series name which can be found under arch/<arch>/soc/<family>/<series>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
+
+config SOC_FAMILY
+	string
+	help
+	SoC family name which can be found under arch/<arch>/soc/<family>.
+	This option holds the directory name used by the build system to locate
+	the correct linker and header files.
 
 config BOARD
 	string
 	help
 	This option holds the name of the board and is used to located the files
-	related to the board in the source tree.
+	related to the board in the source tree (under boards/).
+	The Board is the first location where we search for a linker.ld file,
+	if not found we look for the linker file in
+	arch/<arch>/soc/<family>/<series>
+
+#
+# Interrupt related configs
+#
+
+config GEN_ISR_TABLES
+	bool
+	prompt "Use generated IRQ tables"
+	default n
+	help
+	This option controls whether a platform uses the gen_isr_tables
+	script to generate its interrupt tables. This mechanism will create
+	an appropriate hardware vector table and/or software IRQ table.
+
+config GEN_IRQ_VECTOR_TABLE
+	bool
+	prompt "Generate an interrupt vector table"
+	default y
+	depends on GEN_ISR_TABLES
+	help
+	This option controls whether a platform using gen_isr_tables
+	needs an interrupt vector table created. Only disable this if the
+	platform does not use a vector table at all, or requires the vector
+	table to be in a format that is not an array of function pointers
+	indexed by IRQ line. In the latter case, the vector table must be
+	supplied by the application or architecture code.
+
+config GEN_SW_ISR_TABLE
+	bool
+	prompt "Generate a software ISR table"
+	default y
+	depends on GEN_ISR_TABLES
+	help
+	This option controls whether a platform using gen_isr_tables
+	needs a software ISR table table created. This is an array of struct
+	_isr_table_entry containing the interrupt service routine and supplied
+	parameter.
+
+config GEN_IRQ_START_VECTOR
+	int
+	default 0
+	depends on GEN_ISR_TABLES
+	help
+	On some architectures, part of the vector table may be reserved for
+	system exceptions and is declared separately from the tables
+	created by gen_isr_tables.py. When creating these tables, this value
+	will be subtracted from CONFIG_NUM_IRQS to properly size them.
+	This is a hidden option which needs to be set-per architecture and
+	left alone.
 
 source "arch/*/Kconfig"
 

arch/Makefile

@@ -1,9 +1 @@
-ifeq (${ARCH},arm)
-obj-y += arm/
-endif
-ifeq (${ARCH},x86)
-obj-y += x86/
-endif
-ifeq (${ARCH},arc)
-obj-y += arc/
-endif
+obj-y += common/ $(ARCH)/

arch/arc/Kbuild

@@ -2,5 +2,5 @@ subdir-ccflags-y +=-I$(srctree)/include/drivers
 subdir-ccflags-y +=-I$(srctree)/drivers
 subdir-asflags-y += $(subdir-ccflags-y)
 
-obj-y += soc/$(SOC_NAME)/
+obj-y += soc/$(SOC_PATH)/
 obj-y += core/

arch/arc/Kconfig

@@ -3,17 +3,7 @@
 #
 # Copyright (c) 2014 Wind River Systems, Inc.
 #
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
 #
 
 choice
@@ -40,6 +30,7 @@ config	CPU_ARCEM4
 	bool
 	default y
 	select CPU_ARCV2
+	select ATOMIC_OPERATIONS_C
 	help
 	This option signifies the use of an ARC EM4 CPU
 
@@ -50,18 +41,9 @@ menu "ARCv2 Family Options"
 config	CPU_ARCV2
 	bool
 	default y
-	select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config RAM_START
-	prompt "RAM start address"
-	hex
-
-config RAM_SIZE
-	prompt "RAM size (in kB)"
-	int
-
 config NSIM
 	prompt "Running on the MetaWare nSIM simulator"
 	bool
@@ -72,8 +54,6 @@ config NSIM
 	  a) Uses non-XIP to run in RAM.
 	  b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
 	     a pc_size of 16 (default).
-	  c) Sets the entry point to __reset, since it seems nSIM ignores the
-	     reset vector when starting (??).
 
 config	DATA_ENDIANNESS_LITTLE
 	bool
@@ -93,22 +73,6 @@ config	NUM_IRQ_PRIO_LEVELS
 
 	  The BSP must provide a valid default for proper operation.
 
-config	NUM_REGULAR_IRQ_PRIO_LEVELS
-	int
-	prompt "Number of supported regular interrupt priority levels"
-	range 1 16
-	help
-	 This represents the number of Regular Interrupt priorities, which
-	 does NOT include the Fast (FIRQ) priority.
-	 The Regular Interrupt priorities available will be
-
-	  (NUM_IRQ_PRIO_LEVELS - NUM_REGULAR_IRQ_PRIO_LEVELS) to
-	  (NUM_REGULAR_IRQ_PRIO_LEVELS - 1).
-
-	  The maximum value is NUM_IRQ_PRIO_LEVELS.
-
-	  The BSP must provide a valid default for proper operation.
-
 config	NUM_IRQS
 	int
 	prompt "Upper limit of interrupt numbers/IDs used"
@@ -121,6 +85,20 @@ config	NUM_IRQS
 	  The BSP must provide a valid default. This drives the size of the
 	  vector table.
 
+config	RGF_NUM_BANKS
+	int
+	prompt "Number of General Purpose Register Banks"
+	depends on CPU_ARCV2
+	range 1 2
+	default 2
+	help
+	The ARC CPU can be configured to have more than one register
+	bank. If fast interrupts are supported (FIRQ), the 2nd
+	register bank, in the set, will be used by FIRQ interrupts.
+	If fast interrupts are supported but there is only 1
+	register bank, the fast interrupt handler must save
+	and restore general purpose regsiters.
+
 config	FIRQ_STACK_SIZE
 	int
 	prompt "Size of stack for FIRQs (in bytes)"
@@ -144,13 +122,15 @@ config	FAULT_DUMP
 	default 2
 	range 0 2
 	help
-	  Different levels for display information when a fault occurs.
+	Different levels for display information when a fault occurs.
 
-	  2: The default. Display specific and verbose information. Consumes
-	     the most memory (long strings).
-	  1: Display general and short information. Consumes less memory
-	     (short strings).
-	  0: Off.
+	2: The default. Display specific and verbose information. Consumes
+		the most memory (long strings).
+
+	1: Display general and short information. Consumes less memory
+		(short strings).
+
+	0: Off.
 
 config IRQ_OFFLOAD
 	bool "Enable IRQ offload"
@@ -164,98 +144,113 @@ config	XIP
 	default n if NSIM
 	default y
 
-config NSIM
-	prompt "Running on the MetaWare nSIM simulator"
-	bool
-	default n
-	help
-	For running on nSIM simulator.
-
-	a) Uses non-XIP to run in RAM.
-	b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
-	   a pc_size of 16 (default).
-	c) Sets the entry point to __reset, since it seems nSIM ignores the
-	   reset vector when starting.
-
-config  SW_ISR_TABLE
-	bool
-	prompt "Enable software interrupt handler table"
+config GEN_ISR_TABLES
 	default y
-	help
-	  Enable an interrupt handler table implemented in software. This
-	  table, unlike ISRs connected directly in the vector table, allow
-	  a parameter to be passed to the interrupt handlers. Also, invoking
-	  the exeception/interrupt exit stub is automatically done.
 
-	  This has to be enabled for dynamically connecting interrupt handlers
-	  at runtime (SW_ISR_TABLE_DYNAMIC).
+config GEN_IRQ_START_VECTOR
+	default 16
 
-config  SW_ISR_TABLE_DYNAMIC
-	bool
-	prompt "Allow installing interrupt handlers at runtime"
-	depends on SW_ISR_TABLE
-	default n
-	help
-	  This option enables irq_connect_dynamic(). It moves the ISR table to
-	  SRAM so that it is writable. This has the side-effect of removing
-	  write-protection on the ISR table.
-
-config  IRQ_VECTOR_TABLE_CUSTOM
-	bool
-	prompt "Projects provide a custom static IRQ part of vector table"
-	depends on !SW_ISR_TABLE
-	default n
-	help
-	  Projects, not the BSP, provide the IRQ part of the vector table.
-
-	  This is the table of interrupt handlers with the best potential
-	  performance, but is the less flexible.
-
-	  The ISRs are installed directly in the vector table, thus are
-	  directly called by the CPU when an interrupt is taken. This adds
-	  the least overhead when handling an interrupt.
-
-	  Downsides:
-
-	  - ISRs cannot have a parameter
-	  - ISRs cannot be connected at runtime
-	  - ISRs must notify the kernel manually by invoking _ExcExit() when
-	    then are about to return.
-
-config	IRQ_VECTOR_TABLE_BSP
-	bool
-	# omit prompt to signify a "hidden" option
-	depends on SW_ISR_TABLE || !IRQ_VECTOR_TABLE_CUSTOM
-	default y
-	help
-	  Not user-selectable, helps build system logic.
-
-config  ARCH_HAS_TASK_ABORT
-	bool
-	# omit prompt to signify a "hidden" option
-	default n
-
-config  ARCH_HAS_NANO_FIBER_ABORT
-	bool
-	# omit prompt to signify a "hidden" option
-	default n
-
-config  ARC_ATOMIC_ASM
+config HARVARD
+	prompt "Harvard Architecture"
 	bool
 	default n
-	depends on !CPU_ARCEM4
 	help
-	  Say y if the processor supports atomic assembly instructions:
-	  LLOCK and SCOND.
+	  The ARC CPU can be configured to have two busses;
+	  one for instruction fetching and another that serves as a data bus.
 
-	  Say n if not sure.
+config ICCM_SIZE
+	int "ICCM Size in kB"
+	help
+	This option specifies the size of the ICCM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
 
-	  Note that these instructions are not supported on ARC EM family
-	  processors.
+config ICCM_BASE_ADDRESS
+	hex "ICCM Base Address"
+	help
+	This option specifies the base address of the ICCM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config DCCM_SIZE
+	int "DCCM Size in kB"
+	help
+	This option specifies the size of the DCCM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config DCCM_BASE_ADDRESS
+	hex "DCCM Base Address"
+	help
+	This option specifies the base address of the DCCM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config SRAM_SIZE
+	int "SRAM Size in kB"
+	help
+	This option specifies the size of the SRAM in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config SRAM_BASE_ADDRESS
+	hex "SRAM Base Address"
+	help
+	This option specifies the base address of the SRAM on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config FLASH_SIZE
+	int "Flash Size in kB"
+	help
+	This option specifies the size of the flash in kB.  It is normally set by
+	the board's defconfig file and the user should generally avoid modifying
+	it via the menu configuration.
+
+config FLASH_BASE_ADDRESS
+	hex "Flash Base Address"
+	help
+	This option specifies the base address of the flash on the board.  It is
+	normally set by the board's defconfig file and the user should generally
+	avoid modifying it via the menu configuration.
+
+config CACHE_LINE_SIZE_DETECT
+	bool
+	prompt "Detect d-cache line size at runtime"
+	default n
+	help
+	This option enables querying the d-cache build register for finding
+	the d-cache line size at the expense of taking more memory and code
+	and a slightly increased boot time.
+
+	If the CPU's d-cache line size is known in advance, disable this
+	option and manually enter the value for CACHE_LINE_SIZE.
+
+config CACHE_LINE_SIZE
+	int
+	prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
+	default 32
+	help
+	Size in bytes of a CPU d-cache line.
+
+	Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
+
+config ARCH_CACHE_FLUSH_DETECT
+	bool
+	default n
+
+config CACHE_FLUSHING
+	bool
+	default n
+	prompt "Enable d-cache flushing mechanism"
+	help
+	This links in the sys_cache_flush() function, which provides a
+	way to flush multiple lines of the d-cache.
+	If the d-cache is present, set this to y.
+	If the d-cache is NOT present, set this to n.
 
 endmenu
 
-
 source "arch/arc/soc/*/Kconfig"
 
 endmenu

arch/arc/Makefile

@@ -1,9 +1,21 @@
 cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
+
+# Without this (poorly named) option, compiler may generate undefined
+# references to abort().
+# See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63691
+cflags-y += $(call cc-option,-fno-delete-null-pointer-checks)
+
 cflags-$(CONFIG_ARC_STACK_CHECKING) = $(call cc-option,-fomit-frame-pointer)
 cflags-$(CONFIG_LTO) = $(call cc-option,-flto,)
 
-include $(srctree)/arch/$(ARCH)/soc/$(SOC_NAME)/Makefile
+include $(srctree)/arch/$(ARCH)/soc/$(SOC_PATH)/Makefile
 
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_CXXFLAGS += $(cflags-y)
 
+soc-cxxflags ?= $(soc-cflags)
+soc-aflags ?= $(soc-cflags)
+KBUILD_CFLAGS += $(soc-cflags)
+KBUILD_CXXFLAGS += $(soc-cxxflags)
+KBUILD_AFLAGS += $(soc-aflags)
+

arch/arc/core/Makefile

@@ -1,11 +1,10 @@
-ccflags-y += -I$(srctree)/kernel/nanokernel/include
+ccflags-y += -I$(srctree)/kernel/include
 ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
-ccflags-y += -I$(srctree)/kernel/microkernel/include
 
 obj-y += thread.o thread_entry_wrapper.o \
 	cpu_idle.o  fast_irq.o  fatal.o  fault.o  \
-	fault_s.o  irq_manage.o  \
-	isr_wrapper.o  regular_irq.o  swap_macros.h  swap.o \
+	fault_s.o  irq_manage.o cache.o timestamp.o  \
+	isr_wrapper.o  regular_irq.o  swap.o \
 	sys_fatal_error_handler.o
 
 obj-y += prep_c.o \
@@ -13,13 +12,7 @@ obj-y += prep_c.o \
          vector_table.o
 
 obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
-obj-$(CONFIG_ERRNO) += errno.o
 
-ifeq ($(CONFIG_ARC_ATOMIC_ASM),y)
-obj-y += atomic.o
-else
-obj-y += atomic_native.o
-endif
-
-obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
-obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o
+# Some ARC cores like the EM4 lack the atomic LLOCK/SCOND and
+# can't use these.
+obj-$(CONFIG_ATOMIC_OPERATIONS_CUSTOM) += atomic.o

arch/arc/core/atomic.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -26,8 +16,6 @@
  * where they are not supported on ARC EM family processors.
  */
 
-#define _ASMLANGUAGE
-
 #include <toolchain.h>
 #include <sections.h>
 

arch/arc/core/atomic_native.c

@@ -1,362 +0,0 @@
-/*
- * Copyright (c) 2016 Intel Corporation
- * Copyright (c) 2011-2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file Atomic ops for ARC EM
- *
- * This module provides the atomic operators for ARC EM family processors
- * which do not support native atomic operations.
- *
- * The atomic operations are guaranteed to be atomic with respect
- * to interrupt service routines, and to operations performed by peer
- * processors.
- *
- * (originally from x86's atomic.c)
- */
-
-#include <atomic.h>
-#include <toolchain.h>
-#include <arch/arc/v2/irq.h>
-
-/**
- *
- * @brief Atomic compare-and-set primitive
- *
- * This routine provides the compare-and-set operator. If the original value at
- * <target> equals <oldValue>, then <newValue> is stored at <target> and the
- * function returns 1.
- *
- * If the original value at <target> does not equal <oldValue>, then the store
- * is not done and the function returns 0.
- *
- * The reading of the original value at <target>, the comparison,
- * and the write of the new value (if it occurs) all happen atomically with
- * respect to both interrupts and accesses of other processors to <target>.
- *
- * @param target address to be tested
- * @param old_value value to compare against
- * @param new_value value to compare against
- * @return Returns 1 if <new_value> is written, 0 otherwise.
- */
-FUNC_NO_FP int atomic_cas(atomic_t *target, atomic_val_t old_value,
-			  atomic_val_t new_value)
-{
-	unsigned int key;
-	int ret = 0;
-
-	key = irq_lock();
-
-	if (*target == old_value) {
-		*target = new_value;
-		ret = 1;
-	}
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic addition primitive
- *
- * This routine provides the atomic addition operator. The <value> is
- * atomically added to the value at <target>, placing the result at <target>,
- * and the old value from <target> is returned.
- *
- * @param target memory location to add to
- * @param value the value to add
- *
- * @return The previous value from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_add(atomic_t *target, atomic_val_t value)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	*target += value;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic subtraction primitive
- *
- * This routine provides the atomic subtraction operator. The <value> is
- * atomically subtracted from the value at <target>, placing the result at
- * <target>, and the old value from <target> is returned.
- *
- * @param target the memory location to subtract from
- * @param value the value to subtract
- *
- * @return The previous value from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_sub(atomic_t *target, atomic_val_t value)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	*target -= value;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic increment primitive
- *
- * @param target memory location to increment
- *
- * This routine provides the atomic increment operator. The value at <target>
- * is atomically incremented by 1, and the old value from <target> is returned.
- *
- * @return The value from <target> before the increment
- */
-FUNC_NO_FP atomic_val_t atomic_inc(atomic_t *target)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	(*target)++;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic decrement primitive
- *
- * @param target memory location to decrement
- *
- * This routine provides the atomic decrement operator. The value at <target>
- * is atomically decremented by 1, and the old value from <target> is returned.
- *
- * @return The value from <target> prior to the decrement
- */
-FUNC_NO_FP atomic_val_t atomic_dec(atomic_t *target)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	(*target)--;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic get primitive
- *
- * @param target memory location to read from
- *
- * This routine provides the atomic get primitive to atomically read
- * a value from <target>. It simply does an ordinary load.  Note that <target>
- * is expected to be aligned to a 4-byte boundary.
- *
- * @return The value read from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_get(const atomic_t *target)
-{
-	return *target;
-}
-
-/**
- *
- * @brief Atomic get-and-set primitive
- *
- * This routine provides the atomic set operator. The <value> is atomically
- * written at <target> and the previous value at <target> is returned.
- *
- * @param target the memory location to write to
- * @param value the value to write
- *
- * @return The previous value from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_set(atomic_t *target, atomic_val_t value)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	*target = value;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic clear primitive
- *
- * This routine provides the atomic clear operator. The value of 0 is atomically
- * written at <target> and the previous value at <target> is returned. (Hence,
- * atomic_clear(pAtomicVar) is equivalent to atomic_set(pAtomicVar, 0).)
- *
- * @param target the memory location to write
- *
- * @return The previous value from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_clear(atomic_t *target)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	*target = 0;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic bitwise inclusive OR primitive
- *
- * This routine provides the atomic bitwise inclusive OR operator. The <value>
- * is atomically bitwise OR'ed with the value at <target>, placing the result
- * at <target>, and the previous value at <target> is returned.
- *
- * @param target the memory location to be modified
- * @param value the value to OR
- *
- * @return The previous value from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_or(atomic_t *target, atomic_val_t value)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	*target |= value;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic bitwise exclusive OR (XOR) primitive
- *
- * This routine provides the atomic bitwise exclusive OR operator. The <value>
- * is atomically bitwise XOR'ed with the value at <target>, placing the result
- * at <target>, and the previous value at <target> is returned.
- *
- * @param target the memory location to be modified
- * @param value the value to XOR
- *
- * @return The previous value from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_xor(atomic_t *target, atomic_val_t value)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	*target ^= value;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic bitwise AND primitive
- *
- * This routine provides the atomic bitwise AND operator. The <value> is
- * atomically bitwise AND'ed with the value at <target>, placing the result
- * at <target>, and the previous value at <target> is returned.
- *
- * @param target the memory location to be modified
- * @param value the value to AND
- *
- * @return The previous value from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_and(atomic_t *target, atomic_val_t value)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	*target &= value;
-
-	irq_unlock(key);
-
-	return ret;
-}
-
-/**
- *
- * @brief Atomic bitwise NAND primitive
- *
- * This routine provides the atomic bitwise NAND operator. The <value> is
- * atomically bitwise NAND'ed with the value at <target>, placing the result
- * at <target>, and the previous value at <target> is returned.
- *
- * @param target the memory location to be modified
- * @param value the value to NAND
- *
- * @return The previous value from <target>
- */
-FUNC_NO_FP atomic_val_t atomic_nand(atomic_t *target, atomic_val_t value)
-{
-	unsigned int key;
-	atomic_val_t ret;
-
-	key = irq_lock();
-
-	ret = *target;
-	*target = ~(*target & value);
-
-	irq_unlock(key);
-
-	return ret;
-}

arch/arc/core/cache.c

@@ -0,0 +1,174 @@
+/* cache.c - d-cache support for ARC CPUs */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief d-cache manipulation
+ *
+ * This module contains functions for manipulation of the d-cache.
+ */
+
+#include <kernel.h>
+#include <arch/cpu.h>
+#include <misc/util.h>
+#include <toolchain.h>
+#include <cache.h>
+#include <linker-defs.h>
+#include <arch/arc/v2/aux_regs.h>
+#include <nano_internal.h>
+#include <misc/__assert.h>
+#include <init.h>
+
+#if defined(CONFIG_CACHE_FLUSHING)
+
+#if (CONFIG_CACHE_LINE_SIZE == 0) && !defined(CONFIG_CACHE_LINE_SIZE_DETECT)
+#error Cannot use this implementation with a cache line size of 0
+#endif
+
+#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
+#define DCACHE_LINE_SIZE sys_cache_line_size
+#else
+#define DCACHE_LINE_SIZE CONFIG_CACHE_LINE_SIZE
+#endif
+
+#define DC_CTRL_DC_ENABLE            0x0  /* enable d-cache */
+#define DC_CTRL_DC_DISABLE           0x1  /* disable d-cache */
+#define DC_CTRL_INVALID_ONLY         0x0  /* invalid d-cache only */
+#define DC_CTRL_INVALID_FLUSH        0x40 /* invalid and flush d-cache */
+#define DC_CTRL_ENABLE_FLUSH_LOCKED  0x80 /* locked d-cache can be flushed */
+#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0  /* locked d-cache cannot be flushed */
+#define DC_CTRL_FLUSH_STATUS         0x100/* flush status */
+#define DC_CTRL_DIRECT_ACCESS        0x0  /* direct access mode  */
+#define DC_CTRL_INDIRECT_ACCESS      0x20 /* indirect access mode */
+#define DC_CTRL_OP_SUCCEEDED         0x4  /* d-cache operation succeeded */
+
+
+static int dcache_available(void)
+{
+	unsigned long val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+
+	val &= 0xff; /* extract version */
+	return (val == 0)?0:1;
+}
+
+static void dcache_dc_ctrl(uint32_t dcache_en_mask)
+{
+	if (!dcache_available())
+		return;
+	_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, dcache_en_mask);
+}
+
+static void dcache_enable(void)
+{
+	dcache_dc_ctrl(DC_CTRL_DC_ENABLE);
+}
+
+
+/**
+ *
+ * @brief Flush multiple d-cache lines to memory
+ *
+ * No alignment is required for either <start_addr> or <size>, but since
+ * dcache_flush_mlines() iterates on the d-cache lines, a cache line
+ * alignment for both is optimal.
+ *
+ * The d-cache line size is specified either via the CONFIG_CACHE_LINE_SIZE
+ * kconfig option or it is detected at runtime.
+ *
+ * @param start_addr the pointer to start the multi-line flush
+ * @param size the number of bytes that are to be flushed
+ *
+ * @return N/A
+ */
+static void dcache_flush_mlines(uint32_t start_addr, uint32_t size)
+{
+	uint32_t end_addr;
+	unsigned int key;
+
+	if (!dcache_available() || (size == 0)) {
+		return;
+	}
+
+	end_addr = start_addr + size - 1;
+	start_addr &= (uint32_t)(~(DCACHE_LINE_SIZE - 1));
+
+	key = irq_lock(); /* --enter critical section-- */
+
+	do {
+		_arc_v2_aux_reg_write(_ARC_V2_DC_FLDL, start_addr);
+		__asm__ volatile("nop_s");
+		__asm__ volatile("nop_s");
+		__asm__ volatile("nop_s");
+		/* wait for flush completion */
+		do {
+			if ((_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) &
+				DC_CTRL_FLUSH_STATUS) == 0)
+				break;
+		} while (1);
+		start_addr += DCACHE_LINE_SIZE;
+	} while (start_addr <= end_addr);
+
+	irq_unlock(key); /* --exit critical section-- */
+
+}
+
+
+/**
+ *
+ * @brief Flush d-cache lines to main memory
+ *
+ * No alignment is required for either <virt> or <size>, but since
+ * sys_cache_flush() iterates on the d-cache lines, a d-cache line alignment for
+ * both is optimal.
+ *
+ * The d-cache line size is specified either via the CONFIG_CACHE_LINE_SIZE
+ * kconfig option or it is detected at runtime.
+ *
+ * @param start_addr the pointer to start the multi-line flush
+ * @param size the number of bytes that are to be flushed
+ *
+ * @return N/A
+ */
+
+void sys_cache_flush(vaddr_t start_addr, size_t size)
+{
+	dcache_flush_mlines((uint32_t)start_addr, (uint32_t)size);
+}
+
+
+#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
+size_t sys_cache_line_size;
+static void init_dcache_line_size(void)
+{
+	uint32_t val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	__ASSERT((val&0xff) != 0, "d-cache is not present");
+	val = ((val>>16) & 0xf) + 1;
+	val *= 16;
+	sys_cache_line_size = (size_t) val;
+}
+#endif
+
+static int init_dcache(struct device *unused)
+{
+	ARG_UNUSED(unused);
+
+	dcache_enable();
+
+#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
+	init_dcache_line_size();
+#endif
+
+	return 0;
+}
+
+SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_CACHE_FLUSHING */
+

arch/arc/core/cpu_idle.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,36 +11,20 @@
  * CPU power management routines.
  */
 
-#define _ASMLANGUAGE
-
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <sections.h>
 #include <arch/cpu.h>
 
-GTEXT(nano_cpu_idle)
-GTEXT(nano_cpu_atomic_idle)
-GDATA(nano_cpu_sleep_mode)
+GTEXT(k_cpu_idle)
+GTEXT(k_cpu_atomic_idle)
+GDATA(k_cpu_sleep_mode)
 
-#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
-	GTEXT(_power_save_idle)
-#endif
-
-SECTION_VAR(BSS, nano_cpu_sleep_mode)
+	.balign 4
+SECTION_VAR(BSS, k_cpu_sleep_mode)
 	.word 0
 
-#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
-.macro enter_tickless_idle
-	/* interrupts are locked when entering here */
-	push_s blink
-	jl _power_save_idle
-	pop_s blink
-.endm
-#else
-	#define enter_tickless_idle
-#endif
-
 /*
  * @brief Put the CPU in low-power mode
  *
@@ -59,14 +33,18 @@ SECTION_VAR(BSS, nano_cpu_sleep_mode)
  * void nanCpuIdle(void)
  */
 
-SECTION_FUNC(TEXT, nano_cpu_idle)
+SECTION_FUNC(TEXT, k_cpu_idle)
 
-	enter_tickless_idle
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+	push_s blink
+	jl    _sys_k_event_logger_enter_sleep
+	pop_s blink
+#endif
 
-	ld r1, [nano_cpu_sleep_mode]
+	ld r1, [k_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
-	j_s.nd [blink]
+	j_s [blink]
 	nop
 
 /*
@@ -74,13 +52,17 @@ SECTION_FUNC(TEXT, nano_cpu_idle)
  *
  * This function exits with interrupts restored to <key>.
  *
- * void nano_cpu_atomic_idle(unsigned int key)
+ * void k_cpu_atomic_idle(unsigned int key)
  */
-SECTION_FUNC(TEXT, nano_cpu_atomic_idle)
+SECTION_FUNC(TEXT, k_cpu_atomic_idle)
 
-	enter_tickless_idle
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+	push_s blink
+	jl    _sys_k_event_logger_enter_sleep
+	pop_s blink
+#endif
 
-	ld r1, [nano_cpu_sleep_mode]
+	ld r1, [k_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
 	j_s.d [blink]

arch/arc/core/errno.S

@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2015 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/** @file
- *
- * @brief Per-thread errno accessor function
- *
- * Allow accessing the errno for the current thread without involving the
- * context switching.
- */
-
-#define _ASMLANGUAGE
-
-#include <nano_private.h>
-#include <offsets.h>
-
-GTEXT(_nanokernel)
-GTEXT(_get_errno)
-
-SECTION_FUNC(TEXT, _get_errno)
-
-	mov_s r0, _nanokernel
-	ld_s r0, [r0, __tNANO_current_OFFSET]
-	add_s r0, r0, __tTCS_errno_var_OFFSET
-	j_s.nd [blink]
-	nop_s

arch/arc/core/fast_irq.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -23,21 +13,35 @@
  * See isr_wrapper.S for details.
  */
 
-#define _ASMLANGUAGE
-
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
-#include "swap_macros.h"
+#include <swap_macros.h>
 
 GTEXT(_firq_enter)
 GTEXT(_firq_exit)
 GTEXT(_firq_stack_setup)
+GTEXT(_firq_stack_suspend)
+GTEXT(_firq_stack_resume)
+
+#if CONFIG_RGF_NUM_BANKS != 1
 GDATA(_firq_stack)
+GDATA(_saved_firq_stack)
 
 SECTION_VAR(NOINIT, _firq_stack)
 	.space CONFIG_FIRQ_STACK_SIZE
+#else
+GDATA(saved_r0)
+#endif
+
+.macro _firq_return
+#if CONFIG_RGF_NUM_BANKS == 1
+	b _firq_no_reschedule
+#else
+	rtie
+#endif
+.endm
 
 /**
  *
@@ -45,14 +49,16 @@ SECTION_VAR(NOINIT, _firq_stack)
  *
  * The processor switches to a second register bank so registers from the
  * current bank do not have to be preserved yet. The only issue is the LP_START/
- * LP_COUNT/LP_END registers, which are not banked.
+ * LP_COUNT/LP_END registers, which are not banked. These can be saved
+ * in available callee saved registers.
  *
  * If all FIRQ ISRs are programmed such that there are no use of the LP
  * registers (ie. no LPcc instruction), and CONFIG_ARC_STACK_CHECKING is
- * not set, then the kernel can be configured to remove the use of _firq_enter().
+ * not set, then the kernel can be configured to not save and restore them.
  *
  * When entering a FIRQ, interrupts might as well be locked: the processor is
- * running at its highest priority, and cannot be preempted by anything.
+ * running at its highest priority, and cannot be interrupted by any other
+ * interrupt. An exception, however, can be taken.
  *
  * Assumption by _isr_demux: r3 is untouched by _firq_enter.
  *
@@ -61,6 +67,14 @@ SECTION_VAR(NOINIT, _firq_stack)
 
 SECTION_FUNC(TEXT, _firq_enter)
 
+/*
+ * ATTENTION:
+ * If CONFIG_RGF_NUM_BANKS>1, firq uses a 2nd register bank so GPRs do
+ * not need to be saved.
+ * If CONFIG_RGF_NUM_BANKS==1, firq must use the stack to save registers.
+ * This has already been done by _isr_wrapper.
+ */
+
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
@@ -68,22 +82,17 @@ SECTION_FUNC(TEXT, _firq_enter)
 	kflag r2
 #endif
 
+#if CONFIG_RGF_NUM_BANKS != 1
 #ifndef CONFIG_FIRQ_NO_LPCC
 	/*
-	 * Unlike the rest of context switching code, r2 is loaded with something
-	 * else than 'current' in this routine: this is to preserve r3 so that it
-	 * does not have to be fetched again in _isr_demux.
+	 * Save LP_START/LP_COUNT/LP_END because called handler might use.
+	 * Save these in callee saved registers to avoid using memory.
+	 * These will be saved by the compiler if it needs to spill them.
 	 */
-
-	/* save LP_START/LP_COUNT/LP_END variables */
-	mov_s r1, _nanokernel
-
-	st lp_count, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
-
-	lr r2, [_ARC_V2_LP_START]
-	st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
-	lr r2, [_ARC_V2_LP_END]
-	st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
+	mov r23,lp_count
+	lr r24, [_ARC_V2_LP_START]
+	lr r25, [_ARC_V2_LP_END]
+#endif
 #endif
 
 	j @_isr_demux
@@ -97,30 +106,22 @@ SECTION_FUNC(TEXT, _firq_enter)
 
 SECTION_FUNC(TEXT, _firq_exit)
 
-	mov_s r1, _nanokernel
-	ld_s r2, [r1, __tNANO_current_OFFSET]
-
+#if CONFIG_RGF_NUM_BANKS != 1
 #ifndef CONFIG_FIRQ_NO_LPCC
-
-	/* assumption: r1 contains _nanokernel, r2 contains the current thread */
-
-	/* restore LP_START/LP_COUNT/LP_END variables */
-
-	/* cannot load lp_count from memory */
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
-	mov lp_count, r3
-
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
-	sr r3, [_ARC_V2_LP_START]
-	ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
-	sr r3, [_ARC_V2_LP_END]
-
-	/* exiting here: r1/r2 unchanged, r0/r3 destroyed */
+	/* restore lp_count, lp_start, lp_end from r23-r25 */
+	mov lp_count,r23
+	sr r24, [_ARC_V2_LP_START]
+	sr r25, [_ARC_V2_LP_END]
+#endif
 #endif
 
+#ifdef CONFIG_PREEMPT_ENABLED
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
 #if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
-	/* check if we're a nested interrupt: if so, let the interrupted interrupt
-	 * handle the reschedule */
+	/* check if we're a nested interrupt: if so, let the interrupted
+	 * interrupt handle the reschedule */
 
 	lr r3, [_ARC_V2_AUX_IRQ_ACT]
 
@@ -129,29 +130,67 @@ SECTION_FUNC(TEXT, _firq_exit)
 	 * means that another bit is set so an interrupt was interrupted.
 	 */
 
-	breq.nd r3, 1, _check_if_current_is_the_task
-
-	rtie
+	breq r3, 1, _firq_check_for_swap
 
+	_firq_return
 #endif
 
 .balign 4
-_check_if_current_is_the_task:
+_firq_check_for_swap:
+	/*
+	 * Non-preemptible thread ? Do not schedule (see explanation of
+	 * preempt field in kernel_struct.h).
+	 */
+	ldh_s r0, [r2, _thread_offset_to_preempt]
+	brhs r0, _NON_PREEMPT_THRESHOLD, _firq_no_reschedule
 
-	ld r0, [r2, __tTCS_flags_OFFSET]
-	and.f r0, r0, PREEMPTIBLE
-	bnz.nd _check_if_a_fiber_is_ready
-	rtie
+	/* Check if the current thread (in r2) is the cached thread */
+	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
+	brne r0, r2, _firq_reschedule
+
+	/* fall to no rescheduling */
+
+#endif /* CONFIG_PREEMPT_ENABLED */
 
 .balign 4
-_check_if_a_fiber_is_ready:
-	ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
-	brne.nd r0, 0, _firq_reschedule
+_firq_no_reschedule:
+	/*
+	 * Keeping this code block close to those that use it allows using brxx
+	 * instruction instead of a pair of cmp and bxx
+	 */
+#if CONFIG_RGF_NUM_BANKS == 1
+	add sp,sp,4 /* don't need r0 from stack */
+	pop_s r1
+	pop_s r2
+	pop_s r3
+	pop r4
+	pop r5
+	pop r6
+	pop r7
+	pop r8
+	pop r9
+	pop r10
+	pop r11
+	pop_s r12
+	pop_s r13
+	pop_s blink
+	pop_s r0
+	sr r0, [_ARC_V2_LP_END]
+	pop_s r0
+	sr r0, [_ARC_V2_LP_START]
+	pop_s r0
+	mov lp_count,r0
+	ld r0,[saved_r0]
+	add sp,sp,8 /* don't need ilink & status32_po from stack */
+#endif
 	rtie
 
+#ifdef CONFIG_PREEMPT_ENABLED
+
 .balign 4
 _firq_reschedule:
 
+#if CONFIG_RGF_NUM_BANKS != 1
 	/*
 	 * We know there is no interrupted interrupt of lower priority at this
 	 * point, so when switching back to register bank 0, it will contain the
@@ -172,28 +211,26 @@ _firq_reschedule:
 	 */
 
 	lr r0, [_ARC_V2_STATUS32_P0]
-	st_s r0, [sp, __tISF_status32_OFFSET]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
 
-	st ilink, [sp, __tISF_pc_OFFSET] /* ilink into pc */
+	st ilink, [sp, ___isf_t_pc_OFFSET] /* ilink into pc */
+#endif
 
-	mov_s r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
 
 	_save_callee_saved_regs
 
-	st _CAUSE_FIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
+	st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
 
-	ld r2, [r1, __tNANO_fiber_OFFSET]
-
-	st r2, [r1, __tNANO_current_OFFSET]
-	ld r3, [r2, __tTCS_link_OFFSET]
-	st r3, [r1, __tNANO_fiber_OFFSET]
+	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
+	st_s r2, [r1, _kernel_offset_to_current]
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
-	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/*
@@ -202,11 +239,11 @@ _firq_reschedule:
 	 */
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
-	breq.nd r3, _CAUSE_RIRQ, _firq_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _firq_return_from_firq
+	breq r3, _CAUSE_FIRQ, _firq_return_from_firq
 	nop
 
 	/* fall through */
@@ -214,8 +251,8 @@ _firq_reschedule:
 .balign 4
 _firq_return_from_coop:
 
-	ld r3, [r2, __tTCS_intlock_key_OFFSET]
-	st  0, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
 
 	/* pc into ilink */
 	pop_s r0
@@ -225,15 +262,15 @@ _firq_return_from_coop:
 	/*
 	 * There are only two interrupt lock states: locked and unlocked. When
 	 * entering _Swap(), they are always locked, so the IE bit is unset in
-	 * status32. If the incoming thread had them locked recursively, it means
-	 * that the IE bit should stay unset. The only time the bit has to change
-	 * is if they were not locked recursively.
+	 * status32. If the incoming thread had them locked recursively, it
+	 * means that the IE bit should stay unset. The only time the bit
+	 * has to change is if they were not locked recursively.
 	 */
 	and.f r3, r3, (1 << 4)
 	or.nz r0, r0, _ARC_V2_STATUS32_IE
 	sr r0, [_ARC_V2_STATUS32_P0]
 
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, _thread_offset_to_return_value]
 	rtie
 
 .balign 4
@@ -246,23 +283,21 @@ _firq_return_from_firq:
 	sr ilink, [_ARC_V2_STATUS32_P0]
 	ld ilink, [sp, -8] /* pc into ilink */
 
-	/* fall through to rtie instruction */
-
-.balign 4
-_firq_no_reschedule:
-
 	/* LP registers are already restored, just switch back to bank 0 */
 	rtie
 
+#endif /* CONFIG_PREEMPT_ENABLED */
+
 /**
  *
- * @brief Install the FIRQ stack in register bank 1
+ * @brief Install the FIRQ stack in register bank 1 if CONFIG_RGF_NUM_BANK!=1
  *
  * @return N/A
  */
 
 SECTION_FUNC(TEXT, _firq_stack_setup)
 
+#if CONFIG_RGF_NUM_BANKS != 1
 	lr r0, [_ARC_V2_STATUS32]
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	or r0, r0, _ARC_V2_STATUS32_RB(1)
@@ -278,5 +313,58 @@ SECTION_FUNC(TEXT, _firq_stack_setup)
 	lr r0, [_ARC_V2_STATUS32]
 	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
 	kflag r0
+#endif
 
-	j_s.nd [blink]
+	j_s [blink]
+
+/**
+ *
+ * @brief Save the FIRQ context if CONFIG_RGF_NUM_BANK!=1
+ *
+ * @return N/A
+ */
+
+SECTION_FUNC(TEXT, _firq_stack_suspend)
+
+#if CONFIG_RGF_NUM_BANKS != 1
+	/* Switch to bank 1 */
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	or r0, r0, _ARC_V2_STATUS32_RB(1)
+	kflag r0
+
+	st sp, [_saved_firq_stack]
+
+	/* Switch back to bank 0 */
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	kflag r0
+#endif
+
+	j_s [blink]
+
+/**
+ *
+ * @brief Restore the FIRQ context if CONFIG_RGF_NUM_BANK!=1
+ *
+ * @return N/A
+ */
+
+SECTION_FUNC(TEXT, _firq_stack_resume)
+
+#if CONFIG_RGF_NUM_BANKS != 1
+	/* Switch to bank 1 */
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	or r0, r0, _ARC_V2_STATUS32_RB(1)
+	kflag r0
+
+	ld sp, [_saved_firq_stack]
+
+	/* Switch back to bank 0 */
+	lr r0, [_ARC_V2_STATUS32]
+	and r0, r0, ~_ARC_V2_STATUS32_RB(7)
+	kflag r0
+#endif
+
+	j_s [blink]

arch/arc/core/fatal.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -22,8 +12,8 @@
  * ARCv2 CPUs.
  */
 
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 
@@ -40,7 +30,7 @@ const NANO_ESF _default_esf = {
 
 /**
  *
- * @brief Nanokernel fatal error handler
+ * @brief Kernel fatal error handler
  *
  * This routine is called when fatal error conditions are detected by software
  * and is responsible only for reporting the error. Once reported, it then
@@ -75,9 +65,9 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 		PR_EXC("**** Unknown Fatal Error %d! ****\n", reason);
 		break;
 	}
-	PR_EXC("Current thread ID = 0x%x\n"
-	       "Faulting instruction address = 0x%x\n",
-	       sys_thread_self_get(),
+	PR_EXC("Current thread ID = %p\n"
+	       "Faulting instruction address = 0x%lx\n",
+	       k_current_get(),
 	       _arc_v2_aux_reg_read(_ARC_V2_ERET));
 
 	/*

arch/arc/core/fault.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -23,9 +13,10 @@
 
 #include <toolchain.h>
 #include <sections.h>
+#include <inttypes.h>
 
-#include <nanokernel.h>
-#include <nano_private.h>
+#include <kernel.h>
+#include <kernel_structs.h>
 
 #ifdef CONFIG_PRINTK
 #include <misc/printk.h>
@@ -56,15 +47,18 @@
 void _FaultDump(const NANO_ESF *esf, int fault)
 {
 	ARG_UNUSED(esf);
+	ARG_UNUSED(fault);
+
 #ifdef CONFIG_PRINTK
 	uint32_t exc_addr = _arc_v2_aux_reg_read(_ARC_V2_EFA);
 	uint32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
 
-	PR_EXC("Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x\n",
+	PR_EXC("Exception vector: 0x%" PRIx32 ", cause code: 0x%" PRIx32
+	       ", parameter 0x%" PRIx32 "\n",
 	       _ARC_V2_ECR_VECTOR(ecr),
 	       _ARC_V2_ECR_CODE(ecr),
 	       _ARC_V2_ECR_PARAMETER(ecr));
-	PR_EXC("Address 0x%x\n", exc_addr);
+	PR_EXC("Address 0x%" PRIx32 "\n", exc_addr);
 #endif
 }
 #endif /* CONFIG_FAULT_DUMP */

arch/arc/core/fault_s.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,12 +11,10 @@
  * Fault handlers for ARCv2 processors.
  */
 
-#define _ASMLANGUAGE
-
 #include <toolchain.h>
 #include <sections.h>
 #include <arch/cpu.h>
-#include "swap_macros.h"
+#include <swap_macros.h>
 
 GTEXT(_Fault)
 
@@ -44,11 +32,20 @@ GTEXT(__ev_extension)
 GTEXT(__ev_div_zero)
 GTEXT(__ev_dc_error)
 GTEXT(__ev_maligned)
-GDATA(_firq_stack)
 
+	.balign 4
 SECTION_VAR(BSS, saved_stack_pointer)
 	.word 0
 
+#if CONFIG_RGF_NUM_BANKS == 1
+GDATA(_exception_stack)
+SECTION_VAR(NOINIT, _exception_stack)
+	.space 512
+/* note: QUARK_SE_C1000_SS can't afford 512B */
+#else
+GDATA(_firq_stack)
+#endif
+
 /*
  * @brief Fault handler installed in the fault and reserved vectors
  */
@@ -71,20 +68,37 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
 
 	/*
 	 * Before invoking exception handler, the kernel switches to an exception
-	 * stack, which is really the FIRQ stack, to save the faulting thread's
-	 * registers. It can use the FIRQ stack because it knows it is unused
-	 * since it is save to assume that if an exception has happened in FIRQ
-	 * handler, the problem is fatal and all the kernel can do is just print
+	 * stack, to save the faulting thread's registers.
+	 * The exception is fatal and all the kernel can do is just print
 	 * a diagnostic message and halt.
 	 */
 
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
+
 	st sp, [saved_stack_pointer]
+#if CONFIG_RGF_NUM_BANKS == 1
+	mov_s sp, _exception_stack
+	add sp, sp, 512
+#else
 	mov_s sp, _firq_stack
 	add sp, sp, CONFIG_FIRQ_STACK_SIZE
+#endif
 
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
+
 	jl _Fault
 
 	/* if _Fault returns, restore the registers */
@@ -100,26 +114,77 @@ GTEXT(_irq_do_offload);
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	/*
 	 * Before invoking exception handler, the kernel switches to an exception
-	 * stack, which is really the FIRQ stack, to save the faulting thread's
-	 * registers. It can use the FIRQ stack because it knows it is unused
-	 * since it is save to assume that if an exception has happened in FIRQ
-	 * handler, the problem is fatal and all the kernel can do is just print
+	 * stack to save the faulting thread's registers.
+	 * The exception is fatal and all the kernel can do is just print
 	 * a diagnostic message and halt.
 	 */
 
-	st sp, [saved_stack_pointer]
-	mov_s sp, _firq_stack
-	add sp, sp, CONFIG_FIRQ_STACK_SIZE
+#ifdef CONFIG_ARC_STACK_CHECKING
+	push_s r2
+	/* disable stack checking */
+	lr r2, [_ARC_V2_STATUS32]
+	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
+	kflag r2
+	pop_s r2
+#endif
 
 	/* save caller saved registers */
 	_create_irq_stack_frame
 
+	lr r0,[_ARC_V2_ERSTATUS]
+	st_s r0, [sp, ___isf_t_status32_OFFSET]
+	lr r0,[_ARC_V2_ERET]
+	st_s r0, [sp, ___isf_t_pc_OFFSET] /* eret into pc */
+
 	jl _irq_do_offload
 
-	/* if _Fault returns, restore the registers */
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+	/* check if we're a nested interrupt: if so, let the
+	 * interrupted interrupt handle the reschedule
+	 */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
+	 * AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is 0, it
+	 * means trap was taken from outside an interrupt handler.
+	 * But if it was inside, let that handler do the swap.
+	 */
+	breq r3, 0, _trap_check_for_swap
+_trap_return:
 	_pop_irq_stack_frame
-
-	/* now restore the stack */
-	ld sp,[saved_stack_pointer]
 	rtie
+
+.balign 4
+_trap_check_for_swap:
+	/*
+	 * Non-preemptible thread ? Do not schedule (see explanation of
+	 * preempt field in kernel_struct.h).
+	 */
+	ldh_s r0, [r2, _thread_offset_to_preempt]
+	brhs r0, _NON_PREEMPT_THRESHOLD, _trap_return
+
+	/* check if the current thread needs to be rescheduled */
+	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
+	breq r0, r2, _trap_return
+
+	_save_callee_saved_regs
+
+	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
+	/* note: Ok to use _CAUSE_RIRQ since everything is saved */
+
+	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
+	st_s r2, [r1, _kernel_offset_to_current]
+
+	/* clear AE bit to forget this was an exception */
+	lr r3, [_ARC_V2_STATUS32]
+	and r3,r3,(~_ARC_V2_STATUS32_AE)
+	kflag r3
+	/* pretend lowest priority interrupt happened to use common handler */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+	/* Assumption: r2 has current thread */
+	b _rirq_common_interrupt_swap
+
 #endif /* CONFIG_IRQ_OFFLOAD */

arch/arc/core/irq_manage.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -22,15 +12,12 @@
  * Interrupt management:
  *
  * - enabling/disabling
- * - dynamic ISR connecting/replacing
- *
- * SW_ISR_TABLE_DYNAMIC has to be enabled for connecting ISRs at runtime.
  *
  * An IRQ number passed to the @a irq parameters found in this file is a
  * number from 16 to last IRQ number on the platform.
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <arch/cpu.h>
 #include <misc/__assert.h>
 #include <toolchain.h>
@@ -78,24 +65,23 @@ void _arch_irq_disable(unsigned int irq)
  *
  * @brief Set an interrupt's priority
  *
- * Valid values are from 0 to 15. Interrupts of priority 1 are not masked when
- * interrupts are locked system-wide, so care must be taken when using them. ISR
- * installed with priority 0 interrupts cannot make kernel calls.
- *
- * The priority is verified if ASSERT_ON is enabled.
+ * Lower values take priority over higher values. Special case priorities are
+ * expressed via mutually exclusive flags.
+
+ * The priority is verified if ASSERT_ON is enabled; max priority level
+ * depends on CONFIG_NUM_IRQ_PRIO_LEVELS.
  *
  * @return N/A
  */
 
-void _irq_priority_set(
-	unsigned int irq,
-	unsigned int prio
-)
+void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
+	ARG_UNUSED(flags);
+
 	int key = irq_lock();
 
-	__ASSERT(prio >= 0 && prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
-			 "invalid priority!");
+	__ASSERT(prio < CONFIG_NUM_IRQ_PRIO_LEVELS,
+		 "invalid priority %d for irq %d", prio, irq);
 	_arc_v2_irq_unit_prio_set(irq, prio);
 	irq_unlock(key);
 }
@@ -118,75 +104,3 @@ void _irq_spurious(void *unused)
 		;
 }
 
-#if CONFIG_SW_ISR_TABLE_DYNAMIC
-/*
- * @internal
- *
- * @brief Replace an interrupt handler by another
- *
- * An interrupt's ISR can be replaced at runtime.
- *
- * @return N/A
- */
-
-void _irq_handler_set(
-	unsigned int irq,
-	void (*new)(void *arg),
-	void *arg
-)
-{
-	int key = irq_lock();
-	int index = irq - 16;
-
-	__ASSERT(irq < CONFIG_NUM_IRQS, "IRQ number too high");
-	_sw_isr_table[index].isr = new;
-	_sw_isr_table[index].arg = arg;
-
-	irq_unlock(key);
-}
-
-/*
- * @brief Connect an ISR to an interrupt line
- *
- * @a isr is connected to interrupt line @a irq, a number greater than or equal
- * 16. No prior ISR can have been connected on @a irq interrupt line since the
- * system booted.
- *
- * This routine will hang if another ISR was connected for interrupt line @a irq
- * and ASSERT_ON is enabled; if ASSERT_ON is disabled, it will fail silently.
- *
- * @return the interrupt line number
- */
-
-int _arch_irq_connect_dynamic(
-	unsigned int irq,
-	unsigned int prio,
-	void (*isr)(void *arg),
-	void *arg,
-	uint32_t flags
-)
-{
-	ARG_UNUSED(flags);
-	_irq_handler_set(irq, isr, arg);
-	_irq_priority_set(irq, prio);
-	return irq;
-}
-
-/*
- * @internal
- *
- * @brief Disconnect an ISR from an interrupt line
- *
- * Interrupt line @a irq is disconnected from its ISR and the latter is
- * replaced by _irq_spurious(). irq_disable() should have been called before
- * invoking this routine.
- *
- * @return N/A
- */
-
-void _irq_disconnect(unsigned int irq)
-{
-	_irq_handler_set(irq, _irq_spurious, NULL);
-}
-
-#endif /* CONFIG_SW_ISR_TABLE_DYNAMIC */

arch/arc/core/irq_offload.c

@@ -1,24 +1,14 @@
 /*
  * Copyright (c) 2015 Intel corporation
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file Software interrupts utility code - ARC implementation
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <irq_offload.h>
 
 static irq_offload_routine_t offload_routine;

arch/arc/core/irq_vector_table.c

@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @brief IRQ part of vector table for Quark SE Sensor Subsystem
- *
- * This file contains the IRQ part of the vector table. It is meant to be used
- * for one of two cases:
- *
- * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
- * binds _IsrWrapper() to all the IRQ entries in the vector table.
- *
- * b) When the BSP is written so that device ISRs are installed directly in the
- * vector table, they are enumerated here.
- *
- */
-
-#include <toolchain.h>
-#include <sections.h>
-
-extern void _isr_enter(void);
-typedef void (*vth)(void); /* Vector Table Handler */
-
-#if defined(CONFIG_SW_ISR_TABLE)
-
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
-	[0 ...(CONFIG_NUM_IRQS - 17)] = _isr_enter
-};
-
-#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
-
-extern void _SpuriousIRQ(void);
-
-/* placeholders: fill with real ISRs */
-
-vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
-	[0 ...(CONFIG_NUM_IRQS - 17)] = _SpuriousIRQ
-};
-
-#endif /* CONFIG_SW_ISR_TABLE */

arch/arc/core/isr_wrapper.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -23,20 +13,26 @@
  * a parameter.
  */
 
-#define _ASMLANGUAGE
-
-#include <offsets.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <sections.h>
 #include <sw_isr_table.h>
-#include <nano_private.h>
+#include <kernel_structs.h>
 #include <arch/cpu.h>
 
-GTEXT(_isr_enter)
+GTEXT(_isr_wrapper)
 GTEXT(_isr_demux)
 
-#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
-GTEXT(_power_save_idle_exit)
+#if CONFIG_RGF_NUM_BANKS == 1
+GDATA(saved_r0)
+
+	.balign 4
+SECTION_VAR(BSS, saved_r0)
+        .word 0
+#endif
+
+#if defined(CONFIG_SYS_POWER_MANAGEMENT)
+GTEXT(_sys_power_save_idle_exit)
 #endif
 
 /*
@@ -45,9 +41,9 @@ _rirq_enter/_firq_enter: they are jump points.
 
 The flow is the following:
 
-ISR -> _isr_enter -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
-                     |
-                     + -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
+ISR -> _isr_wrapper -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
+                       |
+                       + -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
 
 Context switch explanation:
 
@@ -61,9 +57,6 @@ IRQ stack frame layout:
 
            status32
               pc
-          [jli_base]
-          [ldi_base]
-          [ei_base]
            lp_count
            lp_start
             lp_end
@@ -74,16 +67,21 @@ IRQ stack frame layout:
 
   low address
 
-  [registers not taken into account in the current implementation]
+Registers not taken into account in the current implementation.
+          jli_base
+          ldi_base
+          ei_base
+          accl
+          acch
 
 The context switch code adopts this standard so that it is easier to follow:
 
-  - r1 contains _nanokernel ASAP and is not overwritten over the lifespan of
+  - r1 contains _kernel ASAP and is not overwritten over the lifespan of
     the functions.
-  - r2 contains _nanokernel.current ASAP, and the incoming thread when we
+  - r2 contains _kernel.current ASAP, and the incoming thread when we
     transition from outgoing thread to incoming thread
 
-Not loading _nanokernel into r0 allows loading _nanokernel without stomping on
+Not loading _kernel into r0 allows loading _kernel without stomping on
 the parameter in r0 in _Swap().
 
 
@@ -92,16 +90,23 @@ official documentation calls the regular interrupts 'IRQs', but the internals
 of the kernel call them 'RIRQs' to differentiate from the 'irq' subsystem,
 which is the interrupt API/layer of abstraction.
 
-FIRQs can be used to allow ISRs to run without having to save any context,
-since they work with a second register bank. However, they can be somewhat more
-limited than RIRQs since the register bank does not copy every possible
-register that is needed to implement all available instructions: an example is
-that the 'loop' registers (lp_count, lp_end, lp_start) are not present in the
-second bank. The kernel thus takes upon itself to save these extra registers,
-if the FIRQ is made known to the kernel. It is possible for a FIRQ to operate
-outside of the kernel, but care must be taken to only use instructions that
-only use the banked registers. RIRQs must always use the kernel's interrupt
-entry and exit mechanisms.
+For FIRQ, there are two cases, depending upon the value of
+CONFIG_RGF_NUM_BANKS.
+
+CONFIG_RGF_NUM_BANKS==1 case:
+Scratch registers are pushed onto the current stack just as they are with
+RIRQ. See the above frame layout. Unlike RIRQ, the status32_p0 and ilink
+registers are where status32 and the program counter are located, so these
+need to be pushed.
+
+CONFIG_RGF_NUM_BANKS!=1 case:
+The FIRQ handler has its own register bank for general purpose registers,
+and thus it doesn't have to save them on a stack. The 'loop' registers
+(lp_count, lp_end, lp_start), however, are not present in the
+second bank. The handler saves these special registers in unused callee saved
+registers (to avoid stack accesses). It is possible to register a FIRQ
+handler that operates outside of the kernel, but care must be taken to only
+use instructions that only use the banked registers.
 
 The kernel is able to handle transitions to and from FIRQ, RIRQ and threads
 (fibers/task). The contexts are saved 'lazily': the minimum amount of work is
@@ -122,14 +127,24 @@ o FIRQ
   the FIRQ does not take a scheduling decision and leaves it the RIRQ to
   handle. This limits the amount of code that has to run at interrupt-level.
 
-  GPRs are banked, loop registers are saved in a global structure upon
-  interrupt entry. If returning to a fiber, loop registers are poppped and the
+  CONFIG_RGF_NUM_BANKS==1 case:
+  Registers are saved on the stack frame just as they are for RIRQ.
+  Context switch can happen just as it does in the RIRQ case, however,
+  if the FIRQ interrupted a RIRQ, the FIRQ will return from interrupt and
+  let the RIRQ do the context switch.  At entry, one register is needed in order
+  to have code to save other registers. r0 is saved first in a global called
+  saved_r0.
+
+  CONFIG_RGF_NUM_BANKS!=1 case:
+  During early initialization, the sp in the 2nd register bank is made to
+  refer to _firq_stack. This allows for the FIRQ handler to use its own stack.
+  GPRs are banked, loop registers are saved in unused callee saved regs upon
+  interrupt entry. If returning to a fiber, loop registers are restored and the
   CPU switches back to bank 0 for the GPRs. If a context switch is
   needed, at this point only are all the registers saved. First, a
   stack frame with the same layout as the automatic RIRQ one is created
   and then the callee-saved GPRs are saved in the TCS. status32_p0 and
   ilink are saved in this case, not status32 and pc.
-
   To create the stack frame, the FIRQ handling code must first go back to using
   bank0 of registers, since that is where the registers containing the exiting
   thread are saved. Care must be taken not to touch any register before saving
@@ -159,8 +174,10 @@ From coop:
 
 From FIRQ:
 
-  The processor is back to using bank0, not bank1 anymore, because it had to
-  save the outgoing context from bank0, and now has to load the incoming one
+  When CONFIG_RGF_NUM_BANKS==1, context switch is done as it is for RIRQ.
+  When CONFIG_RGF_NUM_BANKS!=1, the processor is put back to using bank0,
+  not bank1 anymore, because it had to save the outgoing context from bank0,
+  and now has to load the incoming one
   into bank0.
 
   o to coop
@@ -199,28 +216,107 @@ From RIRQ:
     interrupt.
  */
 
-SECTION_FUNC(TEXT, _isr_enter)
+SECTION_FUNC(TEXT, _isr_wrapper)
+#if CONFIG_RGF_NUM_BANKS == 1
+	st r0,[saved_r0]
+#endif
 	lr r0, [_ARC_V2_AUX_IRQ_ACT]
 	ffs r0, r0
 	cmp r0, 0
-
+#if CONFIG_RGF_NUM_BANKS == 1
+	bnz rirq_path
+	/* 1-register bank FIRQ handling must save registers on stack */
+	lr r0,[_ARC_V2_STATUS32_P0]
+	push_s r0
+	mov r0,ilink
+	push_s r0
+	mov r0,lp_count
+	push_s r0
+	lr r0, [_ARC_V2_LP_START]
+	push_s r0
+	lr r0, [_ARC_V2_LP_END]
+	push_s r0
+	push_s blink
+	push_s r13
+	push_s r12
+	push r11
+	push r10
+	push r9
+	push r8
+	push r7
+	push r6
+	push r5
+	push r4
+	push_s r3
+	push_s r2
+	push_s r1
+	ld r0,[saved_r0]
+	push_s r0
+	mov r3, _firq_exit
+	mov r2, _firq_enter
+	j_s [r2]
+rirq_path:
+	mov r3, _rirq_exit
+	mov r2, _rirq_enter
+	j_s [r2]
+#else
 	mov.z r3, _firq_exit
 	mov.z r2, _firq_enter
 	mov.nz r3, _rirq_exit
 	mov.nz r2, _rirq_enter
+	j_s [r2]
+#endif
 
-	j_s.nd [r2]
+#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
+GTEXT(_sys_k_event_logger_exit_sleep)
 
-#if defined(CONFIG_NANOKERNEL) && defined(CONFIG_TICKLESS_IDLE)
-.macro exit_tickless_idle
-	clri r0 /* do not interrupt exiting tickless idle operations */
+.macro log_sleep_k_event
+	clri r0 /* do not interrupt event logger operations */
 	push_s r0
 	push_s blink
-	jl _power_save_idle_exit
+	jl _sys_k_event_logger_exit_sleep
 	pop_s blink
 	pop_s r0
 	seti r0
 .endm
+#else
+	#define log_sleep_k_event
+#endif
+#if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
+GTEXT(_sys_k_event_logger_interrupt)
+
+.macro log_interrupt_k_event
+	clri r0 /* do not interrupt event logger operations */
+	push_s r0
+	push_s blink
+	jl _sys_k_event_logger_interrupt
+	pop_s blink
+	pop_s r0
+	seti r0
+.endm
+#else
+	#define log_interrupt_k_event
+#endif
+
+#if defined(CONFIG_SYS_POWER_MANAGEMENT)
+.macro exit_tickless_idle
+	clri r0 /* do not interrupt exiting tickless idle operations */
+	push_s r1
+	push_s r0
+	mov_s r1, _kernel
+	ld_s r0, [r1, _kernel_offset_to_idle] /* requested idle duration */
+	breq r0, 0, _skip_sys_power_save_idle_exit
+
+	st 0, [r1, _kernel_offset_to_idle] /* zero idle duration */
+	push_s blink
+	jl _sys_power_save_idle_exit
+	pop_s blink
+
+_skip_sys_power_save_idle_exit:
+	pop_s r0
+	pop_s r1
+	seti r0
+.endm
 #else
 	#define exit_tickless_idle
 #endif
@@ -232,6 +328,8 @@ SECTION_FUNC(TEXT, _isr_demux)
 	/* cannot be done before this point because we must be able to run C */
 	/* r0 is available to be stomped here, and exit_tickless_idle uses it */
 	exit_tickless_idle
+	log_interrupt_k_event
+	log_sleep_k_event
 
 	lr r0, [_ARC_V2_ICAUSE]
 	sub r0, r0, 16
@@ -239,11 +337,11 @@ SECTION_FUNC(TEXT, _isr_demux)
 	mov r1, _sw_isr_table
 	add3 r0, r1, r0   /* table entries are 8-bytes wide */
 
-	ld r1, [r0, 4] /* ISR into r1 */
+	ld_s r1, [r0, 4] /* ISR into r1 */
 	jl_s.d [r1]
 	ld_s r0, [r0] /* delay slot: ISR parameter into r0  */
 
 	/* back from ISR, jump to exit stub */
 	pop_s r3
-	j_s.nd [r3]
+	j_s [r3]
 	nop

arch/arc/core/offsets/offsets.c

@@ -1,30 +1,19 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
- * @brief ARCv2 nano kernel structure member offset definition file
+ * @brief ARCv2 kernel structure member offset definition file
  *
  * This module is responsible for the generation of the absolute symbols whose
- * value represents the member offsets for various ARCv2 nanokernel
- * structures.
+ * value represents the member offsets for various ARCv2 kernel structures.
  *
  * All of the absolute symbols defined by this module will be present in the
- * final microkernel or nanokernel ELF image (due to the linker's reference to
- * the _OffsetAbsSyms symbol).
+ * final kernel ELF image (due to the linker's reference to the _OffsetAbsSyms
+ * symbol).
  *
  * INTERNAL
  * It is NOT necessary to define the offset for every member of a structure.
@@ -34,81 +23,60 @@
  */
 
 #include <gen_offset.h>
-#include <nano_private.h>
-#include <nano_offsets.h>
+#include <kernel_structs.h>
+#include <kernel_offsets.h>
 
-/* ARCv2-specific tNANO structure member offsets */
-GEN_OFFSET_SYM(tNANO, rirq_sp);
-GEN_OFFSET_SYM(tNANO, firq_regs);
-#ifdef CONFIG_SYS_POWER_MANAGEMENT
-GEN_OFFSET_SYM(tNANO, idle);
-#endif
-
-/* ARCv2-specific struct tcs structure member offsets */
-GEN_OFFSET_SYM(tTCS, intlock_key);
-GEN_OFFSET_SYM(tTCS, relinquish_cause);
-GEN_OFFSET_SYM(tTCS, return_value);
+GEN_OFFSET_SYM(_thread_arch_t, intlock_key);
+GEN_OFFSET_SYM(_thread_arch_t, relinquish_cause);
+GEN_OFFSET_SYM(_thread_arch_t, return_value);
 #ifdef CONFIG_ARC_STACK_CHECKING
-GEN_OFFSET_SYM(tTCS, stack_top);
+GEN_OFFSET_SYM(_thread_arch_t, stack_top);
 #endif
-#ifdef CONFIG_THREAD_CUSTOM_DATA
-GEN_OFFSET_SYM(tTCS, custom_data);
-#endif
-
 
 /* ARCv2-specific IRQ stack frame structure member offsets */
-GEN_OFFSET_SYM(tISF, r0);
-GEN_OFFSET_SYM(tISF, r1);
-GEN_OFFSET_SYM(tISF, r2);
-GEN_OFFSET_SYM(tISF, r3);
-GEN_OFFSET_SYM(tISF, r4);
-GEN_OFFSET_SYM(tISF, r5);
-GEN_OFFSET_SYM(tISF, r6);
-GEN_OFFSET_SYM(tISF, r7);
-GEN_OFFSET_SYM(tISF, r8);
-GEN_OFFSET_SYM(tISF, r9);
-GEN_OFFSET_SYM(tISF, r10);
-GEN_OFFSET_SYM(tISF, r11);
-GEN_OFFSET_SYM(tISF, r12);
-GEN_OFFSET_SYM(tISF, r13);
-GEN_OFFSET_SYM(tISF, blink);
-GEN_OFFSET_SYM(tISF, lp_end);
-GEN_OFFSET_SYM(tISF, lp_start);
-GEN_OFFSET_SYM(tISF, lp_count);
-GEN_OFFSET_SYM(tISF, pc);
-GEN_OFFSET_SYM(tISF, status32);
-GEN_ABSOLUTE_SYM(__tISF_SIZEOF, sizeof(tISF));
+GEN_OFFSET_SYM(_isf_t, r0);
+GEN_OFFSET_SYM(_isf_t, r1);
+GEN_OFFSET_SYM(_isf_t, r2);
+GEN_OFFSET_SYM(_isf_t, r3);
+GEN_OFFSET_SYM(_isf_t, r4);
+GEN_OFFSET_SYM(_isf_t, r5);
+GEN_OFFSET_SYM(_isf_t, r6);
+GEN_OFFSET_SYM(_isf_t, r7);
+GEN_OFFSET_SYM(_isf_t, r8);
+GEN_OFFSET_SYM(_isf_t, r9);
+GEN_OFFSET_SYM(_isf_t, r10);
+GEN_OFFSET_SYM(_isf_t, r11);
+GEN_OFFSET_SYM(_isf_t, r12);
+GEN_OFFSET_SYM(_isf_t, r13);
+GEN_OFFSET_SYM(_isf_t, blink);
+GEN_OFFSET_SYM(_isf_t, lp_end);
+GEN_OFFSET_SYM(_isf_t, lp_start);
+GEN_OFFSET_SYM(_isf_t, lp_count);
+GEN_OFFSET_SYM(_isf_t, pc);
+GEN_OFFSET_SYM(_isf_t, status32);
+GEN_ABSOLUTE_SYM(___isf_t_SIZEOF, sizeof(_isf_t));
 
-/* ARCv2-specific preempt registers structure member offsets */
-GEN_OFFSET_SYM(tPreempt, sp);
-GEN_ABSOLUTE_SYM(__tPreempt_SIZEOF, sizeof(tPreempt));
+GEN_OFFSET_SYM(_callee_saved_t, sp);
+GEN_ABSOLUTE_SYM(___callee_saved_t_SIZEOF, sizeof(_callee_saved_t));
 
-/* ARCv2-specific callee-saved stack */
-GEN_OFFSET_SYM(tCalleeSaved, r13);
-GEN_OFFSET_SYM(tCalleeSaved, r14);
-GEN_OFFSET_SYM(tCalleeSaved, r15);
-GEN_OFFSET_SYM(tCalleeSaved, r16);
-GEN_OFFSET_SYM(tCalleeSaved, r17);
-GEN_OFFSET_SYM(tCalleeSaved, r18);
-GEN_OFFSET_SYM(tCalleeSaved, r19);
-GEN_OFFSET_SYM(tCalleeSaved, r20);
-GEN_OFFSET_SYM(tCalleeSaved, r21);
-GEN_OFFSET_SYM(tCalleeSaved, r22);
-GEN_OFFSET_SYM(tCalleeSaved, r23);
-GEN_OFFSET_SYM(tCalleeSaved, r24);
-GEN_OFFSET_SYM(tCalleeSaved, r25);
-GEN_OFFSET_SYM(tCalleeSaved, r26);
-GEN_OFFSET_SYM(tCalleeSaved, fp);
-GEN_OFFSET_SYM(tCalleeSaved, r30);
-GEN_ABSOLUTE_SYM(__tCalleeSaved_SIZEOF, sizeof(tCalleeSaved));
+GEN_OFFSET_SYM(_callee_saved_stack_t, r13);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r14);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r15);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r16);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r17);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r18);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r19);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r20);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r21);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r22);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r23);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r24);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r25);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r26);
+GEN_OFFSET_SYM(_callee_saved_stack_t, fp);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r30);
+GEN_ABSOLUTE_SYM(___callee_saved_stack_t_SIZEOF, sizeof(_callee_saved_stack_t));
 
-/* ARCv2-specific registers-saved-in-FIRQ structure member offsets */
-GEN_OFFSET_SYM(tFirqRegs, lp_count);
-GEN_OFFSET_SYM(tFirqRegs, lp_start);
-GEN_OFFSET_SYM(tFirqRegs, lp_end);
-GEN_ABSOLUTE_SYM(__tFirqRegs_SIZEOF, sizeof(tFirqRegs));
-
-/* size of the struct tcs structure sans save area for floating point regs */
-GEN_ABSOLUTE_SYM(__tTCS_NOFLOAT_SIZEOF, sizeof(tTCS));
+GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, sizeof(struct k_thread));
 
 GEN_ABS_SYM_END

arch/arc/core/prep_c.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -29,52 +19,88 @@
 #include <stdint.h>
 #include <toolchain.h>
 #include <linker-defs.h>
+#include <arch/arc/v2/aux_regs.h>
+#include <kernel_structs.h>
+#include <nano_internal.h>
 
+
+/* XXX - keep for future use in full-featured cache APIs */
+#if 0
 /**
  *
- * @brief Clear BSS
+ * @brief Disable the i-cache if present
  *
- * This routine clears the BSS region, so all bytes are 0.
+ * For those ARC CPUs that have a i-cache present,
+ * invalidate the i-cache and then disable it.
  *
  * @return N/A
  */
 
-static void bssZero(void)
+static void disable_icache(void)
 {
-	volatile uint32_t *pBSS = (uint32_t *)&__bss_start;
-	unsigned int n;
+	unsigned int val;
 
-	for (n = 0; n < (unsigned int)&__bss_num_words; n++) {
-		pBSS[n] = 0;
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val &= 0xff; /* version field */
+	if (val == 0) {
+		return; /* skip if i-cache is not present */
 	}
+	_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
+	__asm__ __volatile__ ("nop");
+	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
 }
 
 /**
  *
- * @brief Copy the data section from ROM to RAM
+ * @brief Invalidate the data cache if present
  *
- * This routine copies the data section from ROM to RAM.
+ * For those ARC CPUs that have a data cache present,
+ * invalidate the data cache.
  *
  * @return N/A
  */
 
-#ifdef CONFIG_XIP
-static void dataCopy(void)
+static void invalidate_dcache(void)
 {
-	volatile uint32_t *pROM = (uint32_t *)&__data_rom_start;
-	volatile uint32_t *pRAM = (uint32_t *)&__data_ram_start;
-	unsigned int n;
+	unsigned int val;
 
-	for (n = 0; n < (unsigned int)&__data_num_words; n++) {
-		pRAM[n] = pROM[n];
+	val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
+	val &= 0xff; /* version field */
+	if (val == 0) {
+		return; /* skip if d-cache is not present */
 	}
-}
-#else
-static void dataCopy(void)
-{
+	_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
 }
 #endif
 
+/**
+ *
+ * @brief Adjust the vector table base
+ *
+ * Set the vector table base if the value found in the
+ * _ARC_V2_IRQ_VECT_BASE auxiliary register is different from the
+ * _VectorTable known by software. It is important to do this very early
+ * so that exception vectors can be handled.
+ *
+ * @return N/A
+ */
+
+static void adjust_vector_table_base(void)
+{
+	extern struct vector_table _VectorTable;
+	unsigned int vbr;
+	/* if the compiled-in vector table is different
+	 * from the base address known by the ARC CPU,
+	 * set the vector base to the compiled-in address.
+	 */
+	vbr = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
+	vbr &= 0xfffffc00;
+	if (vbr != (unsigned int)&_VectorTable) {
+		_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
+					(unsigned int)&_VectorTable);
+	}
+}
+
 extern FUNC_NORETURN void _Cstart(void);
 /**
  *
@@ -87,8 +113,10 @@ extern FUNC_NORETURN void _Cstart(void);
 
 void _PrepC(void)
 {
-	bssZero();
-	dataCopy();
+	_icache_setup();
+	adjust_vector_table_base();
+	_bss_zero();
+	_data_copy();
 	_Cstart();
 	CODE_UNREACHABLE;
 }

arch/arc/core/regular_irq.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -24,16 +14,34 @@
  * See isr_wrapper.S for details.
  */
 
-#define _ASMLANGUAGE
-
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
-#include "swap_macros.h"
+#include <swap_macros.h>
 
 GTEXT(_rirq_enter)
 GTEXT(_rirq_exit)
+GTEXT(_rirq_common_interrupt_swap)
+
+#if 0 /* TODO: when FIRQ is not present, all would be regular */
+#define NUM_REGULAR_IRQ_PRIO_LEVELS CONFIG_NUM_IRQ_PRIO_LEVELS
+#else
+#define NUM_REGULAR_IRQ_PRIO_LEVELS (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
+#endif
+/* note: the above define assumes that prio 0 IRQ is for FIRQ, and
+ * that all others are regular interrupts.
+ * TODO: Revist this if FIRQ becomes configurable.
+ */
+
+#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
+#error "nested regular interrupts are not supported."
+/*
+ * Nesting of Regularing interrupts is not yet supported.
+ * Set CONFIG_NUM_IRQ_PRIO_LEVELS to 2 even if SOC supports more.
+ */
+#endif
+
 
 /**
  *
@@ -50,17 +58,17 @@ GTEXT(_rirq_exit)
 
 SECTION_FUNC(TEXT, _rirq_enter)
 
-	mov r1, _nanokernel
+	mov r1, _kernel
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* disable stack checking */
 	lr r2, [_ARC_V2_STATUS32]
 	bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
 	kflag r2
 #endif
-	ld r2, [r1, __tNANO_current_OFFSET]
-#if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS == 1
-	st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
-	ld sp, [r1, __tNANO_rirq_sp_OFFSET]
+	ld_s r2, [r1, _kernel_offset_to_current]
+#if NUM_REGULAR_IRQ_PRIO_LEVELS == 1
+	st sp, [r2, _thread_offset_to_sp]
+	ld sp, [r1, _kernel_offset_to_irq_stack]
 #else
 #error regular irq nesting is not implemented
 #endif
@@ -76,10 +84,19 @@ SECTION_FUNC(TEXT, _rirq_enter)
 
 SECTION_FUNC(TEXT, _rirq_exit)
 
-	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+#ifdef CONFIG_PREEMPT_ENABLED
 
-#if CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS > 1
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	/*
+	 * Lock interrupts to ensure kernel queues do not change from this
+	 * point on until return from interrupt.
+	 */
+
+	clri
+
+#if NUM_REGULAR_IRQ_PRIO_LEVELS > 1
 	/* check if we're a nested interrupt: if so, let the interrupted interrupt
 	 * handle the reschedule */
 
@@ -95,28 +112,34 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 */
 
 	cmp r0, r3
-	brgt.nd _rirq_return_from_rirq
-	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
+	brgt _rirq_return_from_rirq
 #endif
 
 	/*
-	 * Both (a)reschedule and (b)non-reschedule cases need to load the current
-	 * thread's stack, but don't have to use it until the decision is taken:
-	 * load the delay slots with the 'load stack pointer' instruction.
+	 * Non-preemptible thread ? Do not schedule (see explanation of
+	 * preempt field in kernel_struct.h).
+	 */
+	ldh_s r0, [r2, _thread_offset_to_preempt]
+	mov r3, _NON_PREEMPT_THRESHOLD
+	brhs.d r0, r3, _rirq_no_reschedule
+
+	/*
+	 * Both (a)reschedule and (b)non-reschedule cases need to load the
+	 * current thread's stack, but don't have to use it until the decision
+	 * is taken: load the delay slots with the 'load stack pointer'
+	 * instruction.
 	 *
 	 * a) needs to load it to save outgoing context.
 	 * b) needs to load it to restore the interrupted context.
 	 */
 
-	ld r0, [r2, __tTCS_flags_OFFSET]
-	and.f r0, r0, PREEMPTIBLE
-	bz.d _rirq_no_reschedule
-	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
+	ld sp, [r2, _thread_offset_to_sp]
 
-	ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
-	cmp r0, 0
-	bz.d _rirq_no_reschedule
-	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
+	/* check if the current thread needs to be rescheduled */
+	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
+	breq r0, r2, _rirq_no_reschedule
+
+	/* cached thread to run is in r0, fall through */
 
 .balign 4
 _rirq_reschedule:
@@ -124,19 +147,21 @@ _rirq_reschedule:
 	/* _save_callee_saved_regs expects outgoing thread in r2 */
 	_save_callee_saved_regs
 
-	st _CAUSE_RIRQ, [r2, __tTCS_relinquish_cause_OFFSET]
+	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
 
-	/* incoming fiber is in r0: it becomes the new 'current' */
+	/* incoming thread is in r0: it becomes the new 'current' */
 	mov r2, r0
-	st r2, [r1, __tNANO_current_OFFSET]
-	ld r3, [r2, __tTCS_link_OFFSET]
-	st r3, [r1, __tNANO_fiber_OFFSET]
+	st_s r2, [r1, _kernel_offset_to_current]
+
+.balign 4
+_rirq_common_interrupt_swap:
+	/* r2 contains pointer to new thread */
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
-	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/*
@@ -145,11 +170,11 @@ _rirq_reschedule:
 	 */
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
-	breq.nd r3, _CAUSE_RIRQ, _rirq_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _rirq_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _rirq_return_from_firq
+	breq r3, _CAUSE_FIRQ, _rirq_return_from_firq
 	nop
 
 	/* fall through */
@@ -160,20 +185,23 @@ _rirq_return_from_coop:
 	/* status32 and pc (blink) are already on the stack in the right order */
 
 	/* update status32.ie (explanation in firq_exit:_firq_return_from_coop) */
-	ld r0, [sp, 4]
-	ld r3, [r2, __tTCS_intlock_key_OFFSET]
-	st  0, [r2, __tTCS_intlock_key_OFFSET]
+	ld_s r0, [sp, 4]
+	ld_s r3, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
 	cmp r3, 0
 	or.ne r0, r0, _ARC_V2_STATUS32_IE
-	st r0, [sp, 4]
+	st_s r0, [sp, 4]
 
 	/* carve fake stack */
 
-	sub sp, sp, (__tISF_SIZEOF - 12) /* a) status32/pc are already on the stack
-	                                  * b) a real value will be pushed in r0 */
+	/*
+	 * a) status32/pc are already on the stack
+	 * b) a real value will be pushed in r0
+	 */
+	sub sp, sp, (___isf_t_SIZEOF - 12)
 
 	/* push return value on stack */
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r0, [r2, _thread_offset_to_return_value]
 	push_s r0
 
 	/*
@@ -182,7 +210,7 @@ _rirq_return_from_coop:
 	 * IRQ prologue. r13 thus has to be set to its correct value in the IRQ
 	 * stack frame.
 	 */
-	st r13, [sp, __tISF_r13_OFFSET]
+	st_s r13, [sp, ___isf_t_r13_OFFSET]
 
 	/* stack now has the IRQ stack frame layout, pointing to r0 */
 
@@ -196,6 +224,8 @@ _rirq_return_from_rirq:
 
 	/* fall through to rtie instruction */
 
+#endif /* CONFIG_PREEMPT_ENABLED */
+
 .balign 4
 _rirq_no_reschedule:
 

arch/arc/core/reset.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,16 +11,35 @@
  * Reset handler that prepares the system for running C code.
  */
 
-#define _ASMLANGUAGE
-
 // #include <board.h>
 #include <toolchain.h>
 #include <sections.h>
 #include <arch/cpu.h>
 
-#define _RAM_END (CONFIG_RAM_START + CONFIG_RAM_SIZE * 1024)
+GDATA(_interrupt_stack)
+GDATA(_firq_stack)
+GDATA(_main_stack)
+
+/* use one of the available interrupt stacks during init */
+
+/* FIRQ only ? */
+#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
+
+	/* FIRQ, but uses _interrupt_stack ? */
+	#if CONFIG_RGF_NUM_BANKS == 1
+		#define INIT_STACK _interrupt_stack
+		#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
+	#else
+		#define INIT_STACK _firq_stack
+		#define INIT_STACK_SIZE CONFIG_FIRQ_STACK_SIZE
+	#endif
+#else
+	#define INIT_STACK _interrupt_stack
+	#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
+#endif
 
 GTEXT(__reset)
+GTEXT(__start)
 
 /**
  *
@@ -47,11 +56,66 @@ GTEXT(__reset)
  */
 
 SECTION_FUNC(TEXT,__reset)
+SECTION_FUNC(TEXT,__start)
 
 	/* lock interrupts: will get unlocked when switch to main task */
 	clri
 
-	/* setup a stack at the end of the RAM */
-	mov sp, _RAM_END
+	mov r1, 1
+
+invalidate_and_disable_icache:
+
+	lr r0, [_ARC_V2_I_CACHE_BUILD]
+	and.f r0, r0, 0xff
+	bz.nd invalidate_dcache
+
+	mov_s r2, 0
+	sr r2, [_ARC_V2_IC_IVIC]
+	/* writing to IC_IVIC needs 3 NOPs */
+	nop
+	nop
+	nop
+	sr r1, [_ARC_V2_IC_CTRL]
+
+invalidate_dcache:
+
+	lr r3, [_ARC_V2_D_CACHE_BUILD]
+	and.f r3, r3, 0xff
+	bz.nd done_cache_invalidate
+
+	sr r1, [_ARC_V2_DC_IVDC]
+
+done_cache_invalidate:
+
+#if defined(CONFIG_SYS_POWER_DEEP_SLEEP) && \
+	!defined(CONFIG_BOOTLOADER_CONTEXT_RESTORE)
+        jl @_sys_soc_resume_from_deep_sleep
+#endif
+
+#ifdef CONFIG_INIT_STACKS
+	/*
+	 * use the main stack to call memset on the interrupt stack and the
+	 * FIRQ stack when CONFIG_INIT_STACKS is enabled before switching to
+	 * one of them for the rest of the early boot
+	 */
+	mov sp, _main_stack
+	add sp, sp, CONFIG_MAIN_STACK_SIZE
+
+	mov_s r0, _interrupt_stack
+	mov_s r1, 0xaa
+	mov_s r2, CONFIG_ISR_STACK_SIZE
+	jl memset
+
+#if CONFIG_RGF_NUM_BANKS != 1
+	mov_s r0, _firq_stack
+	mov_s r1, 0xaa
+	mov_s r2, CONFIG_FIRQ_STACK_SIZE
+	jl memset
+#endif
+
+#endif /* CONFIG_INIT_STACKS */
+
+	mov sp, INIT_STACK
+	add sp, sp, INIT_STACK_SIZE
 
 	j @_PrepC

arch/arc/core/sw_isr_table.S

@@ -1,64 +0,0 @@
-/* sw_isr_table.S - ISR table for static ISR declarations for ARC */
-
-/*
- * Copyright (c) 2015 Intel Corporation
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#define _ASMLANGUAGE
-
-#include <toolchain.h>
-#include <sections.h>
-#include <arch/cpu.h>
-
-/*
- * enable preprocessor features, such
- * as %expr - evaluate the expression and use it as a string
- */
-.altmacro
-
-/*
- * Define an ISR table entry
- * Define symbol as weak and give the section .gnu.linkonce
- * prefix. This allows linker overload the symbol and the
- * whole section by the one defined by a device driver
- */
-.macro _isr_table_entry_declare index
-	WDATA(_isr_irq\index)
-	.section .gnu.linkonce.isr_irq\index
-	_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
-.endm
-
-/*
- * Declare the ISR table
- */
-.macro _isr_table_declare from, to
-	counter = \from
-	.rept (\to - \from)
-		_isr_table_entry_declare %counter
-		counter = counter + 1
-	.endr
-.endm
-
-GTEXT(_irq_spurious)
-GDATA(_sw_isr_table)
-
-.section .isr_irq16
-.align
-_sw_isr_table:
-
-/*In ARC architecture, IRQ 0-15 are reserved for the system and are not
-assignable by the user, for that reason the isr table linker section
-start at IRQ 16*/
-_isr_table_declare 16 CONFIG_NUM_IRQS

arch/arc/core/swap.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -24,26 +14,24 @@
  * See isr_wrapper.S for details.
  */
 
-#define _ASMLANGUAGE
-
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <toolchain.h>
 #include <arch/cpu.h>
 #include <v2/irq.h>
-#include "swap_macros.h"
+#include <swap_macros.h>
 
 GTEXT(_Swap)
-
-GDATA(_nanokernel)
+GDATA(_k_neg_eagain)
+GDATA(_kernel)
 
 /**
  *
  * @brief Initiate a cooperative context switch
  *
- * The _Swap() routine is invoked by various nanokernel services to effect
+ * The _Swap() routine is invoked by various kernel services to effect
  * a cooperative context switch.  Prior to invoking _Swap(), the caller
- * disables interrupts via nanoCpuIntLock() and the return 'key' is passed as a
+ * disables interrupts via irq_lock() and the return 'key' is passed as a
  * parameter to _Swap(). The key is in fact the value stored in the register
  * operand of a CLRI instruction.
  *
@@ -55,13 +43,15 @@ GDATA(_nanokernel)
  * popped when returning from _Swap(), but is not suitable for handling a return
  * from an exception. Thus, the fact that the thread is pending because of a
  * cooperative call to _Swap() has to be recorded via the _CAUSE_COOP code in
- * the relinquish_cause of the thread's tTCS. The _IrqExit()/_FirqExit() code
- * will take care of doing the right thing to restore the thread status.
+ * the relinquish_cause of the thread's k_thread structure. The
+ * _IrqExit()/_FirqExit() code will take care of doing the right thing to
+ * restore the thread status.
  *
  * When _Swap() is invoked, we know the decision to perform a context switch or
  * not has already been taken and a context switch must happen.
  *
- * @return may contain a return value setup by a call to fiberRtnValueSet()
+ * @return may contain a return value setup by a call to
+ * _set_thread_return_value()
  *
  * C function prototype:
  *
@@ -73,12 +63,21 @@ SECTION_FUNC(TEXT, _Swap)
 
 	/* interrupts are locked, interrupt key is in r0 */
 
-	mov r1, _nanokernel
-	ld r2, [r1, __tNANO_current_OFFSET]
+	mov r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
 
 	/* save intlock key */
-	st r0, [r2, __tTCS_intlock_key_OFFSET]
-	st _CAUSE_COOP, [r2, __tTCS_relinquish_cause_OFFSET]
+	st_s r0, [r2, _thread_offset_to_intlock_key]
+	st _CAUSE_COOP, [r2, _thread_offset_to_relinquish_cause]
+
+	/*
+         * Carve space for the return value. Setting it to a defafult of
+         * -EAGAIN eliminates the need for the timeout code to set it.
+         * If another value is ever needed, it can be modified with
+         * _set_thread_return_value().
+         */
+	ld r3, [_k_neg_eagain]
+	st_s r3, [r2, _thread_offset_to_return_value]
 
 	/*
 	 * Save status32 and blink on the stack before the callee-saved registers.
@@ -95,51 +94,27 @@ SECTION_FUNC(TEXT, _Swap)
 
 	_save_callee_saved_regs
 
-	ld r2, [r1, __tNANO_fiber_OFFSET]
-	breq.nd r2, 0, _swap_to_the_task
-
-.balign 4
-_swap_to_a_fiber:
-
-	ld r3, [r2, __tTCS_link_OFFSET]
-	b.d _finish_swapping_to_thread    /* always execute delay slot */
-	st r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
-
-.balign 4
-_swap_to_the_task:
-
-	ld r2, [r1, __tNANO_task_OFFSET]
-
-	/* fall through */
-
-.balign 4
-_finish_swapping_to_thread:
-
+	/* get the cached thread to run */
+	ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
 
 	/* entering here, r2 contains the new current thread */
-#if 0
-/* don't save flags in tNANO: slower, error-prone, and might not even give
- * a speed boost where it's supposed to */
-	ld r3, [r2, __tTCS_flags_OFFSET]
-	st r3, [r1, __tNANO_flags_OFFSET]
-#endif
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* Use stack top and down registers from restored context */
-	add r3, r2, __tTCS_NOFLOAT_SIZEOF
+	add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
 	sr r3, [_ARC_V2_KSTACK_TOP]
-	ld r3, [r2, __tTCS_stack_top_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_stack_top]
 	sr r3, [_ARC_V2_KSTACK_BASE]
 #endif
 	/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
-	st r2, [r1, __tNANO_current_OFFSET]
+	st_s r2, [r1, _kernel_offset_to_current]
 
 	_load_callee_saved_regs
 
-	ld r3, [r2, __tTCS_relinquish_cause_OFFSET]
+	ld_s r3, [r2, _thread_offset_to_relinquish_cause]
 
-	breq.nd r3, _CAUSE_RIRQ, _swap_return_from_rirq
+	breq r3, _CAUSE_RIRQ, _swap_return_from_rirq
 	nop
-	breq.nd r3, _CAUSE_FIRQ, _swap_return_from_firq
+	breq r3, _CAUSE_FIRQ, _swap_return_from_firq
 	nop
 
 	/* fall through to _swap_return_from_coop */
@@ -147,19 +122,12 @@ _finish_swapping_to_thread:
 .balign 4
 _swap_return_from_coop:
 
-	ld r1, [r2, __tTCS_intlock_key_OFFSET]
-	st  0, [r2, __tTCS_intlock_key_OFFSET]
-	ld r0, [r2, __tTCS_return_value_OFFSET]
+	ld_s r1, [r2, _thread_offset_to_intlock_key]
+	st  0, [r2, _thread_offset_to_intlock_key]
+	ld_s r0, [r2, _thread_offset_to_return_value]
 
-	/*
-	 * Adjust the stack here in case we go to _return_from_exc: this allows
-	 * keeping handling both coop and irq cases in _return_from_exc without
-	 * adding extra logic.
-	 */
-	add_s sp, sp, 8
 	lr ilink, [_ARC_V2_STATUS32]
 	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
-	sub_s sp, sp, 8
 
 	pop_s blink /* pc into blink */
 	pop_s r3    /* status32 into r3 */
@@ -173,39 +141,32 @@ _swap_return_from_coop:
 _swap_return_from_rirq:
 _swap_return_from_firq:
 
-	_pop_irq_stack_frame
-
-	lr ilink, [_ARC_V2_STATUS32]
-	bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
-
-	ld ilink, [sp, -4] /* status32 into ilink */
-#ifdef CONFIG_ARC_STACK_CHECKING
-	and ilink, ilink, 0x7fffbffe // keep SC off till we stop using under SP
-#else
-	and ilink, ilink, 0x7ffffffe // keep interrupts disabled until seti
-#endif
-	kflag ilink
-
-	ld ilink, [sp, -8] /* pc into ilink */
-
-#ifdef CONFIG_ARC_STACK_CHECKING
-	/* Enable stack checking now it is safe */
-	push_s r3
 	lr r3, [_ARC_V2_STATUS32]
-	bset r3, r3, _ARC_V2_STATUS32_SC_BIT
-	flag r3
-	pop_s r3
-#endif
-	j.d [ilink]
-	seti (_ARC_V2_DEF_IRQ_LEVEL | (1 << 4))
+	bbit1 r3, _ARC_V2_STATUS32_AE_BIT, _return_from_exc_irq
+
+	/* pretend interrupt happened to use rtie instruction */
+	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	brne r3,0,_swap_already_in_irq
+
+	or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1)) /* use lowest */
+	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+
+_swap_already_in_irq:
+	rtie
 
 .balign 4
+_return_from_exc_irq:
+	_pop_irq_stack_frame
+	sub_s sp, sp, 8
+
 _return_from_exc:
+
 	/* put the return address to eret */
-	ld ilink, [sp, -8] /* pc into ilink */
+	ld ilink, [sp] /* pc into ilink */
 	sr ilink, [_ARC_V2_ERET]
 
 	/* put status32 into estatus */
-	ld ilink, [sp, -4] /* status32 into ilink */
+	ld ilink, [sp, 4] /* status32 into ilink */
 	sr ilink, [_ARC_V2_ERSTATUS]
+	add_s sp, sp, 8
 	rtie

arch/arc/core/swap_macros.h

@@ -1,171 +0,0 @@
-/* swap_macros.h - helper macros for context switch */
-
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _SWAP_MACROS__H_
-#define _SWAP_MACROS__H_
-
-#include <nano_private.h>
-#include <offsets.h>
-#include <toolchain.h>
-#include <arch/cpu.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef _ASMLANGUAGE
-
-/* entering this macro, current is in r2 */
-.macro _save_callee_saved_regs
-
-	sub_s sp, sp, __tCalleeSaved_SIZEOF
-
-	/* save regs on stack */
-	st r13, [sp, __tCalleeSaved_r13_OFFSET]
-	st r14, [sp, __tCalleeSaved_r14_OFFSET]
-	st r15, [sp, __tCalleeSaved_r15_OFFSET]
-	st r16, [sp, __tCalleeSaved_r16_OFFSET]
-	st r17, [sp, __tCalleeSaved_r17_OFFSET]
-	st r18, [sp, __tCalleeSaved_r18_OFFSET]
-	st r19, [sp, __tCalleeSaved_r19_OFFSET]
-	st r20, [sp, __tCalleeSaved_r20_OFFSET]
-	st r21, [sp, __tCalleeSaved_r21_OFFSET]
-	st r22, [sp, __tCalleeSaved_r22_OFFSET]
-	st r23, [sp, __tCalleeSaved_r23_OFFSET]
-	st r24, [sp, __tCalleeSaved_r24_OFFSET]
-	st r25, [sp, __tCalleeSaved_r25_OFFSET]
-	st r26, [sp, __tCalleeSaved_r26_OFFSET]
-	st fp,  [sp, __tCalleeSaved_fp_OFFSET]
-	st r30, [sp, __tCalleeSaved_r30_OFFSET]
-
-	/* save stack pointer in struct tcs */
-	st sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
-.endm
-
-/* entering this macro, current is in r2 */
-.macro _load_callee_saved_regs
-	/* restore stack pointer from struct tcs */
-	ld sp, [r2, __tTCS_preempReg_OFFSET + __tPreempt_sp_OFFSET]
-
-	ld r13, [sp, __tCalleeSaved_r13_OFFSET]
-	ld r14, [sp, __tCalleeSaved_r14_OFFSET]
-	ld r15, [sp, __tCalleeSaved_r15_OFFSET]
-	ld r16, [sp, __tCalleeSaved_r16_OFFSET]
-	ld r17, [sp, __tCalleeSaved_r17_OFFSET]
-	ld r18, [sp, __tCalleeSaved_r18_OFFSET]
-	ld r19, [sp, __tCalleeSaved_r19_OFFSET]
-	ld r20, [sp, __tCalleeSaved_r20_OFFSET]
-	ld r21, [sp, __tCalleeSaved_r21_OFFSET]
-	ld r22, [sp, __tCalleeSaved_r22_OFFSET]
-	ld r23, [sp, __tCalleeSaved_r23_OFFSET]
-	ld r24, [sp, __tCalleeSaved_r24_OFFSET]
-	ld r25, [sp, __tCalleeSaved_r25_OFFSET]
-	ld r26, [sp, __tCalleeSaved_r26_OFFSET]
-	ld fp,  [sp, __tCalleeSaved_fp_OFFSET]
-	ld r30, [sp, __tCalleeSaved_r30_OFFSET]
-
-	add_s sp, sp, __tCalleeSaved_SIZEOF
-
-.endm
-
-/*
- * Must be called with interrupts locked or in P0.
- * Upon exit, sp will be pointing to the stack frame.
- */
-.macro _create_irq_stack_frame
-
-	sub_s sp, sp, __tISF_SIZEOF
-
-	st blink, [sp, __tISF_blink_OFFSET]
-
-	/* store these right away so we can use them if needed */
-
-	st_s r13, [sp, __tISF_r13_OFFSET]
-	st_s r12, [sp, __tISF_r12_OFFSET]
-	st   r11, [sp, __tISF_r11_OFFSET]
-	st   r10, [sp, __tISF_r10_OFFSET]
-	st   r9,  [sp, __tISF_r9_OFFSET]
-	st   r8,  [sp, __tISF_r8_OFFSET]
-	st   r7,  [sp, __tISF_r7_OFFSET]
-	st   r6,  [sp, __tISF_r6_OFFSET]
-	st   r5,  [sp, __tISF_r5_OFFSET]
-	st   r4,  [sp, __tISF_r4_OFFSET]
-	st_s r3,  [sp, __tISF_r3_OFFSET]
-	st_s r2,  [sp, __tISF_r2_OFFSET]
-	st_s r1,  [sp, __tISF_r1_OFFSET]
-	st_s r0,  [sp, __tISF_r0_OFFSET]
-
-	mov r0, lp_count
-	st_s r0, [sp, __tISF_lp_count_OFFSET]
-	lr r0, [_ARC_V2_LP_START]
-	st_s r0, [sp, __tISF_lp_start_OFFSET]
-	lr r0, [_ARC_V2_LP_END]
-	st_s r0, [sp, __tISF_lp_end_OFFSET]
-
-.endm
-
-/*
- * Must be called with interrupts locked or in P0.
- * sp must be pointing the to stack frame.
- */
-.macro _pop_irq_stack_frame
-
-	ld blink, [sp, __tISF_blink_OFFSET]
-
-	ld_s r0, [sp, __tISF_lp_count_OFFSET]
-	mov lp_count, r0
-	ld_s r0, [sp, __tISF_lp_start_OFFSET]
-	sr r0, [_ARC_V2_LP_START]
-	ld_s r0, [sp, __tISF_lp_end_OFFSET]
-	sr r0, [_ARC_V2_LP_END]
-
-	ld_s r13, [sp, __tISF_r13_OFFSET]
-	ld_s r12, [sp, __tISF_r12_OFFSET]
-	ld   r11, [sp, __tISF_r11_OFFSET]
-	ld   r10, [sp, __tISF_r10_OFFSET]
-	ld   r9,  [sp, __tISF_r9_OFFSET]
-	ld   r8,  [sp, __tISF_r8_OFFSET]
-	ld   r7,  [sp, __tISF_r7_OFFSET]
-	ld   r6,  [sp, __tISF_r6_OFFSET]
-	ld   r5,  [sp, __tISF_r5_OFFSET]
-	ld   r4,  [sp, __tISF_r4_OFFSET]
-	ld_s r3,  [sp, __tISF_r3_OFFSET]
-	ld_s r2,  [sp, __tISF_r2_OFFSET]
-	ld_s r1,  [sp, __tISF_r1_OFFSET]
-	ld_s r0,  [sp, __tISF_r0_OFFSET]
-
-	/*
-	 * All gprs have been reloaded, the only one that is still usable is
-	 * ilink.
-	 *
-	 * The pc and status32 values will still be on the stack. We cannot
-	 * pop them yet because the callers of _pop_irq_stack_frame must reload
-	 * status32 differently depending on the execution context they are running
-	 * in (_Swap(), firq or exception).
-	 */
-	add_s sp, sp, __tISF_SIZEOF
-
-.endm
-
-#endif /* _ASMLANGUAGE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*  _SWAP_MACROS__H_ */

arch/arc/core/sys_fatal_error_handler.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,30 +11,11 @@
  * This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs.
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <toolchain.h>
 #include <sections.h>
-
-#ifdef CONFIG_PRINTK
+#include <kernel_structs.h>
 #include <misc/printk.h>
-#define PRINTK(...) printk(__VA_ARGS__)
-#else
-#define PRINTK(...)
-#endif
-
-#ifdef CONFIG_MICROKERNEL
-extern void _TaskAbort(void);
-static inline void nonEssentialTaskAbort(void)
-{
-	PRINTK("Fatal fault in task ! Aborting task.\n");
-	_TaskAbort();
-}
-#define NON_ESSENTIAL_TASK_ABORT() nonEssentialTaskAbort()
-#else
-#define NON_ESSENTIAL_TASK_ABORT() \
-	do {/* nothing */          \
-	} while ((0))
-#endif
 
 /**
  *
@@ -66,28 +37,26 @@ static inline void nonEssentialTaskAbort(void)
  *
  * @return N/A
  */
-void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF * pEsf)
+FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
+					 const NANO_ESF *pEsf)
 {
-	nano_context_type_t curCtx = sys_execution_context_type_get();
-
 	ARG_UNUSED(reason);
 	ARG_UNUSED(pEsf);
 
-	if ((curCtx == NANO_CTX_ISR) || _is_thread_essential(NULL)) {
-		PRINTK("Fatal fault in %s ! Spinning...\n",
-		       NANO_CTX_ISR == curCtx
-			       ? "ISR"
-			       : NANO_CTX_FIBER == curCtx ? "essential fiber"
-							  : "essential task");
+#if !defined(CONFIG_SIMPLE_FATAL_ERROR_HANDLER)
+	if (k_is_in_isr() || _is_thread_essential()) {
+		printk("Fatal fault in %s! Spinning...\n",
+		       k_is_in_isr() ? "ISR" : "essential thread");
 		for (;;)
 			; /* spin forever */
 	}
-
-	if (NANO_CTX_FIBER == curCtx) {
-		PRINTK("Fatal fault in fiber ! Aborting fiber.\n");
-		fiber_abort();
-		return;
+	printk("Fatal fault in thread %p! Aborting.\n", _current);
+	k_thread_abort(_current);
+#else
+	for (;;) {
+		k_cpu_idle();
 	}
+#endif
 
-	NON_ESSENTIAL_TASK_ABORT();
+	CODE_UNREACHABLE;
 }

arch/arc/core/thread.c

@@ -1,31 +1,20 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
  * @brief New thread creation for ARCv2
  *
- * Core nanokernel fiber related primitives for the ARCv2 processor
- * architecture.
+ * Core thread related primitives for the ARCv2 processor architecture.
  */
 
-#include <nanokernel.h>
+#include <kernel.h>
 #include <toolchain.h>
-#include <nano_private.h>
-#include <offsets.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
 #include <wait_q.h>
 #ifdef CONFIG_INIT_STACKS
 #include <string.h>
@@ -40,46 +29,29 @@ struct init_stack_frame {
 	uint32_t r0;
 };
 
-tNANO _nanokernel = {0};
-
-#if defined(CONFIG_THREAD_MONITOR)
-#define THREAD_MONITOR_INIT(tcs) thread_monitor_init(tcs)
-#else
-#define THREAD_MONITOR_INIT(tcs) \
-	do {/* do nothing */     \
-	} while ((0))
-#endif
-
 #if defined(CONFIG_THREAD_MONITOR)
 /*
- * @brief Initialize thread monitoring support
- *
- * Currently only inserts the new thread in the list of active threads.
- *
- * @return N/A
+ * Add a thread to the kernel's list of active threads.
  */
-
-static ALWAYS_INLINE void thread_monitor_init(struct tcs *tcs)
+static ALWAYS_INLINE void thread_monitor_init(struct k_thread *thread)
 {
 	unsigned int key;
 
-	/*
-	 * Add the newly initialized thread to head of the list of threads.  This
-	 * singly linked list of threads maintains ALL the threads in the system:
-	 * both tasks and fibers regardless of whether they are runnable.
-	 */
-
 	key = irq_lock();
-	tcs->next_thread = _nanokernel.threads;
-	_nanokernel.threads = tcs;
+	thread->next_thread = _kernel.threads;
+	_kernel.threads = thread;
 	irq_unlock(key);
 }
+#else
+#define thread_monitor_init(thread) \
+	do {/* do nothing */     \
+	} while ((0))
 #endif /* CONFIG_THREAD_MONITOR */
 
 /*
  * @brief Initialize a new thread from its stack space
  *
- * The control structure (TCS) is put at the lower address of the stack. An
+ * The thread control structure is put at the lower address of the stack. An
  * initial context, to be "restored" by __return_from_coop(), is put at
  * the other end of the stack, and thus reusable by the stack when not
  * needed anymore.
@@ -96,19 +68,22 @@ static ALWAYS_INLINE void thread_monitor_init(struct tcs *tcs)
  * @param parameter1 first param to entry point
  * @param parameter2 second param to entry point
  * @param parameter3 third param to entry point
- * @param fiber priority, -1 for task
- * @param options is unused (saved for future expansion)
+ * @param priority thread priority
+ * @param options thread options: K_ESSENTIAL
  *
  * @return N/A
  */
-void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
+void _new_thread(char *pStackMem, size_t stackSize,
+		 _thread_entry_t pEntry,
 		 void *parameter1, void *parameter2, void *parameter3,
 		 int priority, unsigned options)
 {
+	_ASSERT_VALID_PRIO(priority, pEntry);
+
 	char *stackEnd = pStackMem + stackSize;
 	struct init_stack_frame *pInitCtx;
 
-	struct tcs *tcs = (struct tcs *) pStackMem;
+	struct k_thread *thread = (struct k_thread *) pStackMem;
 
 #ifdef CONFIG_INIT_STACKS
 	memset(pStackMem, 0xaa, stackSize);
@@ -133,40 +108,43 @@ void _new_thread(char *pStackMem, unsigned stackSize, _thread_entry_t pEntry,
 	 */
 #ifdef CONFIG_ARC_STACK_CHECKING
 	pInitCtx->status32 = _ARC_V2_STATUS32_SC | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
-	tcs->stack_top = (uint32_t) stackEnd;
+	thread->arch.stack_top = (uint32_t) stackEnd;
 #else
 	pInitCtx->status32 = _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
 #endif
-	tcs->link = NULL;
-	tcs->flags = priority == -1 ? TASK | PREEMPTIBLE : FIBER;
-	tcs->prio = priority;
+
+	_init_thread_base(&thread->base, priority, _THREAD_PRESTART, options);
+
+	/* static threads overwrite them afterwards with real values */
+	thread->init_data = NULL;
+	thread->fn_abort = NULL;
 
 #ifdef CONFIG_THREAD_CUSTOM_DATA
 	/* Initialize custom data field (value is opaque to kernel) */
 
-	tcs->custom_data = NULL;
+	thread->custom_data = NULL;
 #endif
 
 #ifdef CONFIG_THREAD_MONITOR
 	/*
-	 * In debug mode tcs->entry give direct access to the thread entry
+	 * In debug mode thread->entry give direct access to the thread entry
 	 * and the corresponding parameters.
 	 */
-	tcs->entry = (struct __thread_entry *)(pInitCtx);
+	thread->entry = (struct __thread_entry *)(pInitCtx);
 #endif
+
 	/*
 	 * intlock_key is constructed based on ARCv2 ISA Programmer's
 	 * Reference Manual CLRI instruction description:
 	 * dst[31:6] dst[5] dst[4]       dst[3:0]
 	 *    26'd0    1    STATUS32.IE  STATUS32.E[3:0]
 	 */
-	tcs->intlock_key = 0x3F;
-	tcs->relinquish_cause = _CAUSE_COOP;
-	tcs->preempReg.sp = (uint32_t)pInitCtx - __tCalleeSaved_SIZEOF;
+	thread->arch.intlock_key = 0x3F;
+	thread->arch.relinquish_cause = _CAUSE_COOP;
+	thread->callee_saved.sp =
+		(uint32_t)pInitCtx - ___callee_saved_stack_t_SIZEOF;
 
-	_nano_timeout_tcs_init(tcs);
+	/* initial values in all other regs/k_thread entries are irrelevant */
 
-	/* initial values in all other registers/TCS entries are irrelevant */
-
-	THREAD_MONITOR_INIT(tcs);
+	thread_monitor_init(thread);
 }

arch/arc/core/thread_entry_wrapper.S

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -21,8 +11,6 @@
  * Wrapper for _thread_entry routine when called from the initial context.
  */
 
-#define _ASMLANGUAGE
-
 #include <toolchain.h>
 #include <sections.h>
 

arch/arc/core/timestamp.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2017 Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Time Stamp API for ARCv2
+ *
+ * Provide 64-bit time stamp API
+ */
+
+#include <kernel.h>
+#include <toolchain.h>
+#include <kernel_structs.h>
+
+extern int64_t _sys_clock_tick_count;
+extern int sys_clock_hw_cycles_per_tick;
+
+/*
+ * @brief Read 64-bit timestamp value
+ *
+ * This function returns a 64-bit bit time stamp value that is clocked
+ * at the same frequency as the CPU.
+ *
+ * @return 64-bit time stamp value
+ */
+uint64_t _tsc_read(void)
+{
+	unsigned int key;
+	uint64_t t;
+	uint32_t count;
+
+	key = irq_lock();
+	t = (uint64_t)_sys_clock_tick_count;
+	count = _arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT);
+	irq_unlock(key);
+	t *= (uint64_t)sys_clock_hw_cycles_per_tick;
+	t += (uint64_t)count;
+	return t;
+}

arch/arc/core/vector_table.c

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
@@ -75,4 +65,3 @@ struct vector_table _VectorTable _GENERIC_SECTION(.exc_vector_table) = {
 	0
 };
 
-extern struct vector_table __start _ALIAS_OF(_VectorTable);

arch/arc/defconfig

@@ -1,6 +1,5 @@
 CONFIG_ARC=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
-CONFIG_SOC_GENERIC_ARC=y
 CONFIG_CPU_ARCEM4=y
 CONFIG_CPU_ARCV2=y
 CONFIG_ARCV2_INTERRUPT_UNIT=y

arch/arc/include/kernel_arch_data.h

@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Private kernel definitions
+ *
+ * This file contains private kernel structures definitions and various
+ * other definitions for the ARCv2 processor architecture.
+ *
+ * This file is also included by assembly language files which must #define
+ * _ASMLANGUAGE before including this header file.  Note that kernel
+ * assembly source files obtains structure offset values via "absolute
+ * symbols" in the offsets.o module.
+ */
+
+#ifndef _kernel_arch_data__h_
+#define _kernel_arch_data__h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <toolchain.h>
+#include <sections.h>
+#include <arch/cpu.h>
+#include <vector_table.h>
+
+#ifndef _ASMLANGUAGE
+#include <kernel.h>
+#include <nano_internal.h>
+#include <stdint.h>
+#include <misc/util.h>
+#include <misc/dlist.h>
+#endif
+
+#ifndef _ASMLANGUAGE
+
+struct _caller_saved {
+	/*
+	 * Saved on the stack as part of handling a regular IRQ or by the
+	 * kernel when calling the FIRQ return code.
+	 */
+};
+
+typedef struct _caller_saved _caller_saved_t;
+
+struct _irq_stack_frame {
+	uint32_t r0;
+	uint32_t r1;
+	uint32_t r2;
+	uint32_t r3;
+	uint32_t r4;
+	uint32_t r5;
+	uint32_t r6;
+	uint32_t r7;
+	uint32_t r8;
+	uint32_t r9;
+	uint32_t r10;
+	uint32_t r11;
+	uint32_t r12;
+	uint32_t r13;
+	uint32_t blink;
+	uint32_t lp_end;
+	uint32_t lp_start;
+	uint32_t lp_count;
+#ifdef CONFIG_CODE_DENSITY
+	/*
+	 * Currently unsupported. This is where those registers are
+	 * automatically pushed on the stack by the CPU when taking a regular
+	 * IRQ.
+	 */
+	uint32_t ei_base;
+	uint32_t ldi_base;
+	uint32_t jli_base;
+#endif
+	uint32_t pc;
+	uint32_t status32;
+};
+
+typedef struct _irq_stack_frame _isf_t;
+
+struct _callee_saved {
+	uint32_t sp; /* r28 */
+};
+typedef struct _callee_saved _callee_saved_t;
+
+/* callee-saved registers pushed on the stack, not in k_thread */
+struct _callee_saved_stack {
+	uint32_t r13;
+	uint32_t r14;
+	uint32_t r15;
+	uint32_t r16;
+	uint32_t r17;
+	uint32_t r18;
+	uint32_t r19;
+	uint32_t r20;
+	uint32_t r21;
+	uint32_t r22;
+	uint32_t r23;
+	uint32_t r24;
+	uint32_t r25;
+	uint32_t r26;
+	uint32_t fp; /* r27 */
+	/* r28 is the stack pointer and saved separately */
+	/* r29 is ILINK and does not need to be saved */
+	uint32_t r30;
+	/*
+	 * No need to save r31 (blink), it's either alread pushed as the pc or
+	 * blink on an irq stack frame.
+	 */
+};
+
+typedef struct _callee_saved_stack _callee_saved_stack_t;
+
+#endif /* _ASMLANGUAGE */
+
+/* stacks */
+
+#define STACK_ALIGN_SIZE 4
+
+#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
+#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
+
+/*
+ * Reason a thread has relinquished control: fibers can only be in the NONE
+ * or COOP state, tasks can be one in the four.
+ */
+#define _CAUSE_NONE 0
+#define _CAUSE_COOP 1
+#define _CAUSE_RIRQ 2
+#define _CAUSE_FIRQ 3
+
+#ifndef _ASMLANGUAGE
+
+struct _thread_arch {
+
+	/* interrupt key when relinquishing control */
+	uint32_t intlock_key;
+
+	/* one of the _CAUSE_xxxx definitions above */
+	int relinquish_cause;
+
+	/* return value from _Swap */
+	unsigned int return_value;
+
+#ifdef CONFIG_ARC_STACK_CHECKING
+	/* top of stack for hardware stack checking */
+	uint32_t stack_top;
+#endif
+};
+
+typedef struct _thread_arch _thread_arch_t;
+
+struct _kernel_arch {
+
+	char *rirq_sp; /* regular IRQ stack pointer base */
+
+	/*
+	 * FIRQ stack pointer is installed once in the second bank's SP, so
+	 * there is no need to track it in _kernel.
+	 */
+
+};
+
+typedef struct _kernel_arch _kernel_arch_t;
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _kernel_arch_data__h_ */

arch/arc/include/kernel_arch_func.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Private kernel definitions
+ *
+ * This file contains private kernel structures definitions and various
+ * other definitions for the ARCv2 processor architecture.
+ *
+ * This file is also included by assembly language files which must #define
+ * _ASMLANGUAGE before including this header file.  Note that kernel
+ * assembly source files obtains structure offset values via "absolute
+ * symbols" in the offsets.o module.
+ */
+
+#ifndef _kernel_arch_func__h_
+#define _kernel_arch_func__h_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_ASMLANGUAGE)
+
+#ifdef CONFIG_CPU_ARCV2
+#include <v2/cache.h>
+#include <v2/irq.h>
+#endif
+
+static ALWAYS_INLINE void nanoArchInit(void)
+{
+	_irq_setup();
+}
+
+static ALWAYS_INLINE void
+_set_thread_return_value(struct k_thread *thread, unsigned int value)
+{
+	thread->arch.return_value = value;
+}
+
+static ALWAYS_INLINE int _is_in_isr(void)
+{
+	uint32_t act = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT);
+#if CONFIG_IRQ_OFFLOAD
+	/* Check if we're in a TRAP_S exception as well */
+	if (_arc_v2_aux_reg_read(_ARC_V2_STATUS32) & _ARC_V2_STATUS32_AE &&
+	    _ARC_V2_ECR_VECTOR(_arc_v2_aux_reg_read(_ARC_V2_ECR)) == EXC_EV_TRAP
+	   ) {
+		return 1;
+	}
+#endif
+	return ((act & 0xffff) != 0);
+}
+
+/**
+ *
+ * @bried Indicates the interrupt number of the highest priority
+ * active interrupt
+ *
+ * @return IRQ number
+ */
+static ALWAYS_INLINE int _INTERRUPT_CAUSE(void)
+{
+	uint32_t irq_num = _arc_v2_aux_reg_read(_ARC_V2_ICAUSE);
+
+	return irq_num;
+}
+
+
+extern void _thread_entry_wrapper(void);
+
+static inline void _IntLibInit(void)
+{
+	/* nothing needed, here because the kernel requires it */
+}
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _kernel_arch_func__h_ */

arch/arc/include/kernel_event_logger_arch.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Kernel event logger support for ARM
+ */
+
+#ifndef __KERNEL_EVENT_LOGGER_ARCH_H__
+#define __KERNEL_EVENT_LOGGER_ARCH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the identification of the current interrupt.
+ *
+ * This routine obtain the key of the interrupt that is currently processed
+ * if it is called from a ISR context.
+ *
+ * @return The key of the interrupt that is currently being processed.
+ */
+int _sys_current_irq_key_get(void)
+{
+	return _INTERRUPT_CAUSE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __KERNEL_EVENT_LOGGER_ARCH_H__ */

arch/arc/include/nano_private.h

@@ -1,295 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- * @file
- * @brief Private nanokernel definitions
- *
- * This file contains private nanokernel structures definitions and various
- * other definitions for the ARCv2 processor architecture.
- *
- * This file is also included by assembly language files which must #define
- * _ASMLANGUAGE before including this header file.  Note that nanokernel
- * assembly source files obtains structure offset values via "absolute
- * symbols" in the offsets.o module.
- */
-
-#ifndef _NANO_PRIVATE_H
-#define _NANO_PRIVATE_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <toolchain.h>
-#include <sections.h>
-#include <arch/cpu.h>
-#include <vector_table.h>
-
-#ifndef _ASMLANGUAGE
-#include <nanokernel.h>            /* public nanokernel API */
-#include <../../../kernel/nanokernel/include/nano_internal.h>
-#include <stdint.h>
-#include <misc/util.h>
-#include <misc/dlist.h>
-#endif
-
-#ifndef _ASMLANGUAGE
-
-#ifdef CONFIG_THREAD_MONITOR
-struct __thread_entry {
-	_thread_entry_t pEntry;
-	void *parameter1;
-	void *parameter2;
-	void *parameter3;
-};
-#endif /*CONFIG_THREAD_MONITOR*/
-
-struct coop {
-	/*
-	 * Saved on the stack as part of handling a regular IRQ or by the kernel
-	 * when calling the FIRQ return code.
-	 */
-};
-
-struct irq_stack_frame {
-	uint32_t r0;
-	uint32_t r1;
-	uint32_t r2;
-	uint32_t r3;
-	uint32_t r4;
-	uint32_t r5;
-	uint32_t r6;
-	uint32_t r7;
-	uint32_t r8;
-	uint32_t r9;
-	uint32_t r10;
-	uint32_t r11;
-	uint32_t r12;
-	uint32_t r13;
-	uint32_t blink;
-	uint32_t lp_end;
-	uint32_t lp_start;
-	uint32_t lp_count;
-#ifdef CONFIG_CODE_DENSITY
-	/*
-	 * Currently unsupported. This is where those registers are automatically
-	 * pushed on the stack by the CPU when taking a regular IRQ.
-	 */
-	uint32_t ei_base;
-	uint32_t ldi_base;
-	uint32_t jli_base;
-#endif
-	uint32_t pc;
-	uint32_t status32;
-};
-
-typedef struct irq_stack_frame tISF;
-
-struct preempt {
-	uint32_t sp; /* r28 */
-};
-typedef struct preempt tPreempt;
-
-struct callee_saved {
-	uint32_t r13;
-	uint32_t r14;
-	uint32_t r15;
-	uint32_t r16;
-	uint32_t r17;
-	uint32_t r18;
-	uint32_t r19;
-	uint32_t r20;
-	uint32_t r21;
-	uint32_t r22;
-	uint32_t r23;
-	uint32_t r24;
-	uint32_t r25;
-	uint32_t r26;
-	uint32_t fp; /* r27 */
-	/* r28 is the stack pointer and saved separately */
-	/* r29 is ILINK and does not need to be saved */
-	uint32_t r30;
-	/*
-	 * No need to save r31 (blink), it's either alread pushed as the pc or
-	 * blink on an irq stack frame.
-	 */
-};
-typedef struct callee_saved tCalleeSaved;
-
-/* registers saved by software when taking a FIRQ */
-struct firq_regs {
-	uint32_t lp_count;
-	uint32_t lp_start;
-	uint32_t lp_end;
-};
-typedef struct firq_regs tFirqRegs;
-
-#endif /* _ASMLANGUAGE */
-
-/* Bitmask definitions for the struct tcs->flags bit field */
-
-#define FIBER          0x000
-#define TASK           0x001 /* 1 = task, 0 = fiber   */
-
-#define INT_ACTIVE     0x002 /* 1 = execution context is interrupt handler */
-#define EXC_ACTIVE     0x004 /* 1 = executino context is exception handler */
-#define USE_FP         0x010 /* 1 = thread uses floating point unit */
-#define PREEMPTIBLE    0x020 /* 1 = preemptible thread */
-#define ESSENTIAL      0x200 /* 1 = system thread that must not abort */
-#define NO_METRICS     0x400 /* 1 = _Swap() not to update task metrics */
-
-/* stacks */
-
-#define STACK_ALIGN_SIZE 4
-
-#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
-#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
-
-/*
- * Reason a thread has relinquished control: fibers can only be in the NONE
- * or COOP state, tasks can be one in the four.
- */
-#define _CAUSE_NONE 0
-#define _CAUSE_COOP 1
-#define _CAUSE_RIRQ 2
-#define _CAUSE_FIRQ 3
-
-#ifndef _ASMLANGUAGE
-
-struct tcs {
-	struct tcs *link;         /* node in singly-linked list
-				   * _nanokernel.fibers
-				   */
-	uint32_t flags;           /* bitmask of flags above */
-	uint32_t intlock_key;     /* interrupt key when relinquishing control */
-	int relinquish_cause;     /* one of the _CAUSE_xxxx definitions above */
-	unsigned int return_value;/* return value from _Swap */
-	int prio;                 /* fiber priority, -1 for a task */
-#ifdef CONFIG_THREAD_CUSTOM_DATA
-	void *custom_data;        /* available for custom use */
-#endif
-	struct coop coopReg;
-	struct preempt preempReg;
-#ifdef CONFIG_THREAD_MONITOR
-	struct __thread_entry *entry; /* thread entry and parameters description */
-	struct tcs *next_thread;  /* next item in list of ALL fiber+tasks */
-#endif
-#ifdef CONFIG_NANO_TIMEOUTS
-	struct _nano_timeout nano_timeout;
-#endif
-#ifdef CONFIG_ERRNO
-	int errno_var;
-#endif
-#ifdef CONFIG_ARC_STACK_CHECKING
-	uint32_t stack_top;
-#endif
-};
-
-struct s_NANO {
-	struct tcs *fiber;    /* singly linked list of runnable fibers */
-	struct tcs *task;     /* current task the nanokernel knows about */
-	struct tcs *current;  /* currently scheduled thread (fiber or task) */
-
-#ifdef CONFIG_THREAD_MONITOR
-	struct tcs *threads; /* singly linked list of ALL fiber+tasks */
-#endif
-
-#ifdef CONFIG_FP_SHARING
-	struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */
-#endif
-
-#ifdef CONFIG_SYS_POWER_MANAGEMENT
-	int32_t idle; /* Number of ticks for kernel idling */
-#endif
-
-	char *rirq_sp; /* regular IRQ stack pointer base */
-
-	/*
-	 * FIRQ stack pointer is installed once in the second bank's SP, so
-	 * there is no need to track it in _nanokernel.
-	 */
-
-	struct firq_regs firq_regs;
-#if defined(CONFIG_NANO_TIMEOUTS) || defined(CONFIG_NANO_TIMERS)
-	sys_dlist_t timeout_q;
-	int32_t task_timeout;
-#endif
-};
-
-typedef struct s_NANO tNANO;
-extern tNANO _nanokernel;
-
-#ifdef CONFIG_CPU_ARCV2
-#include <v2/cache.h>
-#include <v2/irq.h>
-#endif
-
-static ALWAYS_INLINE void nanoArchInit(void)
-{
-	_icache_setup();
-	_irq_setup();
-}
-
-/**
- *
- * @brief Set the return value for the specified fiber (inline)
- *
- * The register used to store the return value from a function call invocation
- * to <value>.  It is assumed that the specified <fiber> is pending, and thus
- * the fiber's thread is stored in its struct tcs structure.
- *
- * @return N/A
- */
-static ALWAYS_INLINE void fiberRtnValueSet(struct tcs *fiber, unsigned int value)
-{
-	fiber->return_value = value;
-}
-
-/**
- *
- * @brief Indicates if kernel is handling interrupt
- *
- * @return 1 if interrupt handler is executed, 0 otherwise
- */
-static ALWAYS_INLINE int _IS_IN_ISR(void)
-{
-	uint32_t act = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_ACT);
-#if CONFIG_IRQ_OFFLOAD
-	/* Check if we're in a TRAP_S exception as well */
-	if (_arc_v2_aux_reg_read(_ARC_V2_STATUS32) & _ARC_V2_STATUS32_AE &&
-	    _ARC_V2_ECR_VECTOR(_arc_v2_aux_reg_read(_ARC_V2_ECR)) == EXC_EV_TRAP) {
-		return 1;
-	}
-#endif
-	return ((act & 0xffff) != 0);
-}
-
-extern void nanoCpuAtomicIdle(unsigned int);
-extern void _thread_entry_wrapper(void);
-
-static inline void _IntLibInit(void)
-{
-	/* nothing needed, here because the kernel requires it */
-}
-
-#endif /* _ASMLANGUAGE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NANO_PRIVATE_H */

arch/arc/include/offsets_short_arch.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _offsets_short_arch__h_
+#define _offsets_short_arch__h_
+
+#include <offsets.h>
+
+/* kernel */
+
+/* nothing for now */
+
+/* end - kernel */
+
+/* threads */
+
+#define _thread_offset_to_intlock_key \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_intlock_key_OFFSET)
+
+#define _thread_offset_to_relinquish_cause \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_relinquish_cause_OFFSET)
+
+#define _thread_offset_to_return_value \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_return_value_OFFSET)
+
+#define _thread_offset_to_stack_top \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_stack_top_OFFSET)
+
+#define _thread_offset_to_sp \
+	(___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET)
+
+
+/* end - threads */
+
+#endif /* _offsets_short_arch__h_ */

arch/arc/include/swap_macros.h

@@ -0,0 +1,165 @@
+/* swap_macros.h - helper macros for context switch */
+
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SWAP_MACROS__H_
+#define _SWAP_MACROS__H_
+
+#include <kernel_structs.h>
+#include <offsets_short.h>
+#include <toolchain.h>
+#include <arch/cpu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef _ASMLANGUAGE
+
+/* entering this macro, current is in r2 */
+.macro _save_callee_saved_regs
+
+	sub_s sp, sp, ___callee_saved_stack_t_SIZEOF
+
+	/* save regs on stack */
+	st_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
+	st_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
+	st_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
+	st r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
+	st r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
+	st r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
+	st r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
+	st r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
+	st r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
+	st r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
+	st r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
+	st r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
+	st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
+	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
+	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
+
+	/* save stack pointer in struct tcs */
+	st sp, [r2, _thread_offset_to_sp]
+.endm
+
+/* entering this macro, current is in r2 */
+.macro _load_callee_saved_regs
+	/* restore stack pointer from struct tcs */
+	ld sp, [r2, _thread_offset_to_sp]
+
+	ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
+	ld_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
+	ld_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
+	ld r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
+	ld r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
+	ld r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
+	ld r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
+	ld r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
+	ld r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
+	ld r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
+	ld r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
+	ld r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
+	ld r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
+	ld r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
+	ld fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
+
+	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
+
+.endm
+
+.macro _discard_callee_saved_regs
+	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
+.endm
+
+/*
+ * Must be called with interrupts locked or in P0.
+ * Upon exit, sp will be pointing to the stack frame.
+ */
+.macro _create_irq_stack_frame
+
+	sub_s sp, sp, ___isf_t_SIZEOF
+
+	st blink, [sp, ___isf_t_blink_OFFSET]
+
+	/* store these right away so we can use them if needed */
+
+	st_s r13, [sp, ___isf_t_r13_OFFSET]
+	st_s r12, [sp, ___isf_t_r12_OFFSET]
+	st   r11, [sp, ___isf_t_r11_OFFSET]
+	st   r10, [sp, ___isf_t_r10_OFFSET]
+	st   r9,  [sp, ___isf_t_r9_OFFSET]
+	st   r8,  [sp, ___isf_t_r8_OFFSET]
+	st   r7,  [sp, ___isf_t_r7_OFFSET]
+	st   r6,  [sp, ___isf_t_r6_OFFSET]
+	st   r5,  [sp, ___isf_t_r5_OFFSET]
+	st   r4,  [sp, ___isf_t_r4_OFFSET]
+	st_s r3,  [sp, ___isf_t_r3_OFFSET]
+	st_s r2,  [sp, ___isf_t_r2_OFFSET]
+	st_s r1,  [sp, ___isf_t_r1_OFFSET]
+	st_s r0,  [sp, ___isf_t_r0_OFFSET]
+
+	mov r0, lp_count
+	st_s r0, [sp, ___isf_t_lp_count_OFFSET]
+	lr r1, [_ARC_V2_LP_START]
+	lr r0, [_ARC_V2_LP_END]
+	st_s r1, [sp, ___isf_t_lp_start_OFFSET]
+	st_s r0, [sp, ___isf_t_lp_end_OFFSET]
+
+.endm
+
+/*
+ * Must be called with interrupts locked or in P0.
+ * sp must be pointing the to stack frame.
+ */
+.macro _pop_irq_stack_frame
+
+	ld blink, [sp, ___isf_t_blink_OFFSET]
+
+	ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
+	mov lp_count, r0
+	ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
+	ld_s r0, [sp, ___isf_t_lp_end_OFFSET]
+	sr r1, [_ARC_V2_LP_START]
+	sr r0, [_ARC_V2_LP_END]
+
+	ld_s r13, [sp, ___isf_t_r13_OFFSET]
+	ld_s r12, [sp, ___isf_t_r12_OFFSET]
+	ld   r11, [sp, ___isf_t_r11_OFFSET]
+	ld   r10, [sp, ___isf_t_r10_OFFSET]
+	ld   r9,  [sp, ___isf_t_r9_OFFSET]
+	ld   r8,  [sp, ___isf_t_r8_OFFSET]
+	ld   r7,  [sp, ___isf_t_r7_OFFSET]
+	ld   r6,  [sp, ___isf_t_r6_OFFSET]
+	ld   r5,  [sp, ___isf_t_r5_OFFSET]
+	ld   r4,  [sp, ___isf_t_r4_OFFSET]
+	ld_s r3,  [sp, ___isf_t_r3_OFFSET]
+	ld_s r2,  [sp, ___isf_t_r2_OFFSET]
+	ld_s r1,  [sp, ___isf_t_r1_OFFSET]
+	ld_s r0,  [sp, ___isf_t_r0_OFFSET]
+
+	/*
+	 * All gprs have been reloaded, the only one that is still usable is
+	 * ilink.
+	 *
+	 * The pc and status32 values will still be on the stack. We cannot
+	 * pop them yet because the callers of _pop_irq_stack_frame must reload
+	 * status32 differently depending on the execution context they are
+	 * running in (_Swap(), firq or exception).
+	 */
+	add_s sp, sp, ___isf_t_SIZEOF
+
+.endm
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*  _SWAP_MACROS__H_ */

arch/arc/include/v2/cache.h

@@ -1,25 +1,15 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
- * @brief Cache helper functions (ARC)
+ * @brief Cache helper functions and defines (ARC)
  *
- * This file contains private nanokernel structures definitions and various
- * other definitions for the ARCv2 processor architecture.
+ * This file contains cache related functions and definitions for the
+ * ARCv2 processor architecture.
  */
 
 #ifndef _ARCV2_CACHE__H_
@@ -33,23 +23,31 @@ extern "C" {
 
 #ifndef _ASMLANGUAGE
 
-#define CACHE_ENABLE 0x00
-#define CACHE_DISABLE 0x01
-#define CACHE_DIRECT 0x00
-#define CACHE_CACHE_CONTROLLED 0x20
+/* i-cache defines for IC_CTRL register */
+#define IC_CACHE_ENABLE   0x00
+#define IC_CACHE_DISABLE  0x01
+#define IC_CACHE_DIRECT   0x00
+#define IC_CACHE_INDIRECT 0x20
 
 /*
- * @brief Sets the I-cache
+ * @brief Initialize the I-cache
  *
- * Enables cache and sets the direct access.
+ * Enables the i-cache and sets it to direct access mode.
  */
 static ALWAYS_INLINE void _icache_setup(void)
 {
 	uint32_t icache_config = (
-		CACHE_DIRECT | /* direct mapping (one-way assoc.) */
-		CACHE_ENABLE   /* i-cache enabled */
+		IC_CACHE_DIRECT | /* direct mapping (one-way assoc.) */
+		IC_CACHE_ENABLE   /* i-cache enabled */
 	);
-	_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+	uint32_t val;
+
+	val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
+	val &= 0xff;
+	if (val != 0) { /* is i-cache present? */
+		/* configure i-cache */
+		_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
+	}
 }
 
 #endif /* _ASMLANGUAGE */

arch/arc/include/v2/irq.h

@@ -1,24 +1,14 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
  * @brief Interrupt helper functions (ARC)
  *
- * This file contains private nanokernel structures definitions and various
+ * This file contains private kernel structures definitions and various
  * other definitions for the ARCv2 processor architecture.
  */
 
@@ -31,12 +21,13 @@ extern "C" {
 
 #define _ARC_V2_AUX_IRQ_CTRL_BLINK (1 << 9)
 #define _ARC_V2_AUX_IRQ_CTRL_LOOP_REGS (1 << 10)
+#define _ARC_V2_AUX_IRQ_CTRL_LP (1 << 13)
 #define _ARC_V2_AUX_IRQ_CTRL_14_REGS 7
 #define _ARC_V2_AUX_IRQ_CTRL_16_REGS 8
 #define _ARC_V2_AUX_IRQ_CTRL_32_REGS 16
 
-#define _ARC_V2_DEF_IRQ_LEVEL 15
-#define _ARC_V2_WAKE_IRQ_LEVEL 15
+#define _ARC_V2_DEF_IRQ_LEVEL (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
+#define _ARC_V2_WAKE_IRQ_LEVEL _ARC_V2_DEF_IRQ_LEVEL
 
 #ifndef _ASMLANGUAGE
 
@@ -56,10 +47,10 @@ static ALWAYS_INLINE void _irq_setup(void)
 		_ARC_V2_AUX_IRQ_CTRL_14_REGS     /* save r0 -> r13 (caller-saved) */
 	);
 
-	nano_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
+	k_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
 	_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_CTRL, aux_irq_ctrl_value);
 
-	_nanokernel.rirq_sp = _interrupt_stack + CONFIG_ISR_STACK_SIZE;
+	_kernel.irq_stack = _interrupt_stack + CONFIG_ISR_STACK_SIZE;
 	_firq_stack_setup();
 }
 

arch/arc/include/vector_table.h

@@ -1,17 +1,7 @@
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 /**

arch/arc/soc/em11d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em11d/Kconfig.defconfig

@@ -0,0 +1,249 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EM11D
+
+config SOC
+	default em11d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em11d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x10000000
+
+config SRAM_SIZE
+	default 131072
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 64
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 64
+
+config CACHE_FLUSHING
+	def_bool y
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM11D

arch/arc/soc/em11d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM11D
+	bool "Synopsys ARC EM11D"

arch/arc/soc/em11d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mcpu=arcem) \
+                   $(call cc-option,-mno-sdata)

arch/arc/soc/em11d/linker.ld

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM11D platform.
+ */
+
+/*
+ * DRAM base address and size
+ *
+ * DRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
+/* TODO: Using SRAM config for now, even though this is really DRAM. */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/em11d/soc.c

@@ -0,0 +1,14 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ *
+ * Nothing to be done for now.
+ */

arch/arc/soc/em11d/soc.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+#define SPI_DW_IRQ_FLAGS     0
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS					0 /* Default */
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em11d/soc_config.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em7d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em7d/Kconfig.defconfig

@@ -0,0 +1,249 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EM7D
+
+config SOC
+	default em7d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 30000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em7d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x10000000
+
+config SRAM_SIZE
+	default 131072
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 256
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 128
+
+config CACHE_FLUSHING
+	def_bool y
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM7D

arch/arc/soc/em7d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM7D
+	bool "Synopsys ARC EM7D"

arch/arc/soc/em7d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mcpu=arcem) \
+                   $(call cc-option,-mno-sdata)

arch/arc/soc/em7d/linker.ld

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM7D platform.
+ */
+
+/*
+ * DRAM base address and size
+ *
+ * DRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
+/* TODO: Using SRAM config for now, even though this is really DRAM. */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/em7d/soc.c

@@ -0,0 +1,14 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ *
+ * Nothing to be done for now.
+ */

arch/arc/soc/em7d/soc.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+#define SPI_DW_IRQ_FLAGS     0
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS					0 /* Default */
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em7d/soc_config.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/em9d/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/arch/arc/soc/
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o

arch/arc/soc/em9d/Kconfig.defconfig

@@ -0,0 +1,247 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_EM9D
+
+config SOC
+	default em9d
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	# TODO: But regular irq nesting is not implemented --
+	# so this must be 2 for now.
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 36
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	def_bool y
+
+config FLASH_BASE_ADDRESS
+	default 0x00000000
+
+config FLASH_SIZE
+	default 0
+	# em9d has no FLASH so size is 0.
+
+config SRAM_BASE_ADDRESS
+	default 0x00000000
+
+config SRAM_SIZE
+	default 0
+	# em9d has no SRAM so size is 0.
+
+config ICCM_BASE_ADDRESS
+	default 0x00000000
+
+config ICCM_SIZE
+	default 256
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 128
+
+if GPIO
+
+config GPIO_DW
+	def_bool y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	def_bool y
+
+if GPIO_DW_0
+
+config GPIO_DW_0_NAME
+	default "GPIO_PORTA"
+
+config GPIO_DW_0_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_0
+
+config GPIO_DW_1
+	def_bool y
+
+if GPIO_DW_1
+
+config GPIO_DW_1_NAME
+	default "GPIO_PORTB"
+
+config GPIO_DW_1_IRQ_PRI
+	default 1
+
+endif # GPIO_DW_1
+
+config GPIO_DW_2
+	def_bool y
+
+if GPIO_DW_2
+
+config GPIO_DW_2_IRQ_PRI
+	default 1
+
+config GPIO_DW_2_NAME
+	default "GPIO_PORTC"
+
+endif # GPIO_DW_2
+
+config GPIO_DW_3
+	def_bool y
+
+if GPIO_DW_3
+
+config GPIO_DW_3_IRQ_PRI
+	default 1
+
+config GPIO_DW_3_NAME
+	default "GPIO_PORTD"
+
+endif # GPIO_DW_3
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if I2C
+
+config I2C_CLOCK_SPEED
+	default 100
+
+config I2C_DW
+	def_bool y
+
+if I2C_DW
+
+config I2C_0
+	def_bool y
+
+if I2C_0
+
+config I2C_0_NAME
+	default "I2C_0"
+config I2C_0_DEFAULT_CFG
+	default 0x3
+config I2C_0_IRQ_PRI
+	default 1
+
+endif # I2C_0
+
+config I2C_1
+	def_bool y
+
+if I2C_1
+
+config I2C_1_NAME
+	default "I2C_1"
+config I2C_1_DEFAULT_CFG
+	default 0x3
+config I2C_1_IRQ_PRI
+	default 1
+
+endif # I2C_1
+
+endif # I2C_DW
+
+endif # I2C
+
+if UART_NS16550
+
+config UART_NS16550_PORT_0
+	def_bool n
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_NAME
+	default "UART_0"
+config UART_NS16550_PORT_0_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_0_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_NAME
+	default "UART_1"
+config UART_NS16550_PORT_1_IRQ_PRI
+	default 1
+config UART_NS16550_PORT_1_BAUD_RATE
+	default 115200
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_DW
+	def_bool y
+
+if SPI_DW
+
+config SPI_DW_CLOCK_GATE
+	def_bool n
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	def_bool n
+
+config SPI_0
+	def_bool y
+
+if SPI_0
+
+config SPI_0_IRQ_PRI
+	default 0
+
+endif # SPI_0
+
+config SPI_1
+	def_bool y
+
+if SPI_1
+
+config SPI_1_IRQ_PRI
+	default 0
+
+endif # SPI_1
+
+endif # SPI_DW
+
+endif # SPI
+
+endif #SOC_EM9D

arch/arc/soc/em9d/Kconfig.soc

@@ -0,0 +1,3 @@
+
+config SOC_EM9D
+	bool "Synopsys ARC EM9D"

arch/arc/soc/em9d/Makefile

@@ -0,0 +1,2 @@
+soc-cflags = $(call cc-option,-mcpu=arcem) \
+                  $(call cc-option,-mno-sdata)

arch/arc/soc/em9d/linker.ld

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit v2.2 EM9D platform.
+ */
+
+/*
+ * ICCM base address and size
+ *
+ * ICCM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#define ICCM_START		CONFIG_ICCM_BASE_ADDRESS
+#define ICCM_SIZE		CONFIG_ICCM_SIZE
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker.ld>
+

arch/arc/soc/em9d/soc.c

@@ -0,0 +1,14 @@
+/* soc.c - system/hardware module for em_starterkit BSP */
+
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the ARC EM Starter kit board.
+ *
+ * Nothing to be done for now.
+ */

arch/arc/soc/em9d/soc.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Board configuration macros for EM Starter kit board
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the target.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
+
+
+/* IRQs */
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+
+#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
+#define CONFIG_ARCV2_TIMER0_INT_PRI 0
+
+#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/* I2C */
+
+/* I2C_0 is on Pmod2 connector */
+#define I2C_DW_0_BASE_ADDR                      0xF0004000
+#define I2C_DW_0_IRQ                            23
+
+
+/* I2C_1 is on Pmod4 connector */
+#define I2C_DW_1_BASE_ADDR                      0xF0005000
+#define I2C_DW_1_IRQ                            24
+
+#define I2C_DW_IRQ_FLAGS			0
+
+/* GPIO */
+#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ                           22
+#define GPIO_DW_0_BITS                          32
+#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
+
+#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_2_BITS                          32
+#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+
+#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
+#define GPIO_DW_3_BITS                          12
+#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+
+/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
+/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
+/* undef CONFIG_GPIO_DW_CLOCK_GATE */
+/* undef CONFIG_SOC_QUARK_SE_C1000_SS */
+
+/* SPI */
+
+#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+
+#define SPI_DW_PORT_0_REGS   0xF0006000
+#define SPI_DW_PORT_1_REGS   0xF0007000
+
+#define SPI_DW_PORT_0_IRQ    25
+#define SPI_DW_PORT_1_IRQ    26
+
+#define SPI_DW_IRQ_FLAGS     0
+
+/*
+ * SPI Chip Select Assignments on EM Starter Kit
+ *
+ *  CS0   Pmod6 - pin 1 - J6
+ *  CS1   Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
+ *  CS2   Pmod6 - pin 8 - J6
+ *  CS3   SDCard (onboard)
+ *  CS4   Internal SPI Slave - loopback
+ *  CS5   SPI-Flash (onboard)
+ */
+
+/*
+ * UART
+     UART0 vector 27 0xF0008000
+     UART1 vector 28 0xF0009000
+     UART2 vector 29 0xF000A000
+ */
+#define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
+#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
+#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
+#define UART_IRQ_FLAGS					0 /* Default */
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/em9d/soc_config.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
+	sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_c1000_ss/Kbuild

@@ -0,0 +1,8 @@
+ccflags-y +=-I$(srctree)/include
+ccflags-y +=-I$(srctree)/include/drivers
+ccflags-y +=-I$(srctree)/drivers
+ccflags-$(CONFIG_ADC) +=-I$(srctree)/drivers/adc
+
+asflags-y := ${ccflags-y}
+
+obj-y = soc.o soc_config.o soc_power.o power.o

arch/arc/soc/quark_se_c1000_ss/Kconfig

@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if ARC && SOC_QUARK_SE_C1000_SS
+
+if IPM
+config QUARK_SE_SS_IPM_IRQ_PRI
+	int "IPM interrupt priority"
+	default 1
+	help
+	Priority level for interrupts coming in from the inter-processor
+	mailboxes.
+
+endif # IPM
+endif # SOC_QUARK_SE_C1000_SS

arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig

@@ -0,0 +1,365 @@
+#
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2015-2016 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_QUARK_SE_C1000_SS
+
+config SOC
+	default quark_se_c1000_ss
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports only 2 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 68
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32000000
+
+config HARVARD
+	def_bool n
+
+config FLASH_BASE_ADDRESS
+	default 0x40000000
+
+config FLASH_SIZE
+	default 152
+
+config SRAM_BASE_ADDRESS
+	default 0x4000 if NSIM
+	default 0xa8000400
+
+config SRAM_SIZE
+	default 16 if NSIM
+	default 24
+
+config ICCM_BASE_ADDRESS
+	default 0xFFFFFFFF
+
+config ICCM_SIZE
+	default 0
+
+config DCCM_BASE_ADDRESS
+	default 0x80000000
+
+config DCCM_SIZE
+	default 8
+
+config QMSI
+	def_bool y
+
+config QMSI_BUILTIN
+	def_bool y
+
+if RTC
+
+config RTC_QMSI
+	def_bool y
+
+config RTC_0_IRQ_PRI
+	default 2
+
+endif # RTC
+
+if PWM
+config PWM_QMSI
+	def_bool y
+endif # PWM
+
+if PINMUX
+config PINMUX_QMSI
+	def_bool y
+endif
+
+if GPIO
+
+config GPIO_QMSI
+	def_bool y
+
+if GPIO_QMSI
+
+config GPIO_QMSI_0
+	def_bool y
+
+if GPIO_QMSI_0
+
+config GPIO_QMSI_0_NAME
+	default "GPIO_2"
+
+config GPIO_QMSI_0_IRQ_PRI
+	default 1
+
+endif # GPIO_QMSI_0
+
+config GPIO_QMSI_1
+	def_bool y
+
+if GPIO_QMSI_1
+
+config GPIO_QMSI_1_NAME
+	default "GPIO_3"
+
+config GPIO_QMSI_1_IRQ_PRI
+	default 1
+
+endif # GPIO_QMSI_1
+
+endif # GPIO_QMSI
+
+config GPIO_QMSI_SS
+	def_bool y
+
+if GPIO_QMSI_SS
+
+config GPIO_QMSI_SS_0
+	def_bool y
+
+if GPIO_QMSI_SS_0
+
+config GPIO_QMSI_SS_0_NAME
+	default "GPIO_0"
+
+config GPIO_QMSI_SS_0_IRQ_PRI
+	default 1
+
+endif # GPIO_QMSI_SS_0
+
+config GPIO_QMSI_SS_1
+	def_bool y
+
+if GPIO_QMSI_SS_1
+
+config GPIO_QMSI_SS_1_NAME
+	default "GPIO_1"
+
+config GPIO_QMSI_SS_1_IRQ_PRI
+	default 1
+
+endif # GPIO_QMSI_SS_1
+
+endif # GPIO_QMSI_SS
+
+endif # GPIO
+
+
+if I2C
+
+config I2C_QMSI
+	def_bool n
+
+if I2C_QMSI
+config I2C_0
+	def_bool y
+
+config I2C_0_NAME
+	default "I2C_2"
+
+config I2C_0_IRQ_PRI
+	default 1
+
+config I2C_0_DEFAULT_CFG
+	default 0x12
+
+config I2C_1
+	def_bool y
+
+config I2C_1_NAME
+	default "I2C_3"
+
+config I2C_1_IRQ_PRI
+	default 1
+
+config I2C_1_DEFAULT_CFG
+	default 0x12
+
+config I2C_SDA_SETUP
+	default 2
+
+config I2C_SDA_TX_HOLD
+	default 16
+
+config I2C_SDA_RX_HOLD
+	default 24
+
+endif
+
+config I2C_QMSI_SS
+	def_bool y
+
+if I2C_QMSI_SS
+config I2C_SS_0
+	def_bool y
+
+config I2C_SS_0_NAME
+	default "I2C_0"
+
+config I2C_SS_0_DEFAULT_CFG
+	default 0x12
+
+config I2C_SS_1
+	def_bool y
+
+config I2C_SS_1_NAME
+	default "I2C_1"
+
+config I2C_SS_1_DEFAULT_CFG
+	default 0x12
+
+config I2C_SS_SDA_SETUP
+	default 2
+
+config I2C_SS_SDA_HOLD
+	default 10
+
+endif
+
+endif # I2C
+
+if ADC
+config ADC_QMSI_SS
+	def_bool y
+endif
+
+if BLUETOOTH_H4
+
+config BLUETOOTH_UART_ON_DEV_NAME
+	default UART_QMSI_0_NAME
+
+config UART_QMSI_0
+	def_bool y
+
+config UART_QMSI_0_BAUDRATE
+	default 1000000
+
+config UART_QMSI_0_HW_FC
+	def_bool y
+
+endif # BLUETOOTH_H4
+
+if UART_QMSI
+
+if UART_QMSI_0
+
+config UART_QMSI_0_IRQ_PRI
+	default 3
+
+endif # UART_QMSI_0
+
+config UART_QMSI_1
+	def_bool y
+
+if UART_QMSI_1
+
+config UART_QMSI_1_IRQ_PRI
+	default 3
+
+endif # UART_QMSI_1
+
+endif # UART_QMSI
+
+if UART_CONSOLE
+
+config UART_CONSOLE_ON_DEV_NAME
+	default "UART_1"
+
+endif
+
+if SPI
+
+config SPI_QMSI
+	def_bool n
+
+if SPI_QMSI
+config SPI_0
+	def_bool y
+
+config SPI_0_NAME
+	default "SPI_2"
+
+config SPI_0_IRQ_PRI
+	default 1
+
+config SPI_1
+	def_bool y
+
+config SPI_1_NAME
+	default "SPI_3"
+
+config SPI_1_IRQ_PRI
+	default 1
+
+endif
+
+config SPI_QMSI_SS
+	def_bool y
+
+if SPI_QMSI_SS
+config SPI_SS_0
+	def_bool y
+
+config SPI_SS_0_NAME
+	default "SPI_0"
+
+config SPI_SS_0_IRQ_PRI
+	default 1
+
+config SPI_SS_1
+	def_bool y
+
+config SPI_SS_1_NAME
+	default "SPI_1"
+
+config SPI_SS_1_IRQ_PRI
+	default 1
+
+endif
+
+endif # SPI
+
+if AIO_COMPARATOR
+
+config AIO_COMPARATOR_QMSI
+	def_bool y
+
+endif # AIO_COMPARATOR
+
+if WATCHDOG
+
+config WDT_QMSI
+	def_bool y
+
+config WDT_0_IRQ_PRI
+	default 2
+
+endif # WATCHDOG
+
+if DMA
+
+config DMA_QMSI
+	def_bool y
+
+endif # DMA
+
+if COUNTER
+
+config AON_COUNTER_QMSI
+	def_bool y
+
+config AON_TIMER_QMSI
+	def_bool y
+
+config AON_TIMER_IRQ_PRI
+	default 2
+
+endif # COUNTER
+
+endif #SOC_QUARK_SE_C1000_SS

arch/arc/soc/quark_se_c1000_ss/Kconfig.soc

@@ -0,0 +1,6 @@
+
+config SOC_QUARK_SE_C1000_SS
+	bool "Intel Quark SE C1000- Sensor Sub System"
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select SYS_POWER_DEEP_SLEEP_SUPPORTED
+	select HAS_QMSI

arch/arc/soc/quark_se_c1000_ss/Makefile

@@ -0,0 +1,10 @@
+soc-cflags = $(call cc-option,-mcpu=quarkse_em) \
+             $(call cc-option,-mno-sdata)
+
+soc-aflags = $(soc-cflags)
+soc-cxxflags = $(soc-cflags)
+soc-cflags += -DQM_SENSOR=1
+soc-cflags += -I$(srctree)/arch/x86/soc/intel_quark
+
+## FIXME
+SOC_SERIES = quark_se

arch/arc/soc/quark_se_c1000_ss/linker.ld

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2014-2015 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Quark SE platform, both standard images and XIP
+ * images.
+ */
+
+/* Flash base address and size */
+#define FLASH_START     CONFIG_FLASH_BASE_ADDRESS  /* Flash bank 1 */
+#define FLASH_SIZE      CONFIG_FLASH_SIZE
+
+/*
+ * SRAM base address and size
+ *
+ * Internal SRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#define SRAM_START		CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE		CONFIG_SRAM_SIZE
+
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#define DCCM_START		CONFIG_DCCM_BASE_ADDRESS
+#define DCCM_SIZE		CONFIG_DCCM_SIZE
+
+#include <arch/arc/v2/linker.ld>

arch/arc/soc/quark_se_c1000_ss/power.c

@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+#include <sys_io.h>
+#include <misc/__assert.h>
+#include <power.h>
+#include <soc_power.h>
+#include <init.h>
+#include <kernel_structs.h>
+#include <soc.h>
+
+#include "power_states.h"
+#include "ss_power_states.h"
+#include "vreg.h"
+
+#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
+extern void _power_soc_sleep(void);
+extern void _power_soc_deep_sleep(void);
+extern void _power_soc_deep_sleep_2(void);
+
+static void _deep_sleep(enum power_states state)
+{
+	qm_power_soc_set_ss_restore_flag();
+
+	switch (state) {
+	case SYS_POWER_STATE_DEEP_SLEEP_1:
+		_power_soc_sleep();
+		break;
+	case SYS_POWER_STATE_DEEP_SLEEP:
+		_power_soc_deep_sleep();
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
+void _sys_soc_set_power_state(enum power_states state)
+{
+	switch (state) {
+	case SYS_POWER_STATE_CPU_LPS:
+		qm_ss_power_soc_lpss_enable();
+		qm_ss_power_cpu_ss2();
+		break;
+	case SYS_POWER_STATE_CPU_LPS_1:
+		qm_ss_power_cpu_ss2();
+		break;
+	case SYS_POWER_STATE_CPU_LPS_2:
+		qm_ss_power_cpu_ss1(QM_SS_POWER_CPU_SS1_TIMER_ON);
+		break;
+#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
+	case SYS_POWER_STATE_DEEP_SLEEP:
+	case SYS_POWER_STATE_DEEP_SLEEP_1:
+		_deep_sleep(state);
+		break;
+	case SYS_POWER_STATE_DEEP_SLEEP_2:
+		qm_ss_power_soc_lpss_enable();
+		qm_power_soc_set_ss_restore_flag();
+		_power_soc_deep_sleep_2();
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+void _sys_soc_power_state_post_ops(enum power_states state)
+{
+	uint32_t limit;
+
+	switch (state) {
+	case SYS_POWER_STATE_CPU_LPS:
+		qm_ss_power_soc_lpss_disable();
+	case SYS_POWER_STATE_CPU_LPS_1:
+		/* Expire the timer as it is disabled in SS2. */
+		limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
+		_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
+		break;
+	case SYS_POWER_STATE_DEEP_SLEEP:
+	case SYS_POWER_STATE_DEEP_SLEEP_1:
+		__builtin_arc_seti(0);
+		break;
+	case SYS_POWER_STATE_DEEP_SLEEP_2:
+		qm_ss_power_soc_lpss_disable();
+
+		/* If flag is cleared it means the system entered in
+		 * sleep state while we were in LPS. In that case, we
+		 * must set ARC_READY flag so x86 core can continue
+		 * its execution.
+		 */
+		if ((QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY) == 0) {
+			_quark_se_ss_ready();
+			__builtin_arc_seti(0);
+		} else {
+			QM_SCSS_GP->gp0 &= ~GP0_BIT_SLEEP_READY;
+			QM_SCSS_GP->gps0 &= ~QM_GPS0_BIT_SENSOR_WAKEUP;
+		}
+		break;
+	default:
+		break;
+	}
+}

arch/arc/soc/quark_se_c1000_ss/soc.c

@@ -0,0 +1,32 @@
+/* system.c - system/hardware module for quark_se_ss BSP */
+
+/*
+ * Copyright (c) 2014-2015 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * This module provides routines to initialize and support board-level hardware
+ * for the Quark SE platform.
+ */
+
+#include <kernel.h>
+#include "soc.h"
+#include <init.h>
+
+/**
+ * @brief perform basic hardware initialization
+ *
+ * RETURNS: N/A
+ */
+static int quark_se_arc_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	_quark_se_ss_ready();
+
+	return 0;
+}
+
+SYS_INIT(quark_se_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/arc/soc/quark_se_c1000_ss/soc.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2014-2015 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Board configuration macros for Quark SE Sensor Subsystem
+ *
+ * This header file is used to specify and describe board-level
+ * aspects for the Quark SE Sensor Subsystem.
+ */
+
+#ifndef _BOARD__H_
+#define _BOARD__H_
+
+#include <misc/util.h>
+
+/* default system clock */
+
+#define SYSCLK_DEFAULT_IOSC_HZ MHZ(32)
+
+/* address bases */
+
+#define SCSS_REGISTER_BASE 0xB0800000 /*Sensor Subsystem Base*/
+
+#define PERIPH_ADDR_BASE_ADC 0x80015000 /* ADC */
+
+#define PERIPH_ADDR_BASE_CREG_MST0 0x80018000 /* CREG Master 0 */
+#define PERIPH_ADDR_BASE_CREG_SLV0 0x80018080 /* CREG Slave 0 */
+#define PERIPH_ADDR_BASE_CREG_SLV1 0x80018180 /* CREG Slave 1 */
+
+#define PERIPH_ADDR_BASE_GPIO0 0x80017800 /* GPIO 0 */
+#define PERIPH_ADDR_BASE_GPIO1 0x80017900 /* GPIO 1 */
+
+#define PERIPH_ADDR_BASE_SPI_MST0 0x80010000 /* SPI Master 0 */
+#define PERIPH_ADDR_BASE_SPI_MST1 0x80010100 /* SPI Master 1 */
+
+/* IRQs */
+
+/* The CPU-visible IRQ numbers change between the ARC and IA cores,
+ * and QMSI itself has no easy way to pick the correct one, though it
+ * does have the necessary information to do it ourselves (in the meantime).
+ * This macro will be used by the shim drivers to get the IRQ number to
+ * use, and it should always be called using the QM_IRQ_*_INT macro
+ * provided by QMSI.
+ */
+#define IRQ_GET_NUMBER(_irq) _irq##_VECTOR
+
+#define IRQ_TIMER0 16
+#define IRQ_TIMER1 17
+#define IRQ_I2C0_RX_AVAIL 18
+#define IRQ_I2C0_TX_REQ 19
+#define IRQ_I2C0_STOP_DET 20
+#define IRQ_I2C0_ERR 21
+#define IRQ_I2C1_RX_AVAIL 22
+#define IRQ_I2C1_TX_REQ 23
+#define IRQ_I2C1_STOP_DET 24
+#define IRQ_I2C1_ERR 25
+#define IRQ_SPI0_ERR_INT 30
+#define IRQ_SPI0_RX_AVAIL 31
+#define IRQ_SPI0_TX_REQ 32
+
+#define IRQ_SPI1_ERR_INT 33
+#define IRQ_SPI1_RX_AVAIL 34
+#define IRQ_SPI1_TX_REQ 35
+
+#define IRQ_ADC_ERR 18
+#define IRQ_ADC_IRQ 19
+#define IRQ_GPIO0_INTR 20
+#define IRQ_GPIO1_INTR 21
+#define IRQ_I2C_MST0_INTR 36
+#define IRQ_I2C_MST1_INTR 37
+#define IRQ_SPI_MST0_INTR 38
+#define IRQ_SPI_MST1_INTR 39
+#define IRQ_SPI_SLV_INTR 40
+#define IRQ_UART0_INTR 41
+#define IRQ_UART1_INTR 42
+#define IRQ_I2S_INTR 43
+#define IRQ_GPIO_INTR 44
+#define IRQ_PWM_TIMER_INTR 45
+#define IRQ_USB_INTR 46
+#define IRQ_RTC_INTR 47
+#define IRQ_WDOG_INTR 48
+#define IRQ_DMA_CHAN0 49
+#define IRQ_DMA_CHAN1 50
+#define IRQ_DMA_CHAN2 51
+#define IRQ_DMA_CHAN3 52
+#define IRQ_DMA_CHAN4 53
+#define IRQ_DMA_CHAN5 54
+#define IRQ_DMA_CHAN6 55
+#define IRQ_DMA_CHAN7 56
+#define IRQ_MAILBOXES_INTR 57
+#define IRQ_COMPARATORS_INTR 58
+#define IRQ_SYS_PMU_INTR 59
+#define IRQ_DMA_CHANS_ERR 60
+#define IRQ_INT_SRAM_CTLR 61
+#define IRQ_INT_FLASH0_CTLR 62
+#define IRQ_INT_FLASH1_CTLR 63
+#define IRQ_ALWAYS_ON_TMR 64
+#define IRQ_ADC_PWR 65
+#define IRQ_ADC_CALIB 66
+#define IRQ_ALWAYS_ON_GPIO 67
+
+#ifndef _ASMLANGUAGE
+
+#include <misc/util.h>
+#include <drivers/rand32.h>
+#include <quark_se/shared_mem.h>
+
+#define INT_ENABLE_ARC					~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS				(8)
+
+/*
+ * I2C
+ */
+#define I2C_SS_0_ERR_VECTOR				22
+#define I2C_SS_0_ERR_MASK				0x410
+#define I2C_SS_0_RX_VECTOR				23
+#define I2C_SS_0_RX_MASK				0x414
+#define I2C_SS_0_TX_VECTOR				24
+#define I2C_SS_0_TX_MASK				0x418
+#define I2C_SS_0_STOP_VECTOR				25
+#define I2C_SS_0_STOP_MASK				0x41C
+
+#define I2C_SS_1_ERR_VECTOR				26
+#define I2C_SS_1_ERR_MASK				0x420
+#define I2C_SS_1_RX_VECTOR				27
+#define I2C_SS_1_RX_MASK				0x424
+#define I2C_SS_1_TX_VECTOR				28
+#define I2C_SS_1_TX_MASK				0x428
+#define I2C_SS_1_STOP_VECTOR				29
+#define I2C_SS_1_STOP_MASK				0x42C
+
+/*
+ * GPIO
+ */
+#define GPIO_DW_IO_ACCESS
+
+#define GPIO_DW_0_BASE_ADDR			0x80017800
+#define GPIO_DW_0_IRQ				20
+#define GPIO_DW_0_BITS				8
+#define GPIO_DW_PORT_0_INT_MASK			(SCSS_REGISTER_BASE + 0x408)
+
+#define GPIO_DW_1_BASE_ADDR			0x80017900
+#define GPIO_DW_1_IRQ				21
+#define GPIO_DW_1_BITS				8
+#define GPIO_DW_PORT_1_INT_MASK			(SCSS_REGISTER_BASE + 0x40C)
+
+#if defined(CONFIG_IOAPIC)
+#define GPIO_DW_0_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#define GPIO_DW_1_IRQ_FLAGS			(IOAPIC_EDGE | IOAPIC_HIGH)
+#endif
+
+/*
+ * UART
+ */
+
+#define UART_IRQ_FLAGS                                  0
+
+#define UART_NS16550_PORT_0_BASE_ADDR			0xB0002000
+#define UART_NS16550_PORT_0_IRQ				41
+#define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_0_INT_MASK			0x460
+
+#define UART_NS16550_PORT_1_BASE_ADDR			0xB0002400
+#define UART_NS16550_PORT_1_IRQ				42
+#define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+#define UART_NS16550_PORT_1_INT_MASK			0x464
+
+/*
+ * SPI
+ */
+
+#define SPI_DW_PORT_0_REGS				0x80010000
+#define SPI_DW_PORT_1_REGS				0x80010100
+
+#define SPI_DW_PORT_0_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x430)
+#define SPI_DW_PORT_0_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x434)
+#define SPI_DW_PORT_0_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x438)
+
+#define SPI_DW_PORT_1_ERROR_INT_MASK			(SCSS_REGISTER_BASE + 0x43C)
+#define SPI_DW_PORT_1_RX_INT_MASK			(SCSS_REGISTER_BASE + 0x440)
+#define SPI_DW_PORT_1_TX_INT_MASK			(SCSS_REGISTER_BASE + 0x444)
+
+#define SPI_DW_IRQ_FLAGS				0
+
+static inline void _quark_se_ss_ready(void)
+{
+	shared_data->flags |= ARC_READY;
+}
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _BOARD__H_ */

arch/arc/soc/quark_se_c1000_ss/soc_config.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+#include "soc.h"
+
+#if CONFIG_IPM_QUARK_SE
+#include <ipm.h>
+#include <ipm/ipm_quark_se.h>
+
+static int arc_quark_se_ipm_init(void)
+{
+	IRQ_CONNECT(QUARK_SE_IPM_INTERRUPT, CONFIG_QUARK_SE_SS_IPM_IRQ_PRI,
+		    quark_se_ipm_isr, NULL, 0);
+	irq_enable(QUARK_SE_IPM_INTERRUPT);
+	return 0;
+}
+
+static struct quark_se_ipm_controller_config_info ipm_controller_config = {
+	.controller_init = arc_quark_se_ipm_init
+};
+DEVICE_AND_API_INIT(quark_se_ipm, "", quark_se_ipm_controller_initialize,
+				NULL, &ipm_controller_config,
+				POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+				&ipm_quark_se_api_funcs);
+
+#if CONFIG_IPM_CONSOLE_SENDER
+#include <console/ipm_console.h>
+QUARK_SE_IPM_DEFINE(quark_se_ipm4, 4, QUARK_SE_IPM_OUTBOUND);
+
+static struct ipm_console_sender_config_info quark_se_ipm_sender_config = {
+	.bind_to = "quark_se_ipm4",
+	.flags = IPM_CONSOLE_PRINTK | IPM_CONSOLE_STDOUT,
+};
+DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init,
+				NULL, &quark_se_ipm_sender_config,
+				POST_KERNEL, CONFIG_IPM_CONSOLE_INIT_PRIORITY);
+
+#endif /* CONFIG_IPM_CONSOLE_SENDER */
+#endif /* CONFIG_IPM_QUARK_SE */
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+#ifdef CONFIG_UART_NS16550_PORT_0
+	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK),
+		      INT_ENABLE_ARC_BIT_POS);
+#endif /* CONFIG_UART_NS16550_PORT_0 */
+
+#ifdef CONFIG_UART_NS16550_PORT_1
+	sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK),
+		      INT_ENABLE_ARC_BIT_POS);
+#endif /* CONFIG_UART_NS16550_PORT_1 */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

arch/arc/soc/quark_se_c1000_ss/soc_power.S

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <toolchain.h>
+#include <arch/arc/v2/aux_regs.h>
+#include <swap_macros.h>
+
+#ifdef CONFIG_SYS_POWER_DEEP_SLEEP
+GDATA(_pm_arc_context)
+
+GTEXT(_sys_soc_resume_from_deep_sleep)
+GTEXT(_power_restore_cpu_context)
+GTEXT(_power_soc_sleep)
+GTEXT(_power_soc_deep_sleep)
+GTEXT(_power_soc_deep_sleep_2)
+
+#define GPS0_REGISTER  0xb0800100
+#define GP0_REGISTER 0xb0800114
+#define GP0_BIT_SLEEP_READY 0
+#define RESTORE_SS_BIT 2
+#define SLEEP_INTR_ENABLED_BIT 4
+#define SLEEP_MODE_RTC_ENABLED_BIT 5
+
+SECTION_FUNC(TEXT, _sys_soc_resume_from_deep_sleep)
+        /* Check is this wakeup after sleep event. */
+        ld r0,[GPS0_REGISTER]
+        bbit1 r0,RESTORE_SS_BIT,restore
+	j_s [blink] /* Jump to context of BLINK register. */
+
+restore:
+        bclr_s r0,r0,RESTORE_SS_BIT
+        st r0,[GPS0_REGISTER]
+
+	/* Enable I-Cache */
+        sr 1, [_ARC_V2_IC_CTRL]
+
+	j @_sys_soc_restore_cpu_context
+
+SECTION_FUNC(TEXT, save_cpu_context)
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	_save_callee_saved_regs
+
+	j_s [blink] /* Jump to context of BLINK register. */
+
+SECTION_FUNC(TEXT, _power_soc_sleep)
+	/*
+	 * Save the return address.
+	 * The restore function will pop this and jump
+	 * back to the caller.
+	 */
+	push_s blink
+
+	/* Do not link to preserve blink */
+	jl @save_cpu_context
+	j @qm_power_soc_sleep
+	/* Does not return */
+
+SECTION_FUNC(TEXT, _power_soc_deep_sleep)
+	/*
+	 * Save the return address.
+	 * The restore function will pop this and jump
+	 * back to the caller.
+	 */
+	push_s blink
+
+	/* Do not link to preserve blink */
+	jl @save_cpu_context
+	j @qm_power_soc_deep_sleep
+	/* Does not return */
+
+SECTION_FUNC(TEXT, _power_soc_deep_sleep_2)
+	/*
+	 * Setup 'sleep' instruction operand.
+	 */
+
+	/* Get interrupt priority from status32 registers. */
+	lr r0, [_ARC_V2_STATUS32]
+	lsr r0, r0
+	and r0, r0, 0xF
+
+	/* Enable interrupts */
+	bset r0, r0, SLEEP_INTR_ENABLED_BIT
+
+	/* Set 'sleep' mode corresponding to SS2 state i.e. core disabled,
+	 * timers disabled, RTC enabled.
+	 */
+	bset r0, r0, SLEEP_MODE_RTC_ENABLED_BIT
+
+	/*
+	 * Save the return address.
+	 * The restore function will pop this and jump
+	 * back to the caller.
+	 */
+	push_s blink
+
+	jl @save_cpu_context
+
+	ld r1, [GP0_REGISTER]
+	bset r1, r1, GP0_BIT_SLEEP_READY
+	st r1, [GP0_REGISTER]
+	sleep r0
+
+	/* If we reach this code it means the x86 core didn't put the
+	 * system in SYS_POWER_STATE_DEEP_SLEEP_2 state while we were
+	 * in LPS. Then discard saved context.
+	 */
+	_discard_callee_saved_regs
+
+	pop_s blink
+	j_s [blink]
+
+SECTION_FUNC(TEXT, _sys_soc_restore_cpu_context)
+	mov_s r1, _kernel
+	ld_s r2, [r1, _kernel_offset_to_current]
+
+	_load_callee_saved_regs
+
+	/* Restore return address */
+	pop_s blink
+
+	j_s [blink] /* Jump to context of BLINK register. */
+#endif

arch/arc/soc/quark_se_c1000_ss/soc_power.h

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_POWER_H_
+#define _SOC_POWER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Bit 0 from GP0 register is used internally by the kernel
+ * to handle PM multicore support. Any change on QMSI and/or
+ * bootloader which affects this bit should take it in
+ * consideration.
+ */
+#define GP0_BIT_SLEEP_READY BIT(0)
+
+enum power_states {
+	SYS_POWER_STATE_CPU_LPS,       /* SS2 with LPSS enabled state */
+	SYS_POWER_STATE_CPU_LPS_1,     /* SS2 state */
+	SYS_POWER_STATE_CPU_LPS_2,     /* SS1 state with Timer ON */
+	SYS_POWER_STATE_DEEP_SLEEP,    /* DEEP SLEEP state */
+	SYS_POWER_STATE_DEEP_SLEEP_1,  /* SLEEP state */
+	SYS_POWER_STATE_DEEP_SLEEP_2,  /* Multicore DEEP SLEEP state.
+					* Execution context is saved
+					* and core enters in LPS state.
+					*/
+	SYS_POWER_STATE_MAX
+};
+
+/**
+ * @brief Put processor into low power state
+ *
+ * This function implements the SoC specific details necessary
+ * to put the processor into available power states.
+ *
+ * Wake up considerations:
+ * -----------------------
+ *
+ * SYS_POWER_STATE_CPU_LPS_2: Any interrupt works as wake event.
+ *
+ * SYS_POWER_STATE_CPU_LPS_1: Any interrupt works as wake event except
+ * the ARC TIMER which is disabled.
+ *
+ * SYS_POWER_STATE_CPU_LPS: SYS_POWER_STATE_DEEP_SLEEP wake events applies.
+ *
+ * SYS_POWER_STATE_DEEP_SLEEP: Only Always-On peripherals can wake up
+ * the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
+ *
+ * SYS_POWER_STATE_DEEP_SLEEP_1: Only Always-On peripherals can wake up
+ * the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
+ *
+ * SYS_POWER_STATE_DEEP_SLEEP_2: Only Always-On peripherals can wake up
+ * the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
+ *
+ * Considerations around SYS_POWER_STATE_CPU_LPS (LPSS state):
+ * -----------------------------------------------------------
+ *
+ * LPSS is a common power state between the x86 and ARC.
+ * When the two applications enter SYS_POWER_STATE_CPU_LPS,
+ * the SoC will enter this lower consumption mode.
+ * After wake up, this state can only be entered again
+ * if the ARC wakes up and transitions again to
+ * SYS_POWER_STATE_CPU_LPS. This is not required on the x86 side.
+ */
+void _sys_soc_set_power_state(enum power_states state);
+
+/**
+ * @brief Do any SoC or architecture specific post ops after low power states.
+ *
+ * This function is a place holder to do any operations that may
+ * be needed to be done after deep sleep exits.  Currently it enables
+ * interrupts after resuming from deep sleep. In future, the enabling
+ * of interrupts may be moved into the kernel.
+ */
+void _sys_soc_power_state_post_ops(enum power_states state);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC_POWER_H_ */

arch/arc/soc/quark_se_ss/Kbuild

@@ -1,9 +0,0 @@
-ccflags-y +=-I$(srctree)/arch/x86/soc/
-ccflags-y +=-I$(srctree)/include
-ccflags-y +=-I$(srctree)/include/drivers
-ccflags-y +=-I$(srctree)/drivers
-ccflags-$(CONFIG_ADC) +=-I$(srctree)/drivers/adc
-
-asflags-y := ${ccflags-y}
-
-obj-y = soc.o soc_config.o

arch/arc/soc/quark_se_ss/Kconfig.defconfig

@@ -1,221 +0,0 @@
-#
-# Copyright (c) 2014 Wind River Systems, Inc.
-# Copyright (c) 2015-2016 Intel Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-
-if SOC_QUARK_SE_SS
-
-config SOC
-	default quark_se_ss
-
-config NUM_IRQ_PRIO_LEVELS
-	# This processor supports only 2 priority levels:
-	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
-	default 2
-
-config NUM_REGULAR_IRQ_PRIO_LEVELS
-	# This processor supports only 1 Regular Interrupt priority level (1).
-	default 1
-
-config  NUM_IRQS
-	# must be > the highest interrupt number used
-	default 68
-
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 32000000
-
-config RAM_START
-	default 0x4000 if NSIM
-	default 0xa8000400
-
-config RAM_SIZE
-	default 16 if NSIM
-	default 24
-
-if GPIO
-
-config GPIO_DW
-	def_bool y
-
-if GPIO_DW
-
-config GPIO_DW_BOTHEDGES_SUPPORT
-	default n
-
-config GPIO_DW_0
-	def_bool y
-
-if GPIO_DW_0
-
-config GPIO_DW_0_BASE_ADDR
-	default 0x80017800
-config GPIO_DW_0_IRQ
-	default 20
-config GPIO_DW_0_PRI
-	default 2
-config GPIO_DW_0_BITS
-	default 8
-
-endif # GPIO_DW_0
-
-config GPIO_DW_1
-	def_bool y
-
-if GPIO_DW_1
-
-config GPIO_DW_1_BASE_ADDR
-	default 0x80017900
-config GPIO_DW_1_IRQ
-	default 21
-config GPIO_DW_1_PRI
-	default 2
-config GPIO_DW_1_BITS
-	default 8
-
-endif # GPIO_DW_1
-
-endif # GPIO_DW
-
-endif # GPIO
-
-if I2C
-
-config I2C_QUARK_SE_SS
-	def_bool y
-
-if I2C_QUARK_SE_SS
-
-config I2C_QUARK_SE_SS_0
-	def_bool y
-
-if I2C_QUARK_SE_SS_0
-
-config I2C_QUARK_SE_SS_0_NAME
-	default "I2C0"
-
-config I2C_QUARK_SE_SS_0_DEFAULT_CFG
-	default 0x12
-
-endif # I2C_QUARK_SE_SS_0
-
-if I2C_QUARK_SE_SS_1
-
-config I2C_QUARK_SE_SS_1_NAME
-	default "I2C1"
-
-config I2C_QUARK_SE_SS_1_DEFAULT_CFG
-	default 0x12
-
-endif # I2C_QUARK_SE_SS_1
-
-endif # I2C_QUARK_SE_SS
-
-endif # I2C
-
-if UART_NS16550
-
-config UART_NS16550_PORT_0
-        def_bool y
-
-if UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_0_NAME
-        default "UART_0"
-config UART_NS16550_PORT_0_IRQ_PRI
-        default 1
-config UART_NS16550_PORT_0_BAUD_RATE
-        default 115200
-config UART_NS16550_PORT_0_OPTIONS
-        default 0
-
-endif # UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_1
-        def_bool y
-
-if UART_NS16550_PORT_1
-
-config UART_NS16550_PORT_1_NAME
-        default "UART_1"
-config UART_NS16550_PORT_1_IRQ_PRI
-        default 1
-config UART_NS16550_PORT_1_BAUD_RATE
-        default 115200
-config UART_NS16550_PORT_1_OPTIONS
-        default 0
-
-endif # UART_NS16550_PORT_1
-
-endif # UART_NS16550
-
-if UART_CONSOLE
-
-config UART_CONSOLE_ON_DEV_NAME
-        default "UART_1"
-
-endif
-
-if SPI
-
-config SPI_DW
-	def_bool y
-
-if SPI_DW
-
-config SPI_DW_CLOCK_GATE
-	def_bool n
-
-config SPI_DW_PORT_0
-	def_bool y
-
-if SPI_DW_PORT_0
-
-config SPI_DW_PORT_0_PRI
-	default 1
-config SPI_DW_PORT_0_REGS
-	default 0x80010000
-config SPI_DW_PORT_0_ERROR_IRQ
-	default 30
-config SPI_DW_PORT_0_RX_IRQ
-	default 31
-config SPI_DW_PORT_0_TX_IRQ
-	default 32
-
-endif # SPI_DW_PORT_0
-
-config SPI_DW_PORT_1
-	def_bool y
-
-if SPI_DW_PORT_1
-
-config SPI_DW_PORT_1_PRI
-	default 1
-config SPI_DW_PORT_1_REGS
-	default 0x80010100
-config SPI_DW_PORT_1_ERROR_IRQ
-	default 33
-config SPI_DW_PORT_1_RX_IRQ
-	default 34
-config SPI_DW_PORT_1_TX_IRQ
-	default 35
-
-endif # SPI_DW_PORT_1
-
-endif # SPI_DW
-
-endif # SPI
-
-endif #SOC_QUARK_SE_ARC