soc: Remove soc_legacy folder and move ARM Kconfig

Removes the soc_legacy folder which is left over from the
transition to hwmv2 and moves the Kconfig for ARM to arch

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

.github/workflows/codecov.yaml

@@ -20,7 +20,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        platform: ["mps2_an385", "native_sim", "qemu_x86", "unit_testing"]
+        platform: ["mps2/an385", "native_sim", "qemu_x86", "unit_testing"]
     steps:
       - name: Apply container owner mismatch workaround
         run: |

.github/workflows/compliance.yml

@@ -57,6 +57,8 @@ jobs:
         # debug
         ls -la
         git log  --pretty=oneline | head -n 10
+        # Increase rename limit to allow for large PRs
+        git config diff.renameLimit 10000
         ./scripts/ci/check_compliance.py --annotate -e KconfigBasic \
         -c origin/${BASE_REF}..
 

.gitignore

@@ -68,14 +68,17 @@ tags
 
 # from check_compliance.py
 BinaryFiles.txt
+BoardYml.txt
 Checkpatch.txt
 DevicetreeBindings.txt
+GitDiffCheck.txt
 Gitlint.txt
 Identity.txt
 ImageSize.txt
 Kconfig.txt
 KconfigBasic.txt
 KconfigBasicNoModules.txt
+KconfigHWMv2.txt
 KeepSorted.txt
 MaintainersFormat.txt
 ModulesMaintainers.txt

CMakeLists.txt

@@ -118,7 +118,7 @@ zephyr_include_directories(
 
 include(${ZEPHYR_BASE}/cmake/linker_script/${ARCH}/linker.cmake OPTIONAL)
 
-zephyr_include_directories(${SOC_DIR}/${ARCH}/${SOC_PATH})
+zephyr_include_directories(${SOC_FULL_DIR})
 
 # Don't inherit compiler flags from the environment
 foreach(var AFLAGS CFLAGS CXXFLAGS CPPFLAGS LDFLAGS)

CODEOWNERS

@@ -19,13 +19,7 @@
 # entries that are not covered by the MAINTAINERS file.
 
 /soc/arm/aspeed/                          @aspeeddylan
-/soc/arm/atmel_sam/common/*_sam4l_*.c     @nandojve
-/soc/arm/atmel_sam/sam3x/                 @ioannisg
-/soc/arm/atmel_sam/sam4e/                 @nandojve
-/soc/arm/atmel_sam/sam4l/                 @nandojve
-/soc/arm/atmel_sam/sam4s/                 @fallrisk
-/soc/arm/atmel_sam/same70/                @nandojve
-/soc/arm/atmel_sam/samv71/                @nandojve
+/soc/atmel/                               @nandojve
 /soc/arm/bcm*/                            @sbranden
 /soc/arm/infineon_cat1/                   @ifyall @npal-cy
 /soc/arm/infineon_xmc/                    @parthitce
@@ -101,11 +95,7 @@
 /boards/arm/rpi_pico/                     @yonsch
 /boards/arm/ronoth_lodev/                 @NorthernDean
 /boards/arm/xmc45_relax_kit/              @parthitce
-/boards/arm/sam4e_xpro/                   @nandojve
-/boards/arm/sam4l_ek/                     @nandojve
-/boards/arm/sam4s_xplained/               @fallrisk
-/boards/arm/sam_e70_xplained/             @nandojve
-/boards/arm/sam_v71_xult/                 @nandojve
+/boards/atmel/                            @nandojve
 /boards/arm/scobc_module1/                @yashi
 /boards/arm/v2m_beetle/                   @fvincenzo
 /boards/arm/olimexino_stm32/              @ydamigos
@@ -411,13 +401,7 @@
 /dts/arc/                                 @abrodkin @ruuddw @iriszzw @evgeniy-paltsev
 /dts/arm/acsip/                           @NorthernDean
 /dts/arm/aspeed/                          @aspeeddylan
-/dts/arm/atmel/sam4e*                     @nandojve
-/dts/arm/atmel/sam4l*                     @nandojve
-/dts/arm/atmel/samr21.dtsi                @benpicco
-/dts/arm/atmel/sam*5*.dtsi                @benpicco
-/dts/arm/atmel/same70*                    @nandojve
-/dts/arm/atmel/samv71*                    @nandojve
-/dts/arm/atmel/                           @galak
+/dts/arm/atmel/                           @galak @nandojve
 /dts/arm/broadcom/                        @sbranden
 /dts/arm/cypress/                         @ifyall @npal-cy
 /dts/arm/gd/                              @nandojve
@@ -428,7 +412,7 @@
 /dts/arm64/nxp/                           @JiafeiPan
 /dts/arm64/renesas/                       @lorc @xakep-amatop
 /dts/arm/quicklogic/                      @fkokosinski @kgugala
-/dts/arm/seeed/                           @str4t0m
+/dts/arm/seeed_studio/                    @str4t0m
 /dts/arm/st/                              @erwango
 /dts/arm/st/h7/*stm32h735*                @benediktibk
 /dts/arm/st/l4/*stm32l451*                @benediktibk
@@ -475,6 +459,7 @@
 /dts/bindings/counter/snps,dw-timers.yaml @pbalsundar
 /dts/bindings/wifi/*esp-at.yaml           @mniestroj
 /dts/bindings/*/*gd32*                    @nandojve
+/dts/bindings/*/*sam*                     @nandojve
 /dts/bindings/*/*npcx*                    @MulinChao @ChiHuaL
 /dts/bindings/*/*psoc6*                   @ifyall @npal-cy
 /dts/bindings/*/*infineon*cat1*           @ifyall @npal-cy

Kconfig.zephyr

@@ -21,12 +21,11 @@ osource "$(KCONFIG_BINARY_DIR)/Kconfig.shield.defconfig"
 # This loads Zephyr base shield defconfigs
 source "boards/shields/*/Kconfig.defconfig"
 
-source "$(BOARD_DIR)/Kconfig.defconfig"
+osource "$(BOARD_DIR)/Kconfig.defconfig"
+
+# This loads Zephyr specific SoC root defconfigs
+source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.defconfig"
 
-# This loads custom SoC root defconfigs
-osource "$(KCONFIG_BINARY_DIR)/Kconfig.soc.defconfig"
-# This loads Zephyr base SoC root defconfigs
-osource "soc/$(ARCH)/*/Kconfig.defconfig"
 # This loads the toolchain defconfigs
 osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig.defconfig"
 # This loads the testsuite defconfig
@@ -644,7 +643,7 @@ config BUILD_OUTPUT_UF2_FAMILY_ID
 	default "0x1c5f21b0" if SOC_SERIES_ESP32
 	default "0x621e937a" if SOC_NRF52833_QIAA
 	default "0xada52840" if SOC_NRF52840_QIAA
-	default "0x4fb2d5bd" if SOC_SERIES_IMX_RT
+	default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
 	default "0x2abc77ec" if SOC_SERIES_LPC55XXX
 	default "0xe48bff56" if SOC_SERIES_RP2XXX
 	default "0x68ed2b88" if SOC_SERIES_SAMD21
@@ -906,7 +905,7 @@ config BOOTLOADER_SRAM_SIZE_DEPRECATED
 
 config BOOTLOADER_ESP_IDF
 	bool "ESP-IDF bootloader support"
-	depends on SOC_FAMILY_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT
+	depends on SOC_FAMILY_ESPRESSIF_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT
 	default	y
 	help
 	  This option will trigger the compilation of the ESP-IDF bootloader

MAINTAINERS.yml

@@ -166,9 +166,7 @@ ARM arch:
     - include/zephyr/arch/arm/
     - tests/arch/arm/
     - doc/hardware/arch/arm_cortex_m.rst
-    - boards/arm/qemu_cortex_m3/
-    - boards/arm/qemu_cortex_m0/
-    - soc/arm/*
+    - boards/qemu/cortex_m0/
   labels:
     - "area: ARM"
   tests:
@@ -186,9 +184,9 @@ ARM64 arch:
     - arch/arm64/
     - include/zephyr/arch/arm64/
     - tests/arch/arm64/
-    - soc/arm64/
-    - boards/arm64/
     - dts/arm64/
+    - boards/qemu/kvm_arm64/
+    - boards/qemu/cortex_a53/
   labels:
     - "area: ARM64"
   tests:
@@ -198,8 +196,11 @@ ARM Platforms:
   status: odd fixes
   files:
     - boards/arm/mps*/
-    - soc/arm/arm/
     - boards/arm/v2m_*/
+    - soc/arm/mps*/
+    - soc/arm/musca/
+    - soc/arm/beetle/
+    - soc/arm/fvp_aemv8r/aarch32/
     - dts/arm/armv*.dtsi
   labels:
     - "platform: ARM"
@@ -207,7 +208,7 @@ ARM Platforms:
 ASPEED Platforms:
   status: odd fixes
   files:
-    - soc/arm/aspeed/
+    - soc/aspeed/
     - dts/arm/aspeed/
     - drivers/*/*_ast10x0.c
     - drivers/*/Kconfig.aspeed
@@ -230,10 +231,9 @@ ARM SiP SVC:
 MIPS arch:
   status: odd fixes
   files:
-    - soc/mips/
     - arch/mips/
     - include/zephyr/arch/mips/
-    - boards/mips/
+    - boards/qemu/malta/
   labels:
     - "area: MIPS"
   tests:
@@ -249,8 +249,8 @@ Ambiq Platforms:
     - aaronyegx
     - RichardSWheatley
   files:
-    - soc/arm/ambiq/
-    - boards/arm/apollo*/
+    - soc/ambiq/
+    - boards/ambiq/apollo*/
     - dts/arm/ambiq/
     - dts/bindings/*/ambiq,*
     - drivers/*/*ambiq*
@@ -268,8 +268,7 @@ BeagleBoard Platforms:
     - con-pax
     - vaishnavachath
   files:
-    - boards/arm/beagle*/
-    - boards/riscv/beagle*/
+    - boards/beagle/
   labels:
     - "platform: BeagleBoard"
 
@@ -524,7 +523,7 @@ Board/SoC configuration:
     - nordicjm
     - "57300"
   files:
-    - soc/Kconfig
+    - soc/Kconfig*
     - boards/Kconfig
   labels:
     - "area: Board/SoC configuration"
@@ -2011,8 +2010,8 @@ Xen Platform:
     - include/zephyr/xen/
     - drivers/xen/
     - arch/arm64/core/xen/
-    - soc/arm64/xenvm/
-    - boards/arm64/xenvm/
+    - soc/xen/
+    - boards/xen/
   labels:
     - "area: Xen Platform"
 
@@ -2070,7 +2069,7 @@ Google Platforms:
     - fabiobaltieri
     - keith-zephyr
   files:
-    - boards/*/google_*/
+    - boards/google/
     - samples/boards/google_*/
 
 Hash Utilities:
@@ -2303,12 +2302,7 @@ Laird Connectivity platforms:
   collaborators:
     - greg-leach
   files:
-    - boards/arm/bl5340_dvk/
-    - boards/arm/bl65*/
-    - boards/arm/bt510/
-    - boards/arm/bt610/
-    - boards/arm/pinnacle_100_dvk/
-    - boards/arm/mg100/
+    - boards/lairdconnect/
   labels:
     - "platform: Laird Connectivity"
 
@@ -2513,10 +2507,10 @@ Native POSIX/Sim and POSIX arch:
     - aescolar
   files:
     - arch/posix/
-    - boards/posix/common/
-    - boards/posix/native_*/
-    - boards/posix/doc/
-    - boards/posix/*.rst
+    - boards/native/common/
+    - boards/native/native_*/
+    - boards/native/doc/
+    - boards/native/*.rst
     - drivers/*/*posix*
     - drivers/*/*native*
     - drivers/*/*/*posix*
@@ -2525,7 +2519,7 @@ Native POSIX/Sim and POSIX arch:
     - include/zephyr/arch/posix/
     - scripts/native_simulator/
     - scripts/valgrind.supp
-    - soc/posix/
+    - soc/native/
     - tests/boards/native_sim/
   labels:
     - "area: native port"
@@ -2769,11 +2763,11 @@ NIOS-2 arch:
     - arch/nios2/
     - dts/nios2/intel/
     - boards/common/nios2.board.cmake
-    - boards/nios2/
-    - soc/nios2/
+    - soc/altr/*nios2*/
     - include/zephyr/arch/nios2/
     - tests/boards/altera_max10/
-    - boards/nios2/qemu_nios2/
+    - boards/qemu/nios2/
+    - boards/altr/max10/
     - scripts/support/quartus-flash.py
   labels:
     - "area: NIOS2"
@@ -2785,7 +2779,7 @@ nRF BSIM:
   maintainers:
     - aescolar
   files:
-    - boards/posix/nrf_bsim/
+    - boards/native/nrf_bsim/
     - tests/boards/nrf52_bsim/
     - tests/bsim/
   files-exclude:
@@ -2846,7 +2840,7 @@ Power management:
 "Quicklogic Platform":
   status: odd fixes
   files:
-    - soc/arm/quicklogic_eos_s3/
+    - soc/quicklogic/
     - dts/arm/quicklogic/
   labels:
     - "platform: Quicklogic"
@@ -2865,10 +2859,14 @@ RISCV arch:
     - npitre
   files:
     - arch/riscv/
-    - boards/riscv/
+    - boards/qemu/riscv*/
+    - boards/sifive/
+    - boards/sparkfun/red_v_things_plus/
     - dts/bindings/riscv/
     - dts/riscv/
     - include/zephyr/arch/riscv/
+    - soc/common/riscv-privileged/
+    - soc/sifive/
     - soc/riscv/
     - tests/arch/riscv/
     - doc/hardware/arch/risc-v.rst
@@ -3009,9 +3007,19 @@ SPARC arch:
   files:
     - arch/sparc/
     - include/zephyr/arch/sparc/
-    - soc/sparc/
-    - boards/sparc/
     - dts/sparc/
+    - boards/qemu/leon3/
+  labels:
+    - "area: SPARC"
+
+Gaisler Platforms:
+  status: odd fixes
+  collaborators:
+    - julius-barendt
+  files:
+    - dts/sparc/gaisler/
+    - soc/gaisler/
+    - boards/gaisler/
   labels:
     - "area: SPARC"
 
@@ -3039,7 +3047,7 @@ ADI Platforms:
     - galak
     - microbuilder
   files:
-    - boards/arm/adi_*/
+    - boards/adi/
     - drivers/*/max*
     - drivers/*/*max*/
     - drivers/dac/dac_ltc*
@@ -3058,8 +3066,8 @@ Broadcom Platforms:
   status: odd fixes
   files:
     - dts/arm/broadcom/
-    - soc/arm/bcm_vk/
-    - boards/arm/bcm95840*/
+    - soc/brcm/
+    - boards/brcm/
 
 GD32 Platforms:
   status: maintained
@@ -3070,14 +3078,12 @@ GD32 Platforms:
     - gmarull
     - soburi
   files:
-    - boards/arm/gd32*/
-    - boards/riscv/gd32*/
-    - boards/riscv/longan_nano/
+    - boards/gd/
     - drivers/*/*gd32*
     - dts/*/gd/
     - dts/bindings/*/*gd32*
-    - soc/*/gd_gd32/
     - scripts/west_commands/*/*gd32*
+    - soc/gd/gd32/
   labels:
     - "platform: GD32"
   description: >-
@@ -3093,8 +3099,8 @@ Synopsys Platforms:
     - evgeniy-paltsev
     - IRISZZW
   files:
-    - soc/arc/
-    - boards/arc/
+    - soc/synopsys/
+    - boards/synopsys/
     - samples/boards/arc_secure_services/
   labels:
     - "platform: Synopsys"
@@ -3112,8 +3118,8 @@ Nuvoton NPCX Platforms:
     - jackrosenthal
     - fabiobaltieri
   files:
-    - soc/arm/nuvoton_npcx/
-    - boards/arm/npcx*/
+    - soc/nuvoton/npcx/
+    - boards/nuvoton/npcx*/
     - dts/arm/nuvoton/
     - dts/bindings/*/*npcx*
     - drivers/*/*_npcx*.c
@@ -3127,10 +3133,9 @@ Nuvoton Numicro Numaker Platforms:
   collaborators:
     - ssekar15
   files:
-    - soc/arm/nuvoton_numicro/
-    - soc/arm/nuvoton_numaker/
-    - boards/arm/nuvoton_pfm*/
-    - boards/arm/numaker_*/
+    - soc/nuvoton/numaker/
+    - soc/nuvoton/numicro/
+    - boards/nuvoton/numaker*/
     - dts/arm/nuvoton/
     - dts/bindings/*/*numicro*
     - dts/bindings/*/*numaker*
@@ -3146,15 +3151,15 @@ Raspberry Pi Pico Platforms:
   collaborators:
     - soburi
   files:
-    - boards/arm/rpi_pico/
-    - boards/arm/adafruit_kb2040/
-    - boards/arm/sparkfun_pro_micro_rp2040/
+    - boards/raspberrypi/
+    - boards/adafruit/kb2040/
+    - boards/sparkfun/pro_micro_rp2040/
     - dts/arm/rpi_pico/
     - dts/bindings/*/raspberrypi,pico*
     - drivers/*/*rpi_pico
     - drivers/*/*rpi_pico*/
     - drivers/*/*rpi_pico*.c
-    - soc/arm/rpi_pico/
+    - soc/raspberrypi/
   labels:
     - "platform: Raspberry Pi Pico"
 
@@ -3165,8 +3170,8 @@ SiLabs Platforms:
   collaborators:
     - tgorochowik
   files:
-    - soc/arm/silabs_*/
-    - boards/arm/ef*/
+    - soc/silabs/
+    - boards/silabs/
     - dts/arm/silabs/
     - dts/bindings/*/silabs*
     - drivers/*/*_gecko*
@@ -3181,9 +3186,13 @@ Intel Platforms (X86):
     - tbursztyka
     - laurenmurphyx64
   files:
-    - boards/x86/
+    - boards/intel/adl/
+    - boards/intel/ehl/
+    - boards/intel/rpl/
     - dts/x86/intel/
-    - soc/x86/
+    - soc/intel/atom/
+    - soc/intel/lakemont/
+    - soc/intel/*_lake/
     - samples/boards/up_squared/
   labels:
     - "platform: X86"
@@ -3205,8 +3214,8 @@ Intel Platforms (Xtensa):
     - jxstelter
     - marcinszkudlinski
   files:
-    - boards/xtensa/intel_*/
-    - soc/xtensa/intel_*/
+    - boards/intel/adsp/
+    - soc/intel/intel_adsp/
     - dts/xtensa/intel/
     - tests/boards/intel_adsp/
     - samples/boards/intel_adsp/
@@ -3223,8 +3232,8 @@ Intel Platforms (ISH):
     - teburd
     - likongintel
   files:
-    - boards/x86/intel_ish/
-    - soc/x86/intel_ish/
+    - boards/intel/ish/
+    - soc/intel/intel_ish/
     - dts/x86/intel/intel_ish*
     - dts/bindings/*/intel,sedi*
     - drivers/*/*sedi*
@@ -3239,8 +3248,8 @@ Intel Platforms (Agilex):
     - nbalabak
     - teikheng
   files:
-    - boards/arm64/intel_*/
-    - soc/arm64/intel_*/
+    - boards/intel/socfpga/
+    - soc/intel/intel_socfpga/
     - dts/arm64/intel/
     - dts/bindings/*/intel,agilex*
     - dts/arm/intel_socfpga_std/
@@ -3272,17 +3281,13 @@ NXP Drivers:
     - include/zephyr/drivers/*/*mcux*
     - arch/arm/core/mpu/nxp_mpu.c
     - dts/bindings/*/nxp*
-  files-exclude:
-    - drivers/*/*s32*
-    - drivers/misc/*/*s32*
-    - include/zephyr/dt-bindings/*/*s32*
-    - include/zephyr/drivers/*/*s32*
-    - dts/bindings/*/*s32*
+  files-regex-exclude:
+    - .*s32.*
   labels:
     - "platform: NXP Drivers"
   description: NXP Drivers
 
-NXP Platforms (MCUX):
+NXP Platforms (MCU):
   status: maintained
   maintainers:
     - dleach02
@@ -3294,23 +3299,21 @@ NXP Platforms (MCUX):
     - EmilioCBen
     - decsny
   files:
-    - boards/arm/mimx*/
-    - boards/arm/frdm*/
-    - boards/arm/lpcxpress*/
-    - boards/arm/twr_*/
-    - boards/arm/vmu*/
-    - soc/arm/nxp_imx/
-    - soc/arm/nxp_kinetis/
-    - soc/arm/nxp_lpc/
+    - boards/nxp/mimxrt*/
+    - boards/nxp/frdm*/
+    - boards/nxp/lpcxpress*/
+    - boards/nxp/twr_*/
+    - boards/nxp/vmu*/
+    - soc/nxp/imxrt/
+    - soc/nxp/kinetis/
+    - soc/nxp/lpc/
     - dts/arm/nxp/
     - samples/boards/nxp*/
-  files-exclude:
-    - boards/arm/*s32*/
-    - dts/arm/nxp/*s32*
-    - samples/boards/nxp_s32/
+  files-regex-exclude:
+    - .*s32.*
   labels:
     - "platform: NXP"
-  description: NXP Platforms supported by MCUXpresso suite
+  description: NXP MCU Platforms supported by MCUXpresso suite
 
 NXP Platforms (S32):
   status: maintained
@@ -3321,11 +3324,11 @@ NXP Platforms (S32):
     - bperseghetti
     - Dat-NguyenDuy
   files:
-    - boards/arm/s32*/
-    - boards/arm/mr_canhubk3/
-    - boards/arm/ucans32k1sic/
+    - boards/nxp/s32*/
+    - boards/nxp/mr_canhubk3/
+    - boards/nxp/ucans32k1sic/
     - boards/common/*nxp_s32*
-    - soc/arm/nxp_s32/
+    - soc/nxp/s32/
     - drivers/*/*nxp_s32*
     - drivers/misc/*nxp_s32*/
     - dts/bindings/*/nxp,s32*
@@ -3338,6 +3341,26 @@ NXP Platforms (S32):
     - "platform: NXP S32"
   description: NXP S32 platforms and S32-specific drivers
 
+NXP Platforms (MPU):
+  status: maintained
+  maintainers:
+    - dleach
+  collaborators:
+    - JiafeiPan
+    - dbaluta
+    - iuliana-prodan
+    - danieldegrasse
+    - decsny
+    - yvanderv
+  files:
+    - soc/nxp/imx/
+    - soc/nxp/layerscape/
+  files-regex:
+    - boards/nxp/m?imx[^(rt)].*/
+  labels:
+    - "platform: NXP MPU"
+  description: NXP MPU platforms
+
 NXP Platforms (Xtensa):
   status: maintained
   maintainers:
@@ -3345,10 +3368,10 @@ NXP Platforms (Xtensa):
   collaborators:
     - iuliana-prodan
   files:
-    - soc/xtensa/nxp_adsp/
-    - boards/xtensa/nxp_adsp_*/
+    - soc/nxp/imx/*/adsp/
+    - soc/nxp/imxrt/imxrt5xx/f1/
   labels:
-    - "platform: NXP ADSP"
+    - "platform: NXP Xtensa"
   description: NXP Xtensa platforms
 
 Microchip MEC Platforms:
@@ -3359,9 +3382,9 @@ Microchip MEC Platforms:
     - VenkatKotakonda
     - albertofloyd
   files:
-    - boards/arm/mec*/
+    - boards/microchip/mec*/
     - dts/arm/microchip/
-    - soc/arm/microchip_mec/
+    - soc/microchip/mec/
     - drivers/*/*mchp*.c
     - tests/boards/mec15xxevb_assy6853/
     - tests/boards/mec172xevb_assy6906/
@@ -3379,10 +3402,9 @@ Microchip SAM Platforms:
     - mnkp
     - stephanosio
   files:
-    - boards/arm/atsam*/
-    - boards/arm/sam*/
+    - boards/atmel/
     - dts/arm/atmel/
-    - soc/arm/atmel_sam*/
+    - soc/atmel/
     - drivers/*/*sam*.c
     - dts/bindings/*/atmel,*
   labels:
@@ -3393,9 +3415,9 @@ nRF Platforms:
   maintainers:
     - anangl
   files:
-    - boards/arm/*nrf*/
+    - boards/nordic/
     - drivers/*/*nrfx*.c
-    - soc/arm/nordic_nrf/
+    - soc/nordic/
     - samples/boards/nrf/
     - dts/arm/nordic/
     - dts/bindings/*/nordic,*
@@ -3409,11 +3431,11 @@ Renesas SmartBond Platforms:
     - andrzej-kaczmarek
     - blauret
   files:
-    - boards/arm/da14*/
+    - boards/renesas/da14*/
     - drivers/*/*smartbond*
     - dts/arm/renesas/smartbond/
     - dts/bindings/*/renesas,smartbond*
-    - soc/arm/renesas_smartbond/
+    - soc/renesas/smartbond/
   labels:
     - "platform: Renesas SmartBond"
   description: >-
@@ -3425,11 +3447,11 @@ Renesas RA Platforms:
   maintainers:
     - soburi
   files:
-    - boards/arm/arduino_uno_r4/
+    - boards/arduino/uno_r4_minima/
     - drivers/*/*renesas_ra*
     - dts/arm/renesas/ra/
     - dts/bindings/*/*renesas,ra*
-    - soc/arm/renesas_ra/
+    - soc/renesas/ra/
   labels:
     - "platforms: Renesas RA"
   description: >-
@@ -3441,11 +3463,11 @@ Renesas RZ Platforms:
   maintainers:
     - tgorochowik
   files:
-    - boards/arm/rzt2m_*/
+    - boards/renesas/rzt2m_*/
     - drivers/*/*rzt2m*
     - dts/arm/renesas/rz/
     - dts/bindings/*/*rzt2m*
-    - soc/arm/renesas_rzt2m/
+    - soc/renesas/rzt2m/
   labels:
     - "platforms: Renesas RZ"
   description: >-
@@ -3461,15 +3483,13 @@ Renesas R-Car Platforms:
     - xakep-amatop
   files:
     - dts/arm/renesas/rcar/
-    - boards/arm/rcar_*/
-    - boards/arm64/rcar_*/
+    - boards/renesas/rcar_*/
     - drivers/*/*rcar*
     - drivers/clock_control/*cpg_mssr*
     - dts/arm/renesas/rcar/
     - dts/arm64/renesas/
     - dts/bindings/*/*rcar*
-    - soc/arm/renesas_rcar/
-    - soc/arm64/renesas_rcar/
+    - soc/renesas/rcar/
   labels:
     - "platform: Renesas R-Car"
   description: >-
@@ -3488,11 +3508,7 @@ STM32 Platforms:
     - Desvauxm-st
     - GeorgeCGV
   files:
-    - boards/arm/b_*/
-    - boards/arm/nucleo_*/
-    - boards/arm/stm32*_disco/
-    - boards/arm/stm32*_dk*/
-    - boards/arm/stm32*_eval/
+    - boards/st/
     - drivers/*/*stm32*/
     - drivers/*/*stm32*.c
     - drivers/*/*stm32*.h
@@ -3500,7 +3516,7 @@ STM32 Platforms:
     - drivers/*/*stm32*
     - dts/arm/st/
     - dts/bindings/*/*stm32*
-    - soc/arm/st_stm32/
+    - soc/st/stm32/
     - samples/boards/stm32/
   labels:
     - "platform: STM32"
@@ -3518,16 +3534,14 @@ Espressif Platforms:
     - uLipe
   files:
     - drivers/*/*esp32*.c
-    - boards/xtensa/esp32*/
-    - soc/xtensa/espressif_esp32*/
-    - boards/riscv/esp32*/
-    - soc/riscv/espressif_esp32*/
+    - boards/espressif/
+    - soc/espressif/
     - dts/xtensa/espressif/
     - dts/riscv/espressif/
     - dts/bindings/*/*esp32*
     - samples/boards/esp32*/
     - tests/boards/espressif_esp32/
-    - drivers/wifi/esp32/
+    - drivers/*/*esp32*/
   labels:
     - "platform: ESP32"
 
@@ -3543,13 +3557,13 @@ ITE Platforms:
     - brockus-zephyr
     - sjg20
   files:
-    - boards/riscv/it8*_evb/
+    - boards/ite/
     - drivers/*/*/*it8xxx2*.c
     - drivers/*/*it8xxx2*.c
     - drivers/*/*_ite_*
     - dts/bindings/*/*ite*
     - dts/riscv/ite/
-    - soc/riscv/ite_ec/
+    - soc/ite/
   labels:
     - "platform: ITE"
 
@@ -3560,17 +3574,15 @@ TI SimpleLink Platforms:
   collaborators:
     - vanti
   files:
-    - boards/arm/cc13*/
-    - boards/arm/cc26*/
-    - boards/arm/cc32*/
-    - boards/*/msp*/
+    - boards/ti/cc*/
+    - boards/ti/msp*/
     - drivers/*/*cc13*
     - drivers/*/*cc25*
     - drivers/*/*cc26*
     - drivers/*/*cc32*
     - dts/arm/ti/
     - dts/bindings/*/ti,*
-    - soc/arm/ti_simplelink/
+    - soc/ti/simplelink/
     - dts/bindings/*/ti,*
     - modules/Kconfig.simplelink
   labels:
@@ -3583,18 +3595,18 @@ TI K3 Platforms:
   collaborators:
     - gramsay0
   files:
-    - boards/*/*phycore_am6*/
-    - boards/*/am6*/
+    - boards/phytec/*am62*/
+    - boards/ti/*am62*/
     - drivers/*/*ti_k3*
     - dts/bindings/*/ti,k3*
-    - soc/*/ti_k3/
+    - soc/ti/k3/
   labels:
     - "platform: TI K3"
 
 TI Platforms:
   status: odd fixes
   files:
-    - soc/arm/ti_lm3s6965/
+    - soc/ti/lm3s6965/
     - dts/arm/ti/lm3s6965.dtsi
   labels:
     - "platform: TI"
@@ -3609,7 +3621,7 @@ Xilinx Platforms:
     - dts/*/xilinx/
     - dts/bindings/*/*xlnx*
     - include/zephyr/*/*/*xlnx*
-    - soc/arm/xilinx*/
+    - soc/xlnx/
   labels:
     - "platform: Xilinx"
 
@@ -3621,18 +3633,17 @@ Infineon Platforms:
     - npal-cy
     - talih0
   files:
-    - boards/arm/cy8ckit_*/
-    - boards/arm/cy8cproto_*/
-    - boards/arm/xmc*_relax*/
+    - boards/cypress/
+    - boards/infineon/
     - drivers/*/*ifx_cat1*
     - drivers/*/*xmc*/
     - drivers/*/*xmc*.c
     - drivers/*/*/*xmc*
     - dts/arm/infineon/
     - dts/arm/cypress/
-    - soc/arm/cypress/
+    - soc/cypress/
     - dts/bindings/*/*infineon*
-    - soc/arm/infineon_*/
+    - soc/infineon/
   labels:
     - "platform: Infineon"
   description: >-
@@ -3644,7 +3655,7 @@ Panasonic Platforms:
   maintainers:
     - pideu-sj
   files:
-    - boards/arm/pan17*/
+    - boards/panasonic/
   labels:
     - "platform: Panasonic"
 
@@ -4588,11 +4599,11 @@ Xtensa arch:
     - arch/xtensa/
     - include/zephyr/arch/xtensa/
     - dts/xtensa/
-    - boards/xtensa/qemu_xtensa/
-    - boards/xtensa/xt-sim/
-    - soc/xtensa/dc233c/
-    - soc/xtensa/sample_controller/
-    - soc/xtensa/CMakeLists.txt
+    - boards/qemu/xtensa/
+    - boards/cdns/xt-sim/
+    - soc/cdns/dc233c/
+    - soc/cdns/dc233c/
+    - soc/cdns/xtensa_sample_controller/
   labels:
     - "area: Xtensa"
 
@@ -4698,8 +4709,8 @@ Testing with Renode:
     - fkokosinski
   files:
     - cmake/emu/renode.cmake
-    - boards/*/*/support/*.repl
-    - boards/*/*/support/*.resc
+    - boards/**/*/support/*.repl
+    - boards/**/*/support/*.resc
   labels:
     - "area: Renode"
 

arch/Kconfig

@@ -8,8 +8,10 @@
 # Include these first so that any properties (e.g. defaults) below can be
 # overridden (by defining symbols in multiple locations)
 
-# Note: $ARCH might be a glob pattern
-source "$(ARCH_DIR)/$(ARCH)/Kconfig"
+source "$(ARCH_DIR)/Kconfig.$(HWM_SCHEME)"
+
+# ToDo: Generate a Kconfig.arch for loading of additional arch in HWMv2.
+osource "$(KCONFIG_BINARY_DIR)/Kconfig.arch"
 
 # Architecture symbols
 #
@@ -1019,27 +1021,6 @@ config ARCH
 	help
 	  System architecture string.
 
-config SOC
-	string
-	help
-	  SoC name which can be found under soc/<arch>/<soc name>.
-	  This option holds the directory name used by the build system to locate
-	  the correct linker and header files for the SoC.
-
-config SOC_SERIES
-	string
-	help
-	  SoC series name which can be found under soc/<arch>/<family>/<series>.
-	  This option holds the directory name used by the build system to locate
-	  the correct linker and header files.
-
-config SOC_FAMILY
-	string
-	help
-	  SoC family name which can be found under soc/<arch>/<family>.
-	  This option holds the directory name used by the build system to locate
-	  the correct linker and header files.
-
 config TOOLCHAIN_HAS_BUILTIN_FFS
 	bool
 	default y if !(64BIT && RISCV)

arch/Kconfig.v1

@@ -0,0 +1,5 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Note: $ARCH might be a glob pattern
+source "$(ARCH_DIR)/$(ARCH)/Kconfig"

arch/Kconfig.v2

@@ -0,0 +1,5 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+
+# SPDX-License-Identifier: Apache-2.0
+
+source "$(KCONFIG_BINARY_DIR)/arch/Kconfig"

arch/arc/Kconfig

@@ -9,7 +9,6 @@ menu "ARC Options"
 config ARCH
 	default "arc"
 
-
 config CPU_ARCEM
 	bool
 	select ATOMIC_OPERATIONS_C
@@ -380,8 +379,6 @@ config ARC_EARLY_SOC_INIT
 	  (before C runtime initialization). Setup code is called in form of
 	  soc_early_asm_init_percpu assembler macro.
 
-endmenu
-
 config MAIN_STACK_SIZE
 	default 4096 if 64BIT
 
@@ -408,3 +405,5 @@ config CMSIS_V2_THREAD_MAX_STACK_SIZE
 
 config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
 	default 2048 if 64BIT
+
+endmenu

arch/archs.yml

@@ -0,0 +1,21 @@
+archs:
+  - name: arc
+    path: arc
+  - name: arm
+    path: arm
+  - name: arm64
+    path: arm64
+  - name: mips
+    path: mips
+  - name: nios2
+    path: nios2
+  - name: posix
+    path: posix
+  - name: riscv
+    path: riscv
+  - name: sparc
+    path: sparc
+  - name: xtensa
+    path: xtensa
+  - name: x86
+    path: x86

arch/arm/Kconfig

@@ -82,4 +82,47 @@ config ARM_ON_EXIT_CPU_IDLE
 rsource "core/Kconfig"
 rsource "core/Kconfig.vfp"
 
+# General options signifying CPU capabilities of ARM SoCs
+config CPU_HAS_ARM_MPU
+	bool
+	select CPU_HAS_MPU
+	help
+	  This option is enabled when the CPU has a Memory Protection Unit (MPU)
+	  in ARM flavor.
+
+config CPU_HAS_NXP_MPU
+	bool
+	select CPU_HAS_MPU
+	help
+	  This option is enabled when the CPU has a Memory Protection Unit (MPU)
+	  in NXP flavor.
+
+config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+	bool "Custom fixed SoC MPU region definition"
+	help
+	  If enabled, this option signifies that the SoC will
+	  define and configure its own fixed MPU regions in the
+	  SoC definition. These fixed MPU regions are currently
+	  used to set Flash and SRAM default access policies and
+	  they are programmed at boot time.
+
+config CPU_HAS_ARM_SAU
+	bool
+	select CPU_HAS_TEE
+	help
+	  MCU implements the ARM Security Attribution Unit (SAU).
+
+config CPU_HAS_NRF_IDAU
+	bool
+	select CPU_HAS_TEE
+	help
+	  MCU implements the nRF (vendor-specific) Security Attribution Unit.
+	  (IDAU: "Implementation-Defined Attribution Unit", in accordance with
+	  ARM terminology).
+
+config HAS_SWO
+	bool
+	help
+	  When enabled, indicates that SoC has an SWO output
+
 endmenu

arch/arm/core/cortex_m/timing.c

@@ -28,8 +28,8 @@
  */
 static inline uint64_t z_arm_dwt_freq_get(void)
 {
-#if defined(CONFIG_SOC_FAMILY_NRF) || \
-	defined(CONFIG_SOC_SERIES_IMX_RT6XX)
+#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) || \
+	defined(CONFIG_SOC_SERIES_IMXRT6XX)
 	/*
 	 * DWT frequency is taken directly from the
 	 * System Core clock (CPU) frequency, if the
@@ -77,7 +77,7 @@ static inline uint64_t z_arm_dwt_freq_get(void)
 
 	}
 	return dwt_frequency;
-#endif /* CONFIG_SOC_FAMILY_NRF */
+#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */
 }
 
 void arch_timing_init(void)

arch/common/CMakeLists.txt

@@ -71,7 +71,7 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
 
 # Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET.
 if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64
-    OR DEFINED CONFIG_SOC_OPENISA_RV32M1_RISCV32)
+    OR DEFINED CONFIG_SOC_OPENISA_RV32M1)
   # Exclamation mark is printable character with lowest number in ASCII table.
   # We are sure that this file will be included as a first.
   zephyr_linker_sources(ROM_START SORT_KEY ! rom_start_address.ld)

arch/riscv/core/fatal.c

@@ -163,7 +163,7 @@ void _Fault(z_arch_esf_t *esf)
 
 	__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
 
-#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
+#ifndef CONFIG_SOC_OPENISA_RV32M1
 	unsigned long mtval;
 	__asm__ volatile("csrr %0, mtval" : "=r" (mtval));
 #endif
@@ -171,7 +171,7 @@ void _Fault(z_arch_esf_t *esf)
 	mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK;
 	LOG_ERR("");
 	LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
-#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32
+#ifndef CONFIG_SOC_OPENISA_RV32M1
 	LOG_ERR("  mtval: %lx", mtval);
 #endif
 

arch/x86/core/early_serial.c

@@ -8,7 +8,6 @@
 #include <zephyr/sys/device_mmio.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/pcie/pcie.h>
-#include <soc.h>
 
 
 #if DT_PROP_OR(DT_CHOSEN(zephyr_console), io_mapped, 0) != 0

arch/xtensa/core/CMakeLists.txt

@@ -53,7 +53,7 @@ file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
 add_custom_command(OUTPUT ${CORE_ISA_DM}
   COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__
           -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC}
-          -I${SOC_DIR}/${ARCH}/${SOC_PATH}
+          -I${SOC_FULL_DIR}
           ${CORE_ISA_IN} -o ${CORE_ISA_DM})
 
 # Generates a list of device-specific scratch register choices

boards/96boards/aerocore2/96b_aerocore2.yaml

@@ -19,4 +19,4 @@ supported:
   - adc
 ram: 256
 flash: 2048
-vendor: gumstix
+vendor: 96boards

boards/96boards/aerocore2/96b_aerocore2_defconfig

@@ -1,9 +1,6 @@
 # Copyright (c) 2020 Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_STM32F4X=y
-CONFIG_SOC_STM32F427XX=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/96boards/aerocore2/Kconfig.96b_aerocore2

@@ -0,0 +1,5 @@
+#  Copyright (c) 2020 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_96B_AEROCORE2
+	select SOC_STM32F427XX

boards/96boards/aerocore2/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: 96b_aerocore2
+  vendor: 96boards
+  socs:
+    - name: stm32f427xx

boards/96boards/aerocore2/doc/index.rst

@@ -0,0 +1,349 @@
+.. _96b_aerocore2_board:
+
+96Boards Aerocore2
+##################
+
+Overview
+********
+
+The 96Boards Aerocore2 Mezzanine is based on the STMicroelectronics
+STM32F427VIT6 Cortex-M4 CPU primarily designed for use in drones.
+This board acts as a mezzanine platform for all 96Boards CE compliant
+boards. It can also be used as a standalone board.
+
+
+.. figure:: img/96b_aerocore2.jpg
+     :align: center
+     :alt: 96Boards Aerocore2
+
+     96Boards Aerocore2
+
+Hardware
+********
+
+96Boards Aerocore2 provides the following hardware components:
+
+- STM32F427VIT6 in LQFP100 package
+- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
+- 168 MHz max CPU frequency
+- VDD from 1.7 V to 3.6 V
+- 2048 KB Flash
+- 256 KB SRAM
+- GPIO with external interrupt capability
+- 12-bit ADC with 16 channels
+- RTC
+- Advanced-control Timers (2)
+- General Purpose Timers (10)
+- Watchdog Timers (2)
+- USART/UART (4)
+- I2C (3)
+- SPI (3)
+- SDIO
+- USB 2.0 OTG FS
+- DMA Controller
+
+More information about STM32F427VIT6 can be found here:
+       - `STM32F427 on www.st.com`_
+
+Supported Features
+==================
+
+The Zephyr 96b_aerocore2 board configuration supports the following hardware
+features:
+
++------------+------------+-------------------------------------+
+| Interface  | Controller | Driver/Component                    |
++============+============+=====================================+
+| NVIC       | on-chip    | nested vector interrupt controller  |
++------------+------------+-------------------------------------+
+| SYSTICK    | on-chip    | system clock                        |
++------------+------------+-------------------------------------+
+| UART       | on-chip    | serial port                         |
++------------+------------+-------------------------------------+
+| GPIO       | on-chip    | gpio                                |
++------------+------------+-------------------------------------+
+| PINMUX     | on-chip    | pinmux                              |
++------------+------------+-------------------------------------+
+| FLASH      | on-chip    | flash                               |
++------------+------------+-------------------------------------+
+| SPI        | on-chip    | spi                                 |
++------------+------------+-------------------------------------+
+| I2C        | on-chip    | i2c                                 |
++------------+------------+-------------------------------------+
+| PWM        | on-chip    | timers / pwm                        |
++------------+------------+-------------------------------------+
+| USB OTG FS | on-chip    | USB device                          |
++------------+------------+-------------------------------------+
+| ADC        | on-chip    | adc                                 |
++------------+------------+-------------------------------------+
+
+More details about the board can be found at `96Boards website`_.
+
+The default configuration can be found in
+:zephyr_file:`boards/96boards/aerocore2/96b_aerocore2_defconfig`
+
+Connections and IOs
+===================
+
+LED
+---
+
+- LED1 / User1 LED = PE10
+- LED2 / User2 LED = PE9
+
+External Connectors
+-------------------
+
+Octal PWM Header (J1)
+
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | Pin # | Signal Name |
++=======+=============+=========================+=======+=============+=======+=============+
+| 1     | PWM4_CH1    | PD12                    | 2     | 5.0v        | 3     | GND         |
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+| 4     | PWM4_CH2    | PD13                    | 5     | 5.0v        | 6     | GND         |
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+| 7     | PWM4_CH3    | PD14                    | 8     | 5.0v        | 9     | GND         |
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+| 10    | PWM4_CH4    | PD15                    | 11    | 5.0v        | 12    | GND         |
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+| 13    | PWM5_CH1    | PA0                     | 14    | 5.0v        | 15    | GND         |
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+| 16    | PWM5_CH2    | PA1                     | 17    | 5.0v        | 18    | GND         |
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+| 19    | PWM5_CH3    | PA2                     | 20    | 5.0v        | 21    | GND         |
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+| 22    | PWM5_CH4    | PA3                     | 23    | 5.0v        | 24    | GND         |
++-------+-------------+-------------------------+-------+-------------+-------+-------------+
+
+
+IO Header J11
+
++-------+-------------+-------+-------------+
+| PIN # | Signal Name | PIN # | Signal Name |
++=======+=============+=======+=============+
+| 1     | PB9         | 2     | PB8*        |
++-------+-------------+-------+-------------+
+| 3     | PC9         | 4     | PB0         |
++-------+-------------+-------+-------------+
+| 5     | PE5         | 6     | NA          |
++-------+-------------+-------+-------------+
+| 7     | PE6         | 8     | NA          |
++-------+-------------+-------+-------------+
+| 9     | PC6         | 10    | NA          |
++-------+-------------+-------+-------------+
+| 11    | PC7         | 12    | NA          |
++-------+-------------+-------+-------------+
+| 13    | PC8         | 14    | NA          |
++-------+-------------+-------+-------------+
+| 15    | PA8         | 16    | GND         |
++-------+-------------+-------+-------------+
+| 17    | PA9         | 18    | 3v3         |
++-------+-------------+-------+-------------+
+| 19    | PA10        | 20    | GND         |
++-------+-------------+-------+-------------+
+
+* PB8 is connected to a watchdog buzzer, It needs to be pulsed every 10 seconds to keep the buzzer silent.
+
+IO Header J5
+
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | STM32F427 Functions Pin |
++=======+=============+=========================+=======+=============+=========================+
+| 1     | AGND        | AGND                    | 2     | ADC1_13     | PC3                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 3     | ADC1_12     | PC2                     | 4     | ADC1_11     | PC1                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 5     | I2C_SDA     | PB11                    | 6     | GND         | GND                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 7     | I2C_SCL     | PB10                    | 8     | VCC 3v3     | VCC 3v3                 |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 9     | NC          | NC                      | 10    | NC          | NC                      |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 11    | NC          | NC                      | 12    | NC          | NC                      |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 13    | UART_TX 7   | PE8                     | 14    | GND         | GND                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 15    | UART_RX 7   | PE7                     | 16    | GND         | GND                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 17    | UART_TX 2   | PD5                     | 18    | GND         | GND                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 19    | UART_TX 2   | PD6                     | 20    | GND         | GND                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 21    | NC          | NC                      | 10    | NC          | NC                      |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 23    | NC          | NC                      | 10    | NC          | NC                      |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 25    | SPI1_NIRQ   | PC5                     | 26    | GND         | GND                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 27    | SPI1_CLK    | PA5                     | 28    | SPI1_MISO   | PA6                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 29    | SPI1_CS0    | PA4                     | 30    | SPI1_MOSI   | PA7                     |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 31    | CAN_TX      | PD1                     | 32    | CANH        | NC                      |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+| 33    | CAN_RX      | PD0                     | 34    | CANL        | NC                      |
++-------+-------------+-------------------------+-------+-------------+-------------------------+
+
+
+GPS connector J15
+
++-------+-------------+-------------------------+
+| PIN # | Signal Name | STM32F427 Functions Pin |
++=======+=============+=========================+
+| 1     | V_OUT 5v    | NC                      |
++-------+-------------+-------------------------+
+| 2     | UART1_TX    | PB6                     |
++-------+-------------+-------------------------+
+| 3     | UART1_RX    | PB7                     |
++-------+-------------+-------------------------+
+| 4     | VCC 3v3     | NC                      |
++-------+-------------+-------------------------+
+| 5     | GND         | GND                     |
++-------+-------------+-------------------------+
+
+
+Spektrum connector J3
+
++-------+-------------+-------------------------+
+| PIN # | Signal Name | STM32F427 Functions Pin |
++=======+=============+=========================+
+| 1     | VCC 3v3     | NC                      |
++-------+-------------+-------------------------+
+| 2     | GND         | GND                     |
++-------+-------------+-------------------------+
+| 3     | UART8_RX    | PE0                     |
++-------+-------------+-------------------------+
+
+
+External Clock Sources
+----------------------
+
+STM32F4 has one external oscillator. The frequency of the clock is
+32.768 kHz. The internal 16MHz clock is used as the main clock.
+
+Serial Port
+-----------
+
+96Boards Aerocore2 board has up to 4 U(S)ARTs. The Zephyr console output is
+assigned to USART7. Default settings are 115200 8N1.
+
+I2C
+---
+
+96Boards Aerocore2 board has 1 I2C port. The default I2C mapping for Zephyr is:
+
+- I2C1_SCL : PB10
+- I2C1_SDA : PB11
+
+SPI
+---
+
+96Boards Aerocore2 board has 1 SPI port. The default SPI mapping for Zephyr is:
+
+- SPI1_CS0  : PA4
+- SPI1_SCK  : PA5
+- SPI1_MISO : PA6
+- SPI1_MOSI : PA7
+
+USB
+===
+
+96Boards Aerocore2 board has a USB OTG dual-role device (DRD) controller that
+supports both device and host functions through its mini "OTG" USB connector.
+Only USB device functions are supported in Zephyr at the moment.
+
+Programming and Debugging
+*************************
+
+There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
+bootloader, and another by using the SWD debug port (which requires additional
+hardware). Flashing using the ROM bootloader requires a special activation
+pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader
+supports flashing via USB (DFU), UART, I2C and SPI. You can read more about
+how to enable and use the ROM bootloader by checking the application
+note `AN2606`_, page 109.
+
+Flashing
+========
+
+Installing dfu-util
+-------------------
+
+It is recommended to use at least v0.8 of `dfu-util`_. The package available in
+debian/ubuntu can be quite old, so you might have to build dfu-util from source.
+
+Flashing an Application to 96Boards Aerocore2
+---------------------------------------------
+
+Connect the micro-USB cable to the USB OTG/STM_CONSOLE Aerocore2 port and to your computer.
+The board should power ON. Force the board into DFU mode by keeping the BOOT0
+switch pressed while pressing and releasing the RST switch.
+
+The BOOT button is located at the back-side of the PCB.
+
+Confirm that the board is in DFU mode:
+
+.. code-block:: console
+
+   $ sudo dfu-util -l
+   dfu-util 0.8
+   Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
+   Copyright 2010-2014 Tormod Volden and Stefan Schmidt
+   This program is Free Software and has ABSOLUTELY NO WARRANTY
+   Please report bugs to dfu-util@lists.gnumonks.org
+   Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034"
+   Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034"
+   Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034"
+   Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034"
+   Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN"
+
+You should see following confirmation on your Linux host:
+
+.. code-block:: console
+
+   $ dmesg
+   usb 1-2.1: new full-speed USB device number 14 using xhci_hcd
+   usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11
+   usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+   usb 1-2.1: Product: STM32 BOOTLOADER
+   usb 1-2.1: Manufacturer: STMicroelectronics
+   usb 1-2.1: SerialNumber: 3574364C3034
+
+Then build and flash an application. Here is an example for the
+:ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_aerocore2
+   :goals: build flash
+
+Connect a USB-TTL dongle to the UART_7 header port and to your computer.
+Run your favorite terminal program to listen for output.
+
+.. code-block:: console
+
+   $ minicom -D <tty_device> -b 115200
+
+Replace :code:`<tty_device>` with the port where the board 96Boards Aerocore2
+can be found. For example, under Linux, :code:`/dev/ttyUSB0`.
+The ``-b`` option sets baud rate ignoring the value from config.
+
+Press the Reset button and you should see the following message in your
+terminal:
+
+.. code-block:: console
+
+   Hello World! arm
+
+.. _96Boards website:
+   https://www.96boards.org/product/aerocore2/
+
+.. _STM32F427 on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32f427vi.html
+
+.. _dfu-util:
+   http://dfu-util.sourceforge.net/build.html
+
+.. _AN2606:
+   https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf

boards/96boards/argonkey/96b_argonkey_defconfig

@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_STM32F4X=y
-CONFIG_SOC_STM32F412CX=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/96boards/argonkey/Kconfig.96b_argonkey

@@ -0,0 +1,5 @@
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_96B_ARGONKEY
+	select SOC_STM32F412CX

boards/96boards/argonkey/Kconfig.defconfig

@@ -0,0 +1,23 @@
+# 96Boards Argonkey Board Configuration
+
+# Copyright (c) 2018 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_96B_ARGONKEY
+
+if LSM6DSL
+
+choice LSM6DSL_TRIGGER_MODE
+	default LSM6DSL_TRIGGER_GLOBAL_THREAD
+endchoice
+
+config LSM6DSL_SENSORHUB
+	default y
+
+choice LSM6DSL_EXTERNAL_SENSOR_0
+	default LSM6DSL_EXT0_LIS2MDL
+endchoice
+
+endif # LSM6DSL
+
+endif # BOARD_96B_ARGONKEY

boards/96boards/argonkey/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: 96b_argonkey
+  vendor: 96boards
+  socs:
+    - name: stm32f412cx

boards/96boards/argonkey/doc/index.rst

@@ -0,0 +1,239 @@
+.. _96b_argonkey:
+
+96Boards Argonkey
+#################
+
+Overview
+********
+
+96Boards Argonkey board is based on the ST Microelectronics STM32F412CG
+Cortex M4 CPU.
+
+This board acts as a sensor hub platform for all 96Boards compliant
+family products. It can also be used as a standalone board.
+
+.. figure:: img/96b_argonkey.jpg
+     :align: center
+     :alt: 96Boards Argonkey
+
+     96Boards Argonkey
+
+Hardware
+********
+
+96Boards Argonkey provides the following hardware components:
+
+- STM32F412CG in UFQFPN48 package
+- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
+- 100 MHz max CPU frequency
+- 1.8V work voltage
+- 1024 KB Flash
+- 256 KB SRAM
+- On board sensors:
+
+  - Humidity: STMicro HTS221
+  - Temperature/Pressure: STMicro LPS22HB
+  - ALS: Intersil ISL29034
+  - Proximity: STMicro VL53L0X
+  - Accelerometer/Gyroscope: STMicro LSM6DSL
+  - Geomagnetic: STMicro LIS2MDL
+  - AMR Hall sensor: MRMS501A
+  - Microphone: STMicro MP34DT05
+
+- 2 User LEDs
+- 16 General purpose LEDs
+- GPIO with external interrupt capability
+- UART
+- I2C (3)
+- SPI (1)
+- I2S (1)
+
+Supported Features
+==================
+
+The Zephyr 96b_argonkey board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | system clock                        |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| FLASH     | on-chip    | flash                               |
++-----------+------------+-------------------------------------+
+| SPI       | on-chip    | spi                                 |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
+
+More information about the board can be found at the
+`ARGONKEY website`_.
+
+The default board configuration can be found in
+:zephyr_file:`boards/96boards/argonkey/96b_argonkey_defconfig`
+
+Connections and IOs
+===================
+
+LED
+---
+
+- LED1 / User1 LED = PB2
+- LED2 / User2 LED = PC13
+
+Push buttons
+------------
+
+- BUTTON = RST (BT1)
+- BUTTON = USR (BT2)
+
+System Clock
+============
+
+96Boards Argonkey can be driven by an internal oscillator as well as the main
+PLL clock. In default board configuration, the 16MHz external oscillator is
+used to drive the main PLL clock to generate a System Clock (SYSCLK) at 84MHz.
+On the bus side, AHB clock runs at 84MHz, while APB1/APB2 clock runs at 42MHz.
+
+Serial Port
+===========
+
+On 96Boards Argonkey, Zephyr console output is assigned to USART1.
+Default settings are 115200 8N1.
+
+I2C
+---
+
+96Boards Argonkey board has up to 3 I2Cs. The default I2C mapping is:
+
+- I2C1_SCL  : PB6
+- I2C1_SDA  : PB7
+- I2C2_SCL  : PB10
+- I2C2_SDA  : PB9
+- I2C3_SCL  : PA8
+- I2C3_SCL  : PB4
+
+I2C3 goes to the P2 connector and can be used to attach external sensors.
+It goes to 100Kbit maximum.
+
+SPI
+---
+96Boards Argonkey board has 2 SPIs. SPI1 is used in slave mode as the communication
+bus with the AP. SPI2 is used in master mode to control the LSM6DSL sensor.
+The default SPI mapping is:
+
+- SPI1_NSS  : PA4
+- SPI1_SCK  : PA5
+- SPI1_MISO : PA6
+- SPI1_MOSI : PA7
+- SPI2_NSS  : PB12
+- SPI2_SCK  : PB13
+- SPI2_MISO : PB14
+- SPI2_MOSI : PB15
+
+Programming and Debugging
+*************************
+
+Building
+========
+
+Here is an example for building the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_argonkey
+   :goals: build
+
+Flashing
+========
+
+96Boards Argonkey can be flashed by two methods, one using the ROM
+bootloader and another using the SWD debug port (which requires additional
+hardware).
+
+Flashing using the ROM bootloader requires a special activation pattern,
+which can be triggered by using the BOOT0 pin. The ROM bootloader supports
+flashing via USB (DFU), UART, I2C and SPI, but this document describes the
+UART case only. You can read more about how to enable and use the ROM
+bootloader by checking the application note `AN2606`_ .
+
+Using ROM bootloader:
+---------------------
+
+Hereafter the documents describes basic steps to perform ArgonKey firmware
+flashing on a Linux PC using UART as communication channel.
+
+1. Connect ArgonKey UART to your Linux PC using, for example, a USB-TTL serial
+   cable. The flashing procedure has been tested using a `TTL-232RG`_ cable with
+   FTDI chip. The UART pins on ArgonKey can be found on the P3 low speed
+   expansion connector on the back of the board.
+
+   - GND (black)  to ArgonKey GND (P3.1)
+   - TXD (orange) to ArgonKey UART0_TXD (P3.5)
+   - RXD (yellow) to ArgonKey UART0_RXD (P3.7)
+
+   When the USB cable is inserted to the Linux PC the following device will be
+   created: /dev/ttyUSBx (x is usually '0').
+
+2. Force STM32F412CG to enter in Bootloader mode
+
+   - Connect BOOT0 to 1V8 (link P2.1 to P3.30)
+   - Press and release the RST button
+
+3. Use stm32flash utility to flash the ArgonKey:
+
+.. code-block:: console
+
+    $ stm32flash  -w zephyr.bin -v -g 0x08000000 /dev/ttyUSB0
+
+See References section for more info on `stm32flash`_.
+
+Using SWD debugger:
+-------------------
+
+Select a commercial JTAG/SWD h/w tool and connect it to ArgonKey P4 connector.
+
+The ArgonKey has been tested using the `ST-LINK/V2`_ tool. Once that the tool
+is connected to the PC through USB, it presents itself as a USB composite
+device with mass storage capability. The device can be then mounted in linux
+and the f/w can be actually copied there and will be automatically flashed by
+the ST-LINK onto the ArgonKey.
+
+Example:
+
+.. code-block:: console
+
+   $ mount /dev/sdb /mnt
+   $ cp zephyr.bin /mnt
+   $ umount /mnt
+
+Debugging
+=========
+
+References
+**********
+
+.. target-notes::
+
+.. _ARGONKEY website:
+   https://www.st.com/en/evaluation-tools/steval-mki187v1.html
+
+.. _AN2606:
+   https://www.st.com/resource/en/application_note/cd00167594.pdf
+
+.. _stm32flash:
+   https://sourceforge.net/p/stm32flash/wiki/Home/
+
+.. _ST-LINK/V2:
+   https://www.st.com/en/development-tools/st-link-v2.html
+
+.. _TTL-232RG:
+   http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232RG_CABLES.pdf

boards/96boards/avenger96/96b_avenger96.yaml

@@ -22,4 +22,4 @@ testing:
     - nfc
 ram: 256
 flash: 64
-vendor: arrow
+vendor: 96boards

boards/96boards/avenger96/96b_avenger96_defconfig

@@ -1,6 +1,3 @@
-CONFIG_SOC_SERIES_STM32MP1X=y
-CONFIG_SOC_STM32MP15_M4=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/96boards/avenger96/Kconfig.96b_avenger96

@@ -0,0 +1,5 @@
+# Copyright (c) 2019 Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_96B_AVENGER96
+	select SOC_STM32MP15_M4

boards/96boards/avenger96/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: 96b_avenger96
+  vendor: 96boards
+  socs:
+    - name: stm32mp157cxx

boards/96boards/avenger96/doc/index.rst

@@ -0,0 +1,279 @@
+.. _96b_avenger96:
+
+96Boards Avenger96
+##################
+
+Overview
+********
+
+96Boards Avenger96 board is based on ST Microelectronics STM32MP157A
+multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4
+core. Zephyr OS is ported to run on the Cortex®-M4 core.
+
+- Board features:
+
+  - PMIC: STPMIC1A
+  - RAM: 1024 Mbyte @ 533MHz
+  - Storage:
+
+    - eMMC: v4.51: 8 Gbyte
+    - QSPI: 2Mbyte
+    - EEPROM: 128 byte
+    - microSD Socket: UHS-1 v3.01
+  - Ethernet: 10/100/1000 Mbit/s, IEEE 802.3 Compliant
+  - Wireless:
+
+    - WiFi: 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac
+    - Bluetooth: v4.2 (BR/EDR/BLE)
+  - USB:
+
+    - Host - 2x type A, 2.0 high-speed
+    - OTG: - 1x type micro-AB, 2.0 high-speed
+  - HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4
+  - Connectors:
+
+    - 40-Pin Low Speed Header
+    - 60-Pin High Speed Header
+  - LEDs:
+
+    - 4x Green user LEDs
+    - 1x Blue Bluetooth LED
+    - 1x Yellow WiFi LED
+    - 1x Red power supply LED
+
+.. image:: img/96b_avenger96.jpg
+     :align: center
+     :alt: 96Boards Avenger96
+
+More information about the board can be found at the
+`96Boards website`_.
+
+Hardware
+********
+
+The STM32MP157A SoC provides the following hardware capabilities:
+
+- Core:
+
+  - 32-bit dual-core Arm® Cortex®-A7
+
+    - L1 32-Kbyte I / 32-Kbyte D for each core
+    - 256-Kbyte unified level 2 cache
+    - Arm® NEON™
+
+  - 32-bit Arm® Cortex®-M4 with FPU/MPU
+
+    - Up to 209 MHz (Up to 703 CoreMark®)
+
+- Memories:
+
+  - External DDR memory up to 1 Gbyte.
+  - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM +
+    64 KB of AHB SRAM in backup domain.
+  - Dual mode Quad-SPI memory interface
+  - Flexible external memory controller with up to 16-bit data bus
+
+- Clock management:
+
+  - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz
+    LSI oscillator
+  - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
+  - 6 × PLLs with fractional mode
+
+- General-purpose input/outputs:
+
+  - Up to 176 I/O ports with interrupt capability
+
+- Interconnect matrix
+
+- 3 DMA controllers
+
+- Communication peripherals:
+
+  - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
+  - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
+  - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)
+  - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
+  - SPDIF Rx with 4 inputs
+  - HDMI-CEC interface
+  - MDIO Slave interface
+  - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
+  - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability
+  - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously
+  - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
+  - 8- to 14-bit camera interface up to 140 Mbyte/s
+  - 6 analog peripherals
+  - 2 × ADCs with 16-bit max. resolution.
+  - 1 × temperature sensor
+  - 2 × 12-bit D/A converters (1 MHz)
+  - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6
+    filters
+  - Internal or external ADC/DAC reference VREF+
+
+- Graphics:
+
+  - 3D GPU: Vivante® - OpenGL® ES 2.0
+  - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps
+  - MIPI® DSI 2 data lanes up to 1 GHz each
+
+- Timers:
+
+  - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
+    (incremental) encoder input
+  - 2 × 16-bit advanced motor control timers
+  - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
+  - 5 × 16-bit low-power timers
+  - RTC with sub-second accuracy and hardware calendar
+  - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
+  - 1 × SysTick Cortex®-M4 timer
+
+- Hardware acceleration:
+
+  - HASH (MD5, SHA-1, SHA224, SHA256), HMAC
+  - 2 × true random number generator (3 oscillators each)
+  - 2 × CRC calculation unit
+
+- Debug mode:
+
+  - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
+  - 8-Kbyte embedded trace buffer
+  - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
+
+More information about STM32P157A can be found here:
+
+- `STM32MP157A on www.st.com`_
+- `STM32MP157A reference manual`_
+
+Supported Features
+==================
+
+The Zephyr 96b_avenger96 board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in
+:zephyr_file:`boards/96boards/avenger96/96b_avenger96_defconfig`
+
+
+Connections and IOs
+===================
+
+96Boards Avenger96 Board schematic is available here:
+`Avenger96 board schematics`_.
+
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- UART_7 TX/RX/RTS/CTS : PE8/PE7/PE9/PE10 (UART console)
+- UART_4 TX/RX : PD1/PB2
+
+System Clock
+------------
+
+The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value
+must match the configured mlhclk_ck frequency.
+
+Serial Port
+-----------
+
+96Boards Avenger96 board has 3 U(S)ARTs. The Zephyr console output is assigned
+by default to the RAM console to be dumped by the Linux Remoteproc Framework
+on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to
+UART7 which is disabled by default. UART console can be enabled through
+board's devicetree and 96b_avenger96_defconfig board file (or prj.conf
+project files), and will disable existing RAM console output. Default UART
+console settings are 115200 8N1.
+
+Programming and Debugging
+*************************
+
+The STM32MP157A doesn't have QSPI flash for the Cortex®-M4  and it needs to be
+started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
+Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset.
+The Cortex®-A7 can perform these steps at bootloader level or after the Linux
+system has booted.
+
+The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at
+address 0x00000000 (RETRAM), the vector table should be loaded at this address
+These are the memory mappings for Cortex®-A7 and Cortex®-M4:
+
++------------+-----------------------+------------------------+----------------+
+| Region     | Cortex®-A7            | Cortex®-M4             | Size           |
++============+=======================+========================+================+
+| RETRAM     | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF  | 64KB           |
++------------+-----------------------+------------------------+----------------+
+| MCUSRAM    | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF  | 384KB          |
++------------+-----------------------+------------------------+----------------+
+| DDR        | 0xC0000000-0xFFFFFFFF |                        | up to 1 GB     |
++------------+-----------------------+------------------------+----------------+
+
+
+Refer to `stm32mp157 boot Cortex-M4 firmware`_ wiki page for instruction
+to load and start the Cortex-M4 firmware.
+
+Debugging
+=========
+
+You can debug an application using OpenOCD and GDB. The Solution proposed below
+is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux
+environment. The firmware must first be loaded by the Cortex®-A7. Developer
+then attaches the debugger to the running Zephyr using OpenOCD.
+
+Prerequisite
+------------
+install `stm32mp1 developer package`_.
+
+1) start OpenOCD in a dedicated terminal
+
+   - Start up the  sdk environment::
+
+      source <SDK installation directory>/environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-linux-gnueabi
+
+   - Start OpenOCD::
+
+      ${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_ev1_jlink_jtag.cfg
+
+2) run gdb in Zephyr environment
+
+   .. code-block:: console
+
+      # On Linux
+      cd $ZEPHYR_BASE/samples/hello_world
+      mkdir -p build && cd build
+
+      # Use cmake to configure a Ninja-based build system:
+      cmake -GNinja -DBOARD=96b_avenger96 ..
+
+      # Now run ninja on the generated build system:
+      ninja debug
+
+.. _96Boards website:
+   https://www.96boards.org/product/avenger96/
+
+.. _STM32MP157A on www.st.com:
+   https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157a.html
+
+.. _STM32MP157A reference manual:
+   https://www.st.com/resource/en/reference_manual/DM00327659.pdf
+
+.. _Avenger96 board schematics:
+   https://www.96boards.org/documentation/consumer/avenger96/hardware-docs/files/avenger96-schematics.pdf
+
+.. _stm32mp1 developer package:
+   https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK
+
+.. _stm32mp157 boot Cortex-M4 firmware:
+   https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework

boards/96boards/carbon/96b_carbon_nrf51822.dts

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf51822_qfac.dtsi>
+#include "96b_carbon_nrf51822-pinctrl.dtsi"
+
+/ {
+	model = "Seeed Studio Carbon nRF51 96board";
+	compatible = "seeed,carbon_nrf51";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,bt-mon-uart = &uart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	aliases {
+		watchdog0 = &wdt0;
+	};
+};
+
+&gpiote {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-1 = <&i2c0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart0 {
+	current-speed = <115200>;
+	status = "okay";
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-1 = <&uart0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&spi1 {
+	compatible = "nordic,nrf-spis";
+	status = "okay";
+	def-char = <0x00>;
+
+	pinctrl-0 = <&spi1_default>;
+	pinctrl-names = "default";
+	bt-hci@0 {
+		compatible = "zephyr,bt-hci-spi-slave";
+		reg = <0>;
+		irq-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+	};
+};

boards/96boards/carbon/96b_carbon_nrf51822.yaml

@@ -0,0 +1,13 @@
+identifier: 96b_carbon/nrf51822
+name: 96Boards Carbon (nRF51)
+type: mcu
+arch: arm
+ram: 32
+flash: 256
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - ble
+vendor: seeed

boards/96boards/carbon/96b_carbon_nrf51822_defconfig

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/96boards/carbon/96b_carbon_stm32f401xe.yaml

@@ -0,0 +1,18 @@
+identifier: 96b_carbon/stm32f401xe
+name: 96Boards Carbon
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - gpio
+  - ble
+  - i2c
+  - counter
+  - spi
+  - usb_device
+ram: 96
+flash: 512
+vendor: 96boards

boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_SERIAL=y
+
+# console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# Enable Clocks
+CONFIG_CLOCK_CONTROL=y
+
+# enable pin controller
+CONFIG_PINCTRL=y

boards/96boards/carbon/Kconfig.96b_carbon

@@ -0,0 +1,6 @@
+# Copyright (c) 2016 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_96B_CARBON
+	select SOC_STM32F401XE if BOARD_96B_CARBON_STM32F401XE
+	select SOC_NRF51822_QFAC if BOARD_96B_CARBON_NRF51822

boards/96boards/carbon/Kconfig.defconfig

@@ -0,0 +1,61 @@
+# 96boards Carbon board configuration
+
+# Copyright (c) 2016 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_96B_CARBON_STM32F401XE
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+if BT
+
+config SPI
+	default y
+
+choice BT_HCI_BUS_TYPE
+	default BT_SPI
+endchoice
+
+endif # BT
+
+if NETWORKING
+
+# Re-create the NET_L2_BT dependencies here
+config BT
+	default y
+
+config BT_PERIPHERAL
+	default BT
+
+config BT_CENTRAL
+	default BT
+
+config BT_SMP
+	default BT
+
+config BT_L2CAP_DYNAMIC_CHANNEL
+	default BT
+
+# BT is the only onboard network iface, so use it for IP networking
+# if it's enabled
+
+config NET_L2_BT
+	depends on NET_IPV6
+	default BT
+
+config NET_L2_BT_ZEP1656
+	depends on NET_IPV6
+	default BT
+
+endif # NETWORKING
+
+endif # BOARD_96B_CARBON_STM32F401XE
+
+if BOARD_96B_CARBON_NRF51822
+
+config BT_CTLR
+	default BT
+
+endif # BOARD_96B_CARBON_NRF51822

boards/96boards/carbon/board.cmake

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_BOARD_96B_CARBON_STM32F401XE)
+  board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
+
+  include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
+endif()

boards/96boards/carbon/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: 96b_carbon
+  vendor: 96boards
+  socs:
+  - name: stm32f401xe
+  - name: nrf51822

boards/96boards/carbon/doc/nrf51822.rst

@@ -0,0 +1,170 @@
+.. _96b_carbon_nrf51_board:
+
+96Boards Carbon nRF51
+#####################
+
+Overview
+********
+
+This is the secondary nRF51822 chip on the 96Boards Carbon and provides
+Bluetooth functionality to the main STM32F401RET chip via SPI.
+
+.. note::
+
+   If you're looking to reprogram the main STMicro part, see
+   :ref:`96b_carbon_board`. Users should not use this configuration
+   unless they want to reprogram the secondary chip which provides
+   Bluetooth connectivity.
+
+
+Hardware
+********
+
+The 96Boards Carbon nRF51 has two external oscillators. The frequency
+of the slow clock is 32.768 kHz. The frequency of the main clock is 16
+MHz.
+
+See :ref:`96b_carbon_board` for other general information about the
+board; that configuration is for the same physical board, just a
+different chip.
+
+Supported Features
+==================
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| RTC       | on-chip    | system clock                        |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| FLASH     | on-chip    | flash                               |
++-----------+------------+-------------------------------------+
+| SPIS      | on-chip    | SPI slave                           |
++-----------+------------+-------------------------------------+
+| RADIO     | on-chip    | Bluetooth                           |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in
+:zephyr_file:`boards/96boards/carbon/96b_carbon_nrf51822_defconfig`
+
+Connections and IOs
+===================
+
+SPI
+---
+
+96Boards Carbon nRF51 has one SPI, which for providing Bluetooth
+communication. The default SPI mapping for Zephyr is:
+
+- SPI1_NSS  : P0.25
+- SPI1_SCK  : P0.07
+- SPI1_MISO : P0.30
+- SPI1_MOSI : P0.00
+
+The SWD debug pins are broken out to an external header; all other
+connected pins are to the main STM32F401RET chip.
+
+.. _96b_carbon_nrf51_programming:
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+The 96Boards Carbon nRF51 can be flashed using an external SWD
+debugger, via the debug header labeled "BLE" on the board's
+silkscreen. The header is not populated; 0.1" male header must be
+soldered on first.
+
+.. figure:: img/96b_carbon_nrf51.jpg
+     :align: center
+     :alt: 96Boards Carbon nRF51 Debug
+
+     96Boards Carbon nRF51 Debug
+
+The following example assumes a Zephyr binary ``zephyr.elf`` will be
+flashed to the board.
+
+It uses the `Black Magic Debug Probe`_ as an SWD programmer, which can
+be connected to the BLE debug header using flying leads and its 20 Pin
+JTAG Adapter Board Kit. When plugged into your host PC, the Black
+Magic Debug Probe enumerates as a USB serial device as documented on
+its `Getting started page`_.
+
+It also uses the GDB binary provided with the Zephyr SDK,
+``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC
+ARM Embedded, can be used as well.
+
+.. code-block:: console
+
+   $ arm-zephyr-eabi-gdb -q zephyr.elf
+   (gdb) target extended-remote /dev/ttyACM0
+   Remote debugging using /dev/ttyACM0
+   (gdb) monitor swdp_scan
+   Target voltage: 3.3V
+   Available Targets:
+   No. Att Driver
+    1      nRF51
+   (gdb) attach 1
+   Attaching to Remote target
+   0xabcdef12 in ?? ()
+   (gdb) load
+
+Debugging
+=========
+
+After you've flashed the chip, you can keep debugging using the same
+GDB instance. To reattach, just follow the same steps above, but don't
+run "load". You can then debug as usual with GDB. In particular, type
+"run" at the GDB prompt to restart the program you've flashed.
+
+As an aid to debugging, this board configuration directs a console
+output to a currently unused pin connected to the STM32F401RET. Users
+who are experienced in electronics rework can remove a resistor (R22)
+on the board and attach a wire to the nRF51822's UART output.
+
+.. _96b_carbon_nrf51_bluetooth:
+
+Providing Bluetooth to 96b_carbon
+*********************************
+
+This ``96b_carbon/nrf51822`` Zephyr board configuration can be used to provide
+Bluetooth functionality from the secondary nRF51822 chip to the
+primary STM32F401RE chip on the :ref:`96b_carbon_board`.
+
+To do this, build the ``samples/bluetooth/hci_spi/`` application
+provided with Zephyr with ``BOARD=96b_carbon/nrf51822``, then flash it to
+the nRF51822 chip using the instructions :ref:`above
+<96b_carbon_nrf51_programming>`. (For instructions on how to build a
+Zephyr application, see :ref:`build_an_application`.)
+
+.. warning::
+
+   Be sure to flash the hci_spi application to the nRF51822 chip and
+   not to the main STM32F401RET chip.  While both chips are supported
+   by Zephyr, the hci_spi application providing Bluetooth support will
+   only run on the nRF51822 chip.
+
+References
+**********
+
+- `Board documentation from 96Boards`_
+- `nRF51822 information from Nordic Semiconductor`_
+
+.. _Black Magic Debug Probe:
+   https://github.com/blacksphere/blackmagic/wiki
+
+.. _Getting started page:
+   https://github.com/blacksphere/blackmagic/wiki/Getting-Started
+
+.. _Board documentation from 96Boards:
+   http://www.96boards.org/product/carbon/
+
+.. _nRF51822 information from Nordic Semiconductor:
+   https://www.nordicsemi.com/eng/Products/Bluetooth-low-energy/nRF51822

boards/96boards/carbon/doc/stm32f401xe.rst

@@ -0,0 +1,383 @@
+.. _96b_carbon_board:
+
+96Boards Carbon
+###############
+
+Overview
+********
+
+The 96Boards is based on the STMicroelectronics STM32F401RET Cortex-M4 CPU and
+also contains a nRF51822 chip connected over SPI for BLE connectivity.
+
+The 96Boards Carbon board is built with two chips: an STMicroelectronics
+STM32F401RET Cortex-M4 CPU and an nRF51822 chip connected to
+the Cortex-M4 CPU over SPI for Bluetooth LE connectivity.  Even though
+both chips exist on the same physical board, they must be programmed
+separately:
+
+- The ``96b_carbon/stm32f401xe`` configuration is used when developing programs for
+  the main chip on the board, the STM32F401RET. Users will likely want to
+  write applications targeting this chip, using the ``96b_carbon``
+  configuration, since it is connected to all of the breakout
+  I/O headers.
+
+- The ``96b_carbon/nrf51822`` configuration should be used for programming
+  the secondary nRF51822 chip. Most users will likely not develop
+  applications for this chip, since Zephyr already provides a
+  sample application that can be flashed onto the nRF51822
+  to provide Bluetooth functionality to applications on the main
+  STM32F401RET chip.
+
+For instructions on how to set up the nRF51822 to develop Bluetooth
+applications, see :ref:`96b_carbon_nrf51_bluetooth`.
+
+After you have flashed your nRF51, you can perform basic validation
+of this Bluetooth setup using the instructions
+:ref:`below <96b_carbon_verify_bluetooth>`.
+
+.. figure:: img/96b_carbon.jpg
+     :align: center
+     :alt: 96Boards Carbon
+
+     96Boards Carbon
+
+Hardware
+********
+
+96Boards Carbon provides the following hardware components:
+
+- STM32F401RET6 in LQFP64 package
+- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
+- 84 MHz max CPU frequency
+- VDD from 1.7 V to 3.6 V
+- 512 KB Flash
+- 96 KB SRAM
+- GPIO with external interrupt capability
+- 12-bit ADC with 16 channels
+- RTC
+- Advanced-control Timer
+- General Purpose Timers (7)
+- Watchdog Timers (2)
+- USART/UART (4)
+- I2C (3)
+- SPI (3)
+- SDIO
+- USB 2.0 OTG FS
+- DMA Controller
+- Bluetooth LE over SPI, provided by nRF51822
+
+More information about STM32F401RE can be found here:
+       - `STM32F401RE on www.st.com`_
+       - `STM32F401 reference manual`_
+
+Supported Features
+==================
+
+The Zephyr ``96b_carbon/stm32f401xe`` board configuration supports the following
+hardware features:
+
++------------+------------+-------------------------------------+
+| Interface  | Controller | Driver/Component                    |
++============+============+=====================================+
+| NVIC       | on-chip    | nested vector interrupt controller  |
++------------+------------+-------------------------------------+
+| SYSTICK    | on-chip    | system clock                        |
++------------+------------+-------------------------------------+
+| UART       | on-chip    | serial port                         |
++------------+------------+-------------------------------------+
+| GPIO       | on-chip    | gpio                                |
++------------+------------+-------------------------------------+
+| PINMUX     | on-chip    | pinmux                              |
++------------+------------+-------------------------------------+
+| FLASH      | on-chip    | flash                               |
++------------+------------+-------------------------------------+
+| SPI        | on-chip    | spi                                 |
++------------+------------+-------------------------------------+
+| I2C        | on-chip    | i2c                                 |
++------------+------------+-------------------------------------+
+| USB OTG FS | on-chip    | USB device                          |
++------------+------------+-------------------------------------+
+
+More details about the board can be found at `96Boards website`_.
+
+The default configuration can be found in
+:zephyr_file:`boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig`
+
+Connections and IOs
+===================
+
+LED
+---
+
+- LED1 / User1 LED = PD2
+- LED2 / User2 LED = PA15
+- LED3 / BT LED = PB5
+- LED4 / Power LED = VCC
+
+Push buttons
+------------
+
+- BUTTON = BOOT0 (SW1)
+- BUTTON = RST
+
+External Connectors
+-------------------
+
+Low Speed Header
+
++--------+-------------+----------------------+
+| PIN #  | Signal Name | STM32F401 Functions  |
++========+=============+======================+
+| 1      | UART2_CTS   | PA0                  |
++--------+-------------+----------------------+
+| 3      | UART2_TX    | PA2                  |
++--------+-------------+----------------------+
+| 5      | UART2_RX    | PA3                  |
++--------+-------------+----------------------+
+| 7      | UART2_RTS   | PA1                  |
++--------+-------------+----------------------+
+| 9      | GND         | GND                  |
++--------+-------------+----------------------+
+| 11     | USB5V       | USB5V                |
++--------+-------------+----------------------+
+| 13     | AIN12       | PC2                  |
++--------+-------------+----------------------+
+| 15     | AIN14       | PC4                  |
++--------+-------------+----------------------+
+| 17     | UART6_TX    | PC6                  |
++--------+-------------+----------------------+
+| 19     | GPIO        | PC8                  |
++--------+-------------+----------------------+
+| 21     | I2C1_SCL    | PB6                  |
++--------+-------------+----------------------+
+| 23     | I2C1_SCA    | PB7                  |
++--------+-------------+----------------------+
+| 25     | I2C2_SCA    | PB3                  |
++--------+-------------+----------------------+
+| 27     | I2C2_SCL    | PB10                 |
++--------+-------------+----------------------+
+| 29     | RST_BTN     | RST_BTN              |
++--------+-------------+----------------------+
+
++--------+-------------+----------------------+
+| PIN #  | Signal Name | STM32F401 Functions  |
++========+=============+======================+
+| 2      | SPI2_SS     | PB12                 |
++--------+-------------+----------------------+
+| 4      | SPI2_MOSI   | PB15                 |
++--------+-------------+----------------------+
+| 6      | SPI2_MISO   | PB14                 |
++--------+-------------+----------------------+
+| 8      | SPI2_SCK    | PB13                 |
++--------+-------------+----------------------+
+| 10     | GND         | GND                  |
++--------+-------------+----------------------+
+| 12     | VCC2        | VCC2                 |
++--------+-------------+----------------------+
+| 14     | AIN13       | PC3                  |
++--------+-------------+----------------------+
+| 16     | AIN15       | PC5                  |
++--------+-------------+----------------------+
+| 18     | UART6_RX    | PC7                  |
++--------+-------------+----------------------+
+| 20     | GPIO        | PC9                  |
++--------+-------------+----------------------+
+| 22     | I2C1_SCL    | PB8                  |
++--------+-------------+----------------------+
+| 24     | I2C1_SDA    | PB9                  |
++--------+-------------+----------------------+
+| 26     | AIN10       | PC0                  |
++--------+-------------+----------------------+
+| 28     | AIN11       | PC1                  |
++--------+-------------+----------------------+
+| 30     | NC          | NC                   |
++--------+-------------+----------------------+
+
+More detailed information about the connectors can be found in
+`96Boards IE Specification`_.
+
+External Clock Sources
+----------------------
+
+STM32F4 has two external oscillators. The frequency of the slow clock is
+32.768 kHz. The frequency of the main clock is 16 MHz.
+
+Serial Port
+-----------
+
+96Boards Carbon board has up to 4 U(S)ARTs. The Zephyr console output is
+assigned to USART1. Default settings are 115200 8N1.
+
+I2C
+---
+
+96Boards Carbon board has up to 2 I2Cs. The default I2C mapping for Zephyr is:
+
+- I2C1_SCL : PB6
+- I2C1_SDA : PB7
+- I2C2_SCL : PB10
+- I2C2_SDA : PB3
+
+SPI
+---
+
+96Boards Carbon board has up to 2 SPIs. SPI1 is used for Bluetooth communication
+over HCI. The default SPI mapping for Zephyr is:
+
+- SPI1_NSS  : PA4
+- SPI1_SCK  : PA5
+- SPI1_MISO : PA6
+- SPI1_MOSI : PA7
+- SPI2_NSS  : PB12
+- SPI2_SCK  : PB13
+- SPI2_MISO : PB14
+- SPI2_MOSI : PB15
+
+USB
+===
+
+96Boards Carbon board has a USB OTG dual-role device (DRD) controller that
+supports both device and host functions through its mini "OTG" USB connector.
+Only USB device functions are supported in Zephyr at the moment.
+
+- USB_DM : PA11
+- USB_DP : PA12
+
+Programming and Debugging
+*************************
+
+There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
+bootloader, and another by using the SWD debug port (which requires additional
+hardware). Flashing using the ROM bootloader requires a special activation
+pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader
+supports flashing via USB (DFU), UART, I2C and SPI. You can read more about
+how to enable and use the ROM bootloader by checking the application
+note `AN2606`_, page 109.
+
+Flashing
+========
+
+Installing dfu-util
+-------------------
+
+It is recommended to use at least v0.8 of `dfu-util`_. The package available in
+debian/ubuntu can be quite old, so you might have to build dfu-util from source.
+
+Flashing an Application to 96Boards Carbon
+------------------------------------------
+
+Connect the micro-USB cable to the USB OTG Carbon port and to your computer.
+The board should power ON. Force the board into DFU mode by keeping the BOOT0
+switch pressed while pressing and releasing the RST switch.
+
+Confirm that the board is in DFU mode:
+
+.. code-block:: console
+
+   $ sudo dfu-util -l
+   dfu-util 0.8
+   Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
+   Copyright 2010-2014 Tormod Volden and Stefan Schmidt
+   This program is Free Software and has ABSOLUTELY NO WARRANTY
+   Please report bugs to dfu-util@lists.gnumonks.org
+   Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034"
+   Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034"
+   Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034"
+   Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034"
+   Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN"
+
+You should see following confirmation on your Linux host:
+
+.. code-block:: console
+
+   $ dmesg
+   usb 1-2.1: new full-speed USB device number 14 using xhci_hcd
+   usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11
+   usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+   usb 1-2.1: Product: STM32 BOOTLOADER
+   usb 1-2.1: Manufacturer: STMicroelectronics
+   usb 1-2.1: SerialNumber: 3574364C3034
+
+Then build and flash an application. Here is an example for the
+:ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_carbon/stm32f401xe
+   :goals: build flash
+
+Connect the micro-USB cable to the USB UART (FTDI) port and to your computer.
+Run your favorite terminal program to listen for output.
+
+.. code-block:: console
+
+   $ minicom -D <tty_device> -b 115200
+
+Replace :code:`<tty_device>` with the port where the board 96Boards Carbon
+can be found. For example, under Linux, :code:`/dev/ttyUSB0`.
+The ``-b`` option sets baud rate ignoring the value from config.
+
+Press the Reset button and you should see the following message in your
+terminal:
+
+.. code-block:: console
+
+   Hello World! arm
+
+.. _96b_carbon_verify_bluetooth:
+
+Verifying Bluetooth Functionality
+---------------------------------
+
+This section contains instructions for verifying basic Bluetooth
+functionality on the board. For help on Zephyr applications
+in general, see :ref:`build_an_application`.
+
+1. Flash the nRF51 with the hci_spi sample application as described in
+   :ref:`96b_carbon_nrf51_bluetooth`.
+
+#. Install the dfu-util flashing app, as described above.
+
+#. Build and flash the ``samples/bluetooth/ipsp`` application for
+   96b_carbon. See the instructions above for how to put your board
+   into DFU mode if you haven't done this before:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/bluetooth/ipsp
+      :board: 96b_carbon/stm32f401xe
+      :goals: build flash
+
+#. Refer to the instructions in :ref:`bluetooth-ipsp-sample` for how
+   to verify functionality.
+
+Congratulations! Your 96Boards Carbon now has Bluetooth
+connectivity. Refer to :ref:`bluetooth` for additional information on
+further Bluetooth application development.
+
+Debugging
+=========
+
+The ``96b_carbon/stm32f401xe`` board can be debugged by installing a 100 mil (0.1 inch) header
+into the header at the bottom right hand side of the board, and
+attaching an SWD debugger to the 3V3 (3.3V), GND, CLK, DIO, and RST
+pins on that header. Then apply power to the 96Boards Carbon via one
+of its USB connectors. You can now attach your debugger to the
+STM32F401RET using an SWD scan.
+
+.. _dfu-util:
+   http://dfu-util.sourceforge.net/build.html
+
+.. _AN2606:
+   https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf
+
+.. _96Boards website:
+   http://www.96boards.org/documentation
+
+.. _STM32F401RE on www.st.com:
+   https://www.st.com/en/microcontrollers/stm32f401re.html
+
+.. _STM32F401 reference manual:
+   https://www.st.com/resource/en/reference_manual/dm00096844.pdf
+
+.. _96Boards IE Specification:
+    https://linaro.co/ie-specification

boards/96boards/carbon/pre_dt_board.cmake

@@ -0,0 +1,8 @@
+# Copyright (c) 2022 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+if("${BOARD_IDENTIFIER}" STREQUAL "/nrf51822")
+  # Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
+  # - power@40000000 & clock@40000000 & nrf-mpu@40000000
+  list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
+endif()

boards/96boards/index.rst

@@ -0,0 +1,10 @@
+.. _boards-96boards:
+
+96Boards
+########
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml

@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2019, Linaro Ltd.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: 96b_meerkat96/mcimx7d/m4
+name: 96Boards Meerkat96
+type: mcu
+arch: arm
+ram: 32
+flash: 32
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - gpio
+  - shell
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: novtech

boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig

@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2019, Linaro Ltd.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# enable uart driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# pinctrl
+CONFIG_PINCTRL=y
+
+CONFIG_XIP=y

boards/96boards/meerkat96/Kconfig.96b_meerkat96

@@ -0,0 +1,7 @@
+# Copyright (c) 2019, Linaro Ltd.
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_96B_MEERKAT96
+	select SOC_PART_NUMBER_MCIMX7D5EVM10SC
+	select SOC_MCIMX7D_M4 if BOARD_96B_MEERKAT96_MCIMX7D_M4

boards/96boards/meerkat96/Kconfig.defconfig

@@ -0,0 +1,15 @@
+# 96Boards Meerkat96 board
+
+# Copyright (c) 2019, Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_96B_MEERKAT96
+
+if !XIP
+config FLASH_SIZE
+	default 0
+config FLASH_BASE_ADDRESS
+	default 0
+endif
+
+endif # BOARD_96B_MEERKAT96

boards/96boards/meerkat96/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: 96b_meerkat96
+  vendor: 96boards
+  socs:
+    - name: mcimx7d

boards/96boards/meerkat96/doc/index.rst

@@ -0,0 +1,325 @@
+.. _96b_meerkat96:
+
+96Boards Meerkat96
+##################
+
+Overview
+********
+
+96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor,
+composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
+Zephyr OS is ported to run on the Cortex®-M4 core.
+
+- Board features:
+
+  - RAM: 512 Mbyte
+  - Storage:
+
+    - microSD Socket
+  - Wireless:
+
+    - WiFi: 2.4GHz IEEE 802.11b/g/n
+    - Bluetooth: v4.1 (BR/EDR)
+  - USB:
+
+    - Host - 2x type A
+    - OTG: - 1x type micro-B
+  - HDMI
+  - Connectors:
+
+    - 40-Pin Low Speed Header
+    - 60-Pin High Speed Header
+  - LEDs:
+
+    - 4x Green user LEDs
+    - 1x Blue Bluetooth LED
+    - 1x Yellow WiFi LED
+
+.. image:: img/96b_meerkat96.jpg
+   :align: center
+   :alt: 96Boards Meerkat96
+
+More information about the board can be found at the
+`96Boards website`_.
+
+Hardware
+********
+
+The i.MX7 SoC provides the following hardware capabilities:
+
+- Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
+
+- Memory
+
+  - External DDR memory up to 1 Gbyte
+  - Internal RAM -> A7: 256KB SRAM
+  - Internal RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
+
+- Display
+
+  - RGB 1920x1080x24bpp
+  - 4-wire Resistive touch
+
+- Multimedia
+
+  - 1x Camera Parallel Interface
+  - 1x Analog Audio Line in (Stereo)
+  - 1x Analog Audio Mic in (Mono)
+  - 1x Analog Audio Headphone out (Stereo)
+
+- Connectivity
+
+  - USB 2.0 OTG (High Speed)
+  - USB 2.0 host (High Speed)
+  - 10/100 Mbit/s Ethernet PHY
+  - 4x I2C
+  - 4x SPI
+  - 7x UART
+  - 1x IrDA
+  - 20x PWM
+  - Up to 125 GPIO
+  - 4x Analog Input (12 Bit)
+  - 2x SDIO/SD/MMC (8 Bit)
+  - 2x CAN
+
+More information about the i.MX7 SoC can be found here:
+
+- `i.MX 7 Series Website`_
+- `i.MX 7 Dual Datasheet`_
+- `i.MX 7 Dual Reference Manual`_
+
+Supported Features
+==================
+
+The Zephyr 96b_meerkat96 board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+
+	:zephyr_file:`boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig`
+
+Other hardware features are not currently supported by the port.
+
+Connections and IOs
+===================
+
+96Boards Meerkat96 board was tested with the following pinmux controller
+configuration.
+
++---------------+-----------------+---------------------------+
+| Board Name    | SoC Name        | Usage                     |
++===============+=================+===========================+
+| UART_1 RXD    | UART1_TXD       | UART Console              |
++---------------+-----------------+---------------------------+
+| UART_1 TXD    | UART1_RXD       | UART Console              |
++---------------+-----------------+---------------------------+
+| LED_R1        | GPIO1_IO04      | LED0                      |
++---------------+-----------------+---------------------------+
+| LED_R2        | GPIO1_IO05      | LED1                      |
++---------------+-----------------+---------------------------+
+| LED_R3        | GPIO1_IO06      | LED2                      |
++---------------+-----------------+---------------------------+
+| LED_R4        | GPIO1_IO07      | LED3                      |
++---------------+-----------------+---------------------------+
+
+System Clock
+============
+
+The M4 Core is configured to run at a 200 MHz clock speed.
+
+Serial Port
+===========
+
+The iMX7D SoC has seven UARTs. UART_1 is configured for the console and
+the remaining are not used/tested.
+
+Programming and Debugging
+*************************
+
+The 96Boards Meerkat96 board doesn't have QSPI flash for the M4 and it needs
+to be started by the A7 core. The A7 core is responsible to load the M4 binary
+application into the RAM, put the M4 in reset, set the M4 Program Counter and
+Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at
+bootloader level or after the Linux system has booted.
+
+The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4:
+
++------------+-----------------------+------------------------+-----------------------+----------------------+
+| Region     | Cortex-A7             | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus)  | Size                 |
++============+=======================+========================+=======================+======================+
+| DDR        | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF  | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) |
++------------+-----------------------+------------------------+-----------------------+----------------------+
+| OCRAM      | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF  | 0x00900000-0x0091FFFF | 128KB                |
++------------+-----------------------+------------------------+-----------------------+----------------------+
+| TCMU       | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF  |                       | 32KB                 |
++------------+-----------------------+------------------------+-----------------------+----------------------+
+| TCML       | 0x007F8000-0x007FFFFF |                        | 0x1FFF8000-0x1FFFFFFF | 32KB                 |
++------------+-----------------------+------------------------+-----------------------+----------------------+
+| OCRAM_S    | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF  | 0x00000000-0x00007FFF | 32KB                 |
++------------+-----------------------+------------------------+-----------------------+----------------------+
+| QSPI Flash |                       |                        | 0x08000000-0x0BFFFFFF | 64MB                 |
++------------+-----------------------+------------------------+-----------------------+----------------------+
+
+For more information about memory mapping see the
+`i.MX 7 Dual Reference Manual`_  (section 2.1.2 and 2.1.3), and the
+`Toradex Wiki`_.
+
+At compilation time you have to choose which RAM will be used. This
+configuration is done in the file :zephyr_file:`boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts`
+with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties.
+The available configurations are:
+
+.. code-block:: none
+
+   "zephyr,flash"
+   - &ddr_code
+   - &tcml_code
+   - &ocram_code
+   - &ocram_s_code
+   - &ocram_pxp_code
+   - &ocram_epdc_code
+
+   "zephyr,sram"
+   - &ddr_sys
+   - &tcmu_sys
+   - &ocram_sys
+   - &ocram_s_sys
+   - &ocram_pxp_sys
+   - &ocram_epdc_sys
+
+
+Below you will find the instructions to load and run Zephyr on M4 from
+A7 using u-boot.
+
+Copy the compiled zephyr.bin to the first FAT partition of the SD card and
+plug into the board. Power it up and stop the u-boot execution.
+Set the u-boot environment variables and run the zephyr.bin from the
+appropriated memory configured in the Zephyr compilation:
+
+.. code-block:: console
+
+   setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr'
+   # TCML
+   setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000'
+   setenv bootm4tcml 'run m4tcml && run bootm4'
+   run bootm4tcml
+   # TCMU
+   setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000'
+   setenv bootm4tcmu 'run m4tcmu && run bootm4'
+   run bootm4tcmu
+   # OCRAM
+   setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000'
+   setenv bootm4ocram 'run m4ocram && run bootm4'
+   run bootm4ocram
+   # OCRAM_S
+   setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000'
+   setenv bootm4ocrams 'run m4ocrams && run bootm4'
+   run bootm4ocrams
+   # DDR
+   setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000'
+   setenv bootm4ddr 'run m4ddr && run bootm4'
+   run bootm4ddr
+
+Debugging
+=========
+
+96Boards Meerkat96 board can be debugged by connecting an external JLink
+JTAG debugger to the J4 debug connector. Then download and install
+`J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_.
+
+To run Zephyr Binary using J-Link create the following script in order to
+get the Program Counter and Stack Pointer from zephyr.bin.
+
+get-pc-sp.sh:
+.. code-block:: console
+
+   #!/bin/sh
+
+   firmware=$1
+
+   pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}')
+   sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}')
+
+   echo pc=$pc
+   echo sp=$sp
+
+
+Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin``
+.. code-block:: console
+
+   pc=00900f01
+   sp=00905020
+
+Plug in the J-Link into the board and PC and run the J-Link command line tool:
+
+.. code-block:: console
+
+   /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript
+
+The following steps are necessary to run the zephyr.bin:
+
+1. Put the M4 core in reset
+2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR)
+3. Set PC (Program Counter)
+4. Set SP (Stack Pointer)
+5. Get the M4 core out of reset
+
+Issue the following commands inside J-Link commander:
+
+.. code-block:: console
+
+   w4 0x3039000C 0xAC
+   loadfile zephyr.bin,0x00900000
+   w4 0x00180000 00900f01
+   w4 0x00180004 00905020
+   w4 0x3039000C 0xAA
+
+With these mechanisms, applications for the ``96b_meerkat96`` board
+configuration can be built and debugged in the usual way (see
+:ref:`build_an_application` and :ref:`application_run` for more details).
+
+References
+==========
+
+- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_
+- `J-Link iMX7D Instructions`_
+
+.. _96Boards website:
+   https://www.96boards.org/product/imx7-96/
+
+.. _i.MX 7 Series Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1
+
+.. _i.MX 7 Dual Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf
+
+.. _i.MX 7 Dual Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=IMX7DRM
+
+.. _J-Link Tools:
+   https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack
+
+.. _NXP iMX7D Connect CortexM4.JLinkScript:
+   https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript
+
+.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors:
+   https://www.nxp.com/docs/en/application-note/AN5317.pdf
+
+.. _J-Link iMX7D Instructions:
+   https://wiki.segger.com/IMX7D
+
+.. _Toradex Wiki:
+   https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas

boards/96boards/neonkey/96b_neonkey_defconfig

@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_STM32F4X=y
-CONFIG_SOC_STM32F411XE=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/96boards/neonkey/Kconfig.96b_neonkey

@@ -0,0 +1,5 @@
+# Copyright (c) 2017 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_96B_NEONKEY
+	select SOC_STM32F411XE

boards/96boards/neonkey/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# 96Boards Neonkey Board Configuration
+
+# Copyright (c) 2017 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_96B_NEONKEY
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_96B_NEONKEY

boards/96boards/neonkey/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: 96b_neonkey
+  vendor: 96boards
+  socs:
+    - name: stm32f411xe

boards/96boards/neonkey/doc/index.rst

@@ -0,0 +1,232 @@
+.. _96b_neonkey:
+
+96Boards Neonkey
+################
+
+Overview
+********
+
+96Boards Neonkey board is based on the STMicroelectronics STM32F411CE
+Cortex M4 CPU.
+
+.. figure:: img/96b_neonkey.jpg
+     :align: center
+     :alt: 96Boards Neonkey
+
+     96Boards Neonkey
+
+This board acts as a sensor hub platform for all 96Boards compliant
+family products. It can also be used as a standalone board.
+
+Hardware
+********
+
+96Boards Neonkey provides the following hardware components:
+
+- STM32F411CE in UFQFPN48 package
+- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
+- 84 MHz max CPU frequency
+- 1.8V work voltage
+- 512 KB Flash
+- 128 KB SRAM
+- On board sensors:
+
+  - Temperature/Humidity: SI7034-A10
+  - Pressure: BMP280
+  - ALS/Proximity: RPR-0521RS
+  - Geomagnetic: BMM150
+  - Accelerometer/Gyroscope: BMI160
+  - AMR Hall sensor: MRMS501A
+  - Microphone: SPK0415HM4H-B
+
+- 4 User LEDs
+- 15 General purpose LEDs
+- GPIO with external interrupt capability
+- I2C (3)
+- SPI (1)
+- I2S (1)
+
+Supported Features
+==================
+
+The Zephyr 96b_neonkey board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | system clock                        |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| FLASH     | on-chip    | flash                               |
++-----------+------------+-------------------------------------+
+| SPI       | on-chip    | spi                                 |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
+
+More details about the board can be found at `96Boards website`_.
+
+The default board configuration can be found in
+:zephyr_file:`boards/96boards/neonkey/96b_neonkey_defconfig`
+
+Connections and IOs
+===================
+
+LED
+---
+
+- LED1 / User1 LED = PB12
+- LED2 / User2 LED = PB13
+- LED3 / User3 LED = PB14
+- LED4 / User4 LED = PB15
+
+Push buttons
+------------
+
+- BUTTON = RST (SW1)
+- BUTTON = USR (SW2)
+
+System Clock
+============
+
+96Boards Neonkey can be driven by an internal oscillator as well as the main
+PLL clock. By default System clock is sourced by PLL clock at 84MHz, driven
+by internal oscillator.
+
+Serial Port
+===========
+
+On 96Boards Neonkey Zephyr console output is assigned to USART1.
+Default settings are 115200 8N1.
+
+I2C
+---
+
+96Boards Neonkey board has up to 3 I2Cs. The default I2C mapping for Zephyr is:
+
+- I2C1_SCL : PB6
+- I2C1_SDA : PB7
+- I2C2_SCL : PB10
+- I2C2_SDA : PB3
+- I2C3_SCL : PA8
+- I2C3_SCL : PB4
+
+SPI
+---
+
+96Boards Neonkey board has one SPI. The default SPI mapping for Zephyr is:
+
+- SPI1_NSS  : PA4
+- SPI1_SCK  : PA5
+- SPI1_MISO : PA6
+- SPI1_MOSI : PA7
+
+Programming and Debugging
+*************************
+
+Building
+========
+
+Here is an example for building the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_neonkey
+   :goals: build
+
+Flashing
+========
+
+96Boards Neonkey can be flashed by two methods, one using the ROM
+bootloader and another using the SWD debug port (which requires additional
+hardware).
+
+Using ROM bootloader:
+---------------------
+
+ROM bootloader can be triggered by the following pattern:
+
+1. Connect BOOT0 to VDD (link JTAG pins 1 and 5 on P4 header)
+2. Press and hold the USR button
+3. Press and release the RST button
+
+More detailed information on activating the ROM bootloader can be found in
+Chapter 29 of Application note `AN2606`_. The ROM bootloader supports flashing
+via UART, I2C and SPI protocols.
+
+For flashing, `stm32flash`_ command line utility can be used. The following
+command will flash the ``zephyr.bin`` binary to the Neonkey board using UART
+and starts its execution:
+
+.. code-block:: console
+
+   $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyS0
+
+.. note::
+   The above command assumes that Neonkey board is connected to
+   serial port ``/dev/ttyS0``.
+
+Using SWD debugger:
+-------------------
+
+For flashing via SWD debug port, 0.1" male header must be soldered at P4
+header available at the bottom of the board, near RST button.
+
+Use the `Black Magic Debug Probe`_ as an SWD programmer, which can
+be connected to the P4 header using its flying leads and its 20 Pin
+JTAG Adapter Board Kit. When plugged into your host PC, the Black
+Magic Debug Probe enumerates as a USB serial device as documented on
+its `Getting started page`_.
+
+It also uses the GDB binary provided with the Zephyr SDK,
+``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC
+ARM Embedded, can be used as well.
+
+.. code-block:: console
+
+   $ arm-zephyr-eabi-gdb -q zephyr.elf
+   (gdb) target extended-remote /dev/ttyACM0
+   Remote debugging using /dev/ttyACM0
+   (gdb) monitor swdp_scan
+   Target voltage: 1.8V
+   Available Targets:
+   No. Att Driver
+    1      STM32F4xx
+   (gdb) attach 1
+   Attaching to Remote target
+   0x080005d0 in ?? ()
+   (gdb) load
+
+Debugging
+=========
+
+After flashing 96Boards Neonkey, it can be debugged using the same
+GDB instance. To reattach, just follow the same steps above, till
+"attach 1". You can then debug as usual with GDB. In particular, type
+"run" at the GDB prompt to restart the program you've flashed.
+
+References
+**********
+
+.. _96Boards website:
+   https://www.96boards.org/product/neonkey/
+
+.. _AN2606:
+   https://www.st.com/resource/en/application_note/cd00167594.pdf
+
+.. _stm32flash:
+   https://sourceforge.net/p/stm32flash/wiki/Home/
+
+.. _Black Magic Debug Probe:
+   https://github.com/blacksphere/blackmagic/wiki
+
+.. _Getting started page:
+   https://github.com/blacksphere/blackmagic/wiki/Getting-Started

boards/96boards/nitrogen/96b_nitrogen_defconfig

@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_NRF52X=y
-CONFIG_SOC_NRF52832_QFAA=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/96boards/nitrogen/Kconfig.96b_nitrogen

@@ -0,0 +1,7 @@
+# 96Boards NITROGEN board configuration
+
+# Copyright (c) 2016 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_96B_NITROGEN
+	select SOC_NRF52832_QFAA

boards/96boards/nitrogen/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# 96Boards NITROGEN board configuration
+
+# Copyright (c) 2016 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_96B_NITROGEN
+
+config BT_CTLR
+	default BT
+
+endif # BOARD_96B_NITROGEN

boards/96boards/nitrogen/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: 96b_nitrogen
+  vendor: 96boards
+  socs:
+  - name: nrf52832

boards/96boards/nitrogen/doc/index.rst

@@ -0,0 +1,329 @@
+.. _96b_nitrogen_board:
+
+96Boards Nitrogen
+#################
+
+Overview
+********
+
+The 96Boards Nitrogen hardware provides support for the Nordic Semiconductor
+nRF52832 ARM Cortex-M4F CPU.
+
+.. figure:: img/96b_nitrogen.jpg
+     :align: center
+     :alt: 96Boards Nitrogen
+
+     96Boards Nitrogen
+
+More information about the board can be found at the `seeed BLE Nitrogen`_
+website. The `Nordic Semiconductor Infocenter`_ contains the processor's
+information and the datasheet.
+
+Hardware
+********
+
+96Boards Nitrogen provides the following hardware components:
+
+- nRF52832 microcontroller with 512kB Flash, 64kB RAM
+- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
+- Bluetooth LE
+- NFC
+- LPC11U35 on board SWD debugger
+
+  - SWD debugger firmware
+  - USB to UART
+  - Drag and Drop firmware upgrade
+
+- 7 LEDs
+
+  - USR1, BT, PWR, CDC, DAP, MSD, Battery charge
+
+- SWD debug connectors
+
+  - nRF52832 SWD connector
+  - nRF52832 Uart connector
+
+- On board chip antenna
+- 1.8V work voltage
+- 2x20pin 2.0mm pitch Low speed connector
+
+Supported Features
+==================
+
+The Zephyr 96b_nitrogen board configuration supports the following hardware
+features:
+
++-----------+------------+--------------------------------------+
+| Interface | Controller | Driver/Component                     |
++===========+============+======================================+
+| NVIC      | on-chip    | nested vectored interrupt controller |
++-----------+------------+--------------------------------------+
+| RTC       | on-chip    | system clock                         |
++-----------+------------+--------------------------------------+
+| UART      | on-chip    | serial port                          |
++-----------+------------+--------------------------------------+
+| GPIO      | on-chip    | gpio                                 |
++-----------+------------+--------------------------------------+
+| FLASH     | on-chip    | flash                                |
++-----------+------------+--------------------------------------+
+| RADIO     | on-chip    | Bluetooth                            |
++-----------+------------+--------------------------------------+
+| RTT       | on-chip    | console                              |
++-----------+------------+--------------------------------------+
+
+Other hardware features have not been enabled yet for this board.
+See `Nordic Semiconductor Infocenter`_ for a complete list of nRF52-based
+board hardware features.
+
+The default configuration can be found in
+:zephyr_file:`boards/96boards/nitrogen/96b_nitrogen_defconfig`
+
+Pin Mapping
+===========
+
+LED
+---
+
+- LED1 / User LED (green) = P0.29
+- LED2 / BT LED (blue) = P0.28
+
+Push buttons
+------------
+
+- BUTTON = SW1 = P0.27
+
+External Connectors
+-------------------
+
+Low Speed Header
+
++--------+-------------+----------------------+
+| PIN #  | Signal Name | nRF52832 Functions   |
++========+=============+======================+
+| 1      | GND         | GND                  |
++--------+-------------+----------------------+
+| 3      | UART CTS    | P.014 / TRACEDATA[3] |
++--------+-------------+----------------------+
+| 5      | UART TX     | P0.13                |
++--------+-------------+----------------------+
+| 7      | UART RX     | P0.15 / TRACEDATA[2] |
++--------+-------------+----------------------+
+| 9      | UART RTS    | P0.12                |
++--------+-------------+----------------------+
+| 11     | UART TX     | P0.13                |
++--------+-------------+----------------------+
+| 13     | UART RX     | P0.15 / TRACEDATA[2] |
++--------+-------------+----------------------+
+| 15     | P0.22       | P0.22                |
++--------+-------------+----------------------+
+| 17     | P0.20       | P0.20                |
++--------+-------------+----------------------+
+| 19     | N/A         | N/A                  |
++--------+-------------+----------------------+
+| 21     | N/A         | N/A                  |
++--------+-------------+----------------------+
+| 23     | P0.02       | P0.02                |
++--------+-------------+----------------------+
+| 25     | P0.04       | P0.04                |
++--------+-------------+----------------------+
+| 27     | P0.06       | P0.06                |
++--------+-------------+----------------------+
+| 29     | P0.08       | P0.08                |
++--------+-------------+----------------------+
+| 31     | P0.16       | P0.16                |
++--------+-------------+----------------------+
+| 33     | P0.18       | P0.18                |
++--------+-------------+----------------------+
+| 35     | VCC         |                      |
++--------+-------------+----------------------+
+| 37     | USB5V       |                      |
++--------+-------------+----------------------+
+| 39     | GND         | GND                  |
++--------+-------------+----------------------+
+
++--------+-------------+----------------------+
+| PIN #  | Signal Name | nRF52832 Functions   |
++========+=============+======================+
+| 2      | GND         | GND                  |
++--------+-------------+----------------------+
+| 4      | PWR BTN     |                      |
++--------+-------------+----------------------+
+| 6      | RST BTN     | P0.21 / RESET        |
++--------+-------------+----------------------+
+| 8      | P0.26       | P0.26                |
++--------+-------------+----------------------+
+| 10     | P0.25       | P0.25                |
++--------+-------------+----------------------+
+| 12     | P0.24       | P0.24                |
++--------+-------------+----------------------+
+| 14     | P0.23       | P0.23                |
++--------+-------------+----------------------+
+| 16     | N/A         | N/A                  |
++--------+-------------+----------------------+
+| 18     | N/A         | PC7                  |
++--------+-------------+----------------------+
+| 20     | N/A         | PC9                  |
++--------+-------------+----------------------+
+| 22     | N/A         | PB8                  |
++--------+-------------+----------------------+
+| 24     | P0.03       | P0.03                |
++--------+-------------+----------------------+
+| 26     | P0.05       | P0.05                |
++--------+-------------+----------------------+
+| 28     | P0.07       | P0.07                |
++--------+-------------+----------------------+
+| 30     | P0.11       | P0.11                |
++--------+-------------+----------------------+
+| 32     | P0.17       | P0.17                |
++--------+-------------+----------------------+
+| 34     | P0.19       | P0.19                |
++--------+-------------+----------------------+
+| 36     | NC          |                      |
++--------+-------------+----------------------+
+| 38     | NC          |                      |
++--------+-------------+----------------------+
+| 40     | GND         | GND                  |
++--------+-------------+----------------------+
+
+More detailed information about the connectors can be found in
+`96Boards IE Specification`_.
+
+System Clock
+============
+
+nRF52 has two external oscillators. The frequency of the slow clock is
+32.768 kHz. The frequency of the main clock is 32 MHz.
+
+Serial Port
+-----------
+
+96Boards Nitrogen has one UART, which is used as Zephyr console.
+Default settings is 115200 8N1.
+
+I2C
+---
+
+96Boards Nitrogen has one I2C. The default I2C mapping for Zephyr is:
+
+- I2C0_SCL : P0.22
+- I2C0_SDA : P0.20
+
+SPI
+---
+
+96Boards Nitrogen has one SPI. The default SPI mapping for Zephyr is:
+
+- SPI0_NSS  : P0.24
+- SPI0_SCK  : P0.26
+- SPI0_MISO : P0.25
+- SPI0_MOSI : P0.23
+
+Flashing Zephyr onto 96Boards Nitrogen
+**************************************
+
+The 96Boards Nitrogen board can be flashed via the `CMSIS DAP`_ interface,
+which is provided by the micro USB interface to the LPC11U35 chip.
+
+Using the CMSIS-DAP interface, the board can be flashed via the USB storage
+interface (drag-and-drop) and also via `pyOCD`_.
+
+To use ``pyOCD``, install the :ref:`pyocd-debug-host-tools` and make sure they
+are in your search path.
+
+Common Errors
+=============
+
+No connected boards
+-------------------
+
+If you don't use sudo when invoking pyocd-flashtool, you might get any of the
+following errors:
+
+.. code-block:: console
+
+   No available boards are connected
+
+.. code-block:: console
+
+   No connected boards
+
+.. code-block:: console
+
+   Error: There is no board connected.
+
+To fix the permission issue, simply add the following udev rule for the
+NXP LPC1768 interface:
+
+.. code-block:: console
+
+   $ echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules
+
+Finally, unplug and plug the board again.
+
+ValueError: The device has no langid
+------------------------------------
+
+As described by `pyOCD issue 259`_, you might get the
+:code:`ValueError: The device has no langid` error when not running
+pyOCD as root (e.g. sudo).
+
+To fix the above error, add the udev rule shown in the previous section
+and install a more recent version of pyOCD.
+
+Flashing an Application to 96Boards Nitrogen
+============================================
+
+Here is an example for the :ref:`hello_world` application. This
+requires installing the :ref:`pyocd-debug-host-tools`.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_nitrogen
+   :goals: build flash
+
+Run your favorite terminal program to listen for output.
+
+.. code-block:: console
+
+   $ minicom -D <tty_device> -b 115200
+
+Replace :code:`<tty_device>` with the port where the board 96Boards Nitrogen
+can be found. For example, under Linux, :code:`/dev/ttyACM0`.
+The ``-b`` option sets baud rate ignoring the value from config.
+
+Press the Reset button and you should see the following message in your
+terminal:
+
+.. code-block:: console
+
+   Hello World! arm
+
+Debugging with GDB
+==================
+
+You can debug an application in the usual way.  Here is an example for the
+:ref:`hello_world` application. This also requires pyOCD.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_nitrogen
+   :maybe-skip-config:
+   :goals: debug
+
+.. _pyOCD:
+    https://github.com/mbedmicro/pyOCD
+
+.. _CMSIS DAP:
+    https://developer.mbed.org/handbook/CMSIS-DAP
+
+.. _Nordic Semiconductor Infocenter:
+    http://infocenter.nordicsemi.com/
+
+.. _seeed BLE Nitrogen:
+    http://wiki.seeed.cc/BLE_Nitrogen/
+
+.. _pyOCD issue 259:
+    https://github.com/mbedmicro/pyOCD/issues/259
+
+.. _96Boards IE Specification:
+    https://linaro.co/ie-specification

boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig

@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_STM32F4X=y
-CONFIG_SOC_STM32F446XX=y
-
 # Enable MPU
 CONFIG_ARM_MPU=y
 

boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez

@@ -0,0 +1,5 @@
+# Copyright (c) 2018 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_96B_STM32_SENSOR_MEZ
+	select SOC_STM32F446XX

boards/96boards/stm32_sensor_mez/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# 96Boards STM32 Sensor Mezzanine board configuration
+
+# Copyright (c) 2018 Linaro Limited.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_96B_STM32_SENSOR_MEZ
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_96B_STM32_SENSOR_MEZ

boards/96boards/stm32_sensor_mez/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: 96b_stm32_sensor_mez
+  vendor: st
+  socs:
+    - name: stm32f446xx

boards/96boards/stm32_sensor_mez/doc/index.rst

@@ -0,0 +1,247 @@
+.. _96b_stm32_sensor_mez:
+
+96Boards STM32 Sensor Mezzanine
+###############################
+
+Overview
+********
+
+96Boards STM32 Sensor Mezzanine is based on the ST Microelectronics
+STM32F446VE Cortex M4 CPU.
+
+This board acts as a mezzanine platform for all 96Boards CE compliant
+boards. It can also be used as a standalone board.
+
+.. figure:: img/96b_stm32_sensor_mez.jpg
+     :align: center
+     :alt: 96Boards STM32 Sensor Mezzanine
+
+     96Boards STM32 Sensor Mezzanine
+
+Hardware
+********
+
+96Boards STM32 Sensor Mezzanine provides the following hardware components:
+
+- STM32F446VE in LQFP100 package
+- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
+- 180 MHz max CPU frequency
+- 1.8V work voltage
+- 512 KB Flash
+- 128 KB SRAM
+- On board sensors:
+
+  - Temperature/Pressure: STMicro LPS22HB
+  - Accelerometer/Gyroscope: STMicro LSM6DS3H
+  - Magnetometer: STMicro LIS3MDL
+  - Microphone: STMicro MP34DT01
+
+- 3User LEDs
+- GPIO with external interrupt capability
+- UART
+- I2C (2)
+- SPI (3)
+- I2S (1)
+
+Supported Features
+==================
+
+The Zephyr 96b_stm32_sensor_mez board configuration supports the following
+hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | system clock                        |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port                         |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| FLASH     | on-chip    | flash                               |
++-----------+------------+-------------------------------------+
+| SPI       | on-chip    | spi                                 |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
+| PWM       | on-chip    | pwm                                 |
++-----------+------------+-------------------------------------+
+| I2S       | on-chip    | i2s                                 |
++-----------+------------+-------------------------------------+
+
+The default board configuration can be found in
+:zephyr_file:`boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig`
+
+Connections and IOs
+===================
+
+LED
+---
+
+- LED1 / User1 LED = PD10
+- LED2 / User2 LED = PD11
+- LED3 / User3 LED = PD12
+
+Push buttons
+------------
+
+- BUTTON = RST (BT1)
+- BUTTON = USR (BT2)
+
+System Clock
+============
+
+96Boards STM32 Sensor Mezzanine can be driven by an internal oscillator as
+well as the main PLL clock. In default board configuration, the 16MHz external
+oscillator is used to drive the main PLL clock to generate a System Clock
+(SYSCLK) at 84MHz. On the bus side, AHB/APB2 clocks runs at 84MHz, while APB1
+clock runs at 42MHz.
+
+Serial Port
+===========
+
+On 96Boards STM32 Sensor Mezzanine, Zephyr console output is assigned to UART4
+exposed via on-board Micro USB connector. Default settings are 115200 8N1.
+
+The default USART mappings for the remaining ones are:
+
+- USART1: Connected to AP via UART0 on the 96Boards Low-Speed Header.
+        - TX: PA9
+        - RX: PA10
+
+- USART2: Connected to D0(RX) and D1(TX) on the Arduino Header.
+        - TX: PD5
+        - RX: PD6
+
+- USART3: Broken out to Grove connector J10.
+        - TX: PD8
+        - RX: PD9
+
+I2C
+---
+
+96Boards STM32 Sensor Mezzanine board has up to 3 I2Cs. The default I2C
+mapping is:
+
+- I2C1_SCL  : PB6
+- I2C1_SDA  : PB7
+- I2C2_SCL  : PB10
+- I2C2_SDA  : PC12
+
+I2C2 goes to the Groove connectors and can be used to attach external sensors.
+
+SPI
+---
+96Boards STM32 Sensor Mezzanine board has 3 SPIs. SPI1 is used in slave mode
+as the communication bus with the AP. SPI2 is used in master mode to control
+the LSM6DS3H sensor. SPI4 is broken out to Grove Connector J5.
+The default SPI mapping is:
+
+- SPI1_NSS  : PA4
+- SPI1_SCK  : PA5
+- SPI1_MISO : PA6
+- SPI1_MOSI : PA7
+- SPI2_NSS  : PB9
+- SPI2_SCK  : PD3
+- SPI2_MISO : PB14
+- SPI2_MOSI : PB15
+- SPI4_NSS  : PE11
+- SPI4_SCK  : PE12
+- SPI4_MISO : PE13
+- SPI4_MOSI : PE14
+
+PWM
+---
+96Boards STM32 Sensor Mezzanine board exposes 6 PWM channels on the Arduino
+connector. The default PWM mapping is:
+
+- PWM3_CH1  : PB4  : D9
+- PWM3_CH3  : PC8  : D3
+- PWM4_CH3  : PD14 : D6
+- PWM4_CH4  : PD15 : D5
+- PWM9_CH1  : PE5  : D12
+- PWM9_CH2  : PE6  : D11
+
+I2S
+---
+
+96Boards STM32 Sensor Mezzanine board exposes 1 I2S port which is connected
+to the on-board ST MP34DT01 DMIC. The default I2S mapping is:
+
+- I2S2_SD   : PC1
+- I2S2_CK   : PC7
+
+Programming and Debugging
+*************************
+
+Building
+========
+
+Here is an example for building the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_stm32_sensor_mez
+   :goals: build
+
+Flashing
+========
+
+96Boards STM32 Sensor Mezzanine board includes an ST-LINK/V2-1 embedded
+debug tool interface. This interface is supported by the openocd version
+included in the Zephyr SDK.
+
+Flashing an application to 96Boards STM32 Sensor Mezzanine
+----------------------------------------------------------
+
+Here is an example for the :ref:`hello_world` application.
+
+Run a serial host program to connect with your 96Boards STM32 Sensor Mezzanine
+board.
+
+.. code-block:: console
+
+   $ minicom -b 115200 -D /dev/ttyACM0
+
+Build and flash the application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_stm32_sensor_mez
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   $ Hello World! 96b_stm32_sensor_mez
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 96b_stm32_sensor_mez
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _96Boards STM32 Sensor Mezzanine website:
+   https://www.96boards.org/documentation/mezzanine/stm32/
+
+.. _STM32F446VE on www.st.com:
+   https://www.st.com/en/microcontrollers/stm32f446ve.html
+
+.. _STM32F446 reference manual:
+   https://www.st.com/resource/en/reference_manual/dm00135183.pdf